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2012-01-18Unify ID_SECTION_OFFSET and mark it deprecatedPatrick Georgi
We used to put the id section at -0x10, with some boards overriding this to avoid collisions with romstraps. Hardcode the location at -0x80, at the possible expense of some space (0x70 bytes). This also makes the section easier to find in a binary image. At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option is moved to src/Kconfig.deprecated_options. Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/549 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2012-01-07Update geode GX2 tree to match LX.Nils Jacobs
Change-Id: I5b99c531e44ea09990b9da0b97213fb7945f34ee Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl> Reviewed-on: http://review.coreboot.org/512 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-01-05Fix Fam14 AGESA ACPI table generationMarc Jones
The AGESA wrapper init late call generates the SSDT and other ACPI tables. The call was failing without heap space allocated causing the ASSERT messages in the output. I think are there may still be other issues in integrating the SSDT table with the DSDT, but now it is there to debug. The changes were made in Persimmon and copied to the other Fam14 mainboards. Change-Id: I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/517 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-01-05Clean up AMD Fam14 SSDTMarc Jones
The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This fixes some ACPI errors in Linux and Windows bluescreens. The Persimmon acpi_tables.c is where the main changes were made and then replicated in the other Fam14 boards. Please test the other mainbords if you have one. Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/516 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-01-05Fix Fam14 mainboard whitespaceMarc Jones
Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming changes Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/515 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-01-02F14 mainboard: mptable updateKerry Sheh
Add GNB internal graphic interrupt, correct southbridge hd audio device interrupt. and remove the dead code already commented out. south_station, union_station, inagua, persimmon and e350m1 mainboard are included herein. Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59 Signed-off-by: Kerry Sheh <shekairui@gmail.com> Signed-off-by: Kerry Sheh <kerry.she@amd.com> Reviewed-on: http://review.coreboot.org/451 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-01-02F14 mainboard: update acpi interrupt routing in pic and apic modeKerry Sheh
Add interrupt routing for APU GNB internal Graphic and HD audio device, and other pcie bridge device in GNB. south_station, union_station, inagua, persimmon and e350m1 mainboard are included herein. Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b Signed-off-by: Kerry Sheh <shekairui@gmail.com> Signed-off-by: Kerry Sheh <kerry.she@amd.com> Reviewed-on: http://review.coreboot.org/452 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-12-22south_station: Enable GNB hd audioKerry Sheh
Enable HD audio over HDMI. Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed. Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c Signed-off-by: Kerry Sheh <shekairui@gmail.com> Signed-off-by: Kerry Sheh <kerry.she@amd.com> Reviewed-on: http://review.coreboot.org/450 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-12-21Add RS780 defaut graphics ID to AMD Mahogany mainboard.Marc Jones
Added the default ID to the mainboard Kconfig. Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/488 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2011-12-21Persimmon audio codec verb patch.Marc Jones
Verb data is required for the HDA audio codec in the sb800 southbridge. Verb data is not required for mainboards that use G-Series HDMI. It is also a setting the may be boards specific. This fixes issues with Windows audio on Persimmon. Change-Id: I067506871e92078d122cf79872363d8937d47e50 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/490 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-12-14Lenovo X60/T60: add first_battery settingSven Schnelle
The EC allows to select the order in which batteries are (dis)charged. Make this setting available to the user. Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/475 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-14asus k8v-x: explicitly set RAM and bus voltagesFlorian Zumbiehl
Change-Id: I9426cafc252ee765d723af569c4a90e090d313d9 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/482 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-14k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-xFlorian Zumbiehl
Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/481 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-08Change DSDT Table ID for M4A785T-M boardAlec Ari
Change the DSDT Table ID for M4A785T-M from M4A785-M to M4A785T-M. This fixes a small copypasta. This is an updated patch set. Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/474 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-06Fix AMD 8132 and 8151 southbridge buildsKyösti Mälkki
Untested, changes ramstage build for boards: supermicro/h8qme_fam10 amd/serengeti_cheetah amd/serengeti_cheetah_fam10 AMD 8132 was not built for any mainboard due to a typo. AMD Serengeti Cheetah: Chip 8151 is referenced in devicetree.cb but was not built. AMD Serengeti Cheetah Family10: There are indications the board has 8151, but it is not listed in the devicetree.cb. The 8151 chip is not added in the build. Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/471 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-12-03adding support for the Asus K8V-XFlorian Zumbiehl
This pulls it all together and adds the real board-specific code. Confirmed to be working: - IDE - SATA - floppy - USB1.1 - USB2.0 - PS/2 keyboard - PS/2 mouse - serial - parport - sound - ethernet - PCI slots - AGP - powernow - fan speed monitoring - flashrom write Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/390 Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2011-12-03Fix Asus A8V-E SE DIMM slot mappingRudolf Marek
Fix the DIMM mappings, channel 0 is "B" on board, and secondary channel is on 0x51,0x53 Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/449 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02copied asus a8v-e_se to k8v-xFlorian Zumbiehl
Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/389 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-12-02i3100: Add HAVE_HARD_RESETSven Schnelle
and remove it from mainboard/intel/mtarvon, as this function is implemented in the southbridge code. Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/469 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02M4A785T-M: fix ACPI's P-States TableDenis 'GNUtoo' Carikli
Without that fix the linux kernel cannot change the frequency of the CPUs with cpufreq. Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/458 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02Add ASUS M4A785T-M mainboard supportDenis 'GNUtoo' Carikli
This mainboard is very similar to the M4A785-M, but it has DDR3 instead of DDR2. That's why most of the code was copied or included from the m4a785-m directory Notable changes between the two mainboards include: * the selection of the last microcode (mc_patch_010000b6.h) which made it pass the CPU init. * the selection of DDR3 which made it pass the ram init This change was tested with the Trisquel 5.0 GNU/Linux distribution which uses the linux-libre version 2.6.38-12-generic The mainboard boots fine, however some special care is required for the onboard sound CODEC, and the onboard video chip: * the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue is the same than the ASUS M4A785-M mainboard: It causes a flood of interupts which prevents booting * The internal video chip currently requires pci=nocrs, else the graphics are frozen as soon as the radeon module loads, and dmesg would print the following(the card only has 256M, and the mainboard was equiped with 2G of RAM): [ 3.674762] [drm] radeon: 3584M of VRAM memory ready [ 3.679863] [drm] radeon: 512M of GTT memory ready. instead of : [ 45.876088] [drm] radeon: 256M of VRAM memory ready [ 45.876089] [drm] radeon: 512M of GTT memory ready. * The screen(both VGA and HDMI) flickers at high resolution * Sometimes the computer freeze while changing the resolution (even the serial console stops responding) The following peripherals were tested: * The ath9k PCI wireless card was tested * The SATA hard disk works fine * the USB keyboard and mouse work fine * htop see 2 cores * serial port works under coreboot and GNU/Linux * power off and reboot works CPU frequency cannot be changed yet, this is addressed in a new commit. More detail are available here: http://www.coreboot.org/ASUS_M4A785T-M dmesg is available here: http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html The mailing list thread on the graphic problem is here: http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/457 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02Remove obsolete TINY_BOOTBLOCKKyösti Mälkki
Change-Id: I0edc69dc5f95cc32ee648eb094c9e5387f80db47 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/470 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02Change AMD vendorcode buildKyösti Mälkki
Apply the normal method of recursively including subdirectories for src/vendorcode. Remove redundant references under mainboard and northbridge. Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/468 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-01X60/T60: reset baudrate loglevel to sane valuesSven Schnelle
Change-Id: Iaf5861e9db0a41a184da6d2e515e3b9afe0655d6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/459 Tested-by: build bot (Jenkins)
2011-11-18mainboard: Add AMD unionstation RDK supportKerry Sheh
AMD unionstation Reference Design Kit is Designed for hd settop box application. This platform using family14 APU, SB800 southbridge. Vgabios is required, can download vgabios from AMD NDA website. Verified Feature: HDMI, LAN, mini-pcie slots, sata, usb, analog audio and optical fiber digital audio output. Change-Id: Ib1d1d8c889d6fb29f4298b57dfe5c5c1cea1431c Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/434 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-11-18mainboard: Add AMD southstation RDK supportKerry Sheh
AMD southstation Reference Design Kit is designed for NAS application. This platform using family14 RevC0 processor, SB850 southbridge. Vgabios and Promise RAID Option ROM is required for hardware RAID support, can retrieve from the AMD NDA website. Verified feature: HDMI, LAN, usb and mini-pcie slot. RAID0, RAID1 RAID10 and RAID5 upto 6 sata hard drive with ubuntu server 10.10. Change-Id: I16e6f5dab8b0d634e186068c81436db77fb4475a Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/433 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-11-09Fixed whitespace and indentationOskar Enoksson
Code style fixes for the hp/dl145_g1 system board code. Change-Id: I3c1a175d954e2d340e82c03c9f984699dcff865e Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/428 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-08Cleanup Persimmon mainboard whitespace.Marc Jones
Change-Id: I389bde86c5583a4fb37a699162b65b475ed94ddc Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/427 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-07Added RAMINIT_SYSINFO and declared the necessary structsOskar Enoksson
Using RAMINIT_SYSINFO should be beneficial for this platform. It is also more clean/safe to put data in struct mb_sysconf_t. It's more consistent with other MB's and I've tested it thoroughly on my DL145. Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be Reviewed-on: http://review.coreboot.org/236 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-06Fix typoPatrick Georgi
Change-Id: I195ea15ddbc725091e32191fac3b84d01b456580 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/410 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-02simplify IDE cable detection for Asus M2VFlorian Zumbiehl
Change-Id: If8e4dcf405e24b744ac34f581c5609fcce96fd07 Signed-off-by: Florian Zumbiehl <florz@florz.de> Reviewed-on: http://review.coreboot.org/371 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-01remove trailing whitespaceStefan Reinauer
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/364 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01Remove XIP_ROM_BASEPatrick Georgi
The base is now calculated automatically, and all mentions of that config option were typical anyway (4GB - XIP_ROM_SIZE). Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/366 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-30remove usbdebug.h include from mainboard/romstage codeSven Schnelle
No romstage is supposed to use usbdebug functions/defines directly, so remove all those includes. The usb code is now called and setup from console code. Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/354 Tested-by: build bot (Jenkins)
2011-10-30asus/m5a88-v: Fix buildPatrick Georgi
We added some new flag for certain AMD boards after support for this board was submitted. Also integrate the mptable refactorings that happened in the meantime. Change-Id: I50cf50f343a740832fd1a14a2a1ef5b903315675 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/353 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-10-28Add ASUS M5A88-V mainboard supportQingPei Wang
it's a AMD 880+800 mainboard. I port the code based on the AMD reference code. update: 1.use CIMX instead of pmio 2.fix some whitespace 3.fix subsystemid of devicetree.cb Change-Id: I9725ccdbb25365c4007621318efee80b131fec29 Signed-off-by: QingPei Wang <wangqingpei@gmail.com> Reviewed-on: http://review.coreboot.org/205 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n. This might break a couple of boards on runtime, but so far, fixes were quite simple. There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be adapted. Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28siemens/sitemp_g1p1: Add more devices to PIR and MP tablePatrick Georgi
Linux 2.4 is happier that way Change-Id: I016609ae1e004ec856e8223893352dcdd061b291 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/346 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28T60: remove redundant usbdebug_init call()Sven Schnelle
called from console code, no need to call it here. Change-Id: I4c34f89c82cc2478db8de4e98584e69d7ab0ca82 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/350 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27Move linux 2.6.11 workaround to generic codePatrick Georgi
Linux 2.6.11 seems to require a certain order in CPUs listed in mptable, so enforce it. This was only done on arima/hdama, but now is generic. Unfortunately this is somewhat slow. Change-Id: I85715ebae8a009cb816bc9ffd6372708f246bf66 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/280 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27X60/T60: enable AHCI modeSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Change-Id: I2166ae9ee9e7e0e431583249f015d130d15fac61 Reviewed-on: http://review.coreboot.org/341 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25X60: enable Cx power saving modesSven Schnelle
Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/331 Tested-by: build bot (Jenkins)
2011-10-25T60: add _CST tableSven Schnelle
Used by power management code to enable Cx powersaving modes. Change-Id: I02c6b10762245bc48f21a341286236e203421de0 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/322 Tested-by: build bot (Jenkins)
2011-10-25T60: enable C4onC3 modeSven Schnelle
It is safe to enable this setting on these Boards. Change-Id: Iaa7377117743d18a95c496c25abf9fb4a1b20ad9 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/330 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25T60: use ICS954309 clock driverSven Schnelle
Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/328 Tested-by: build bot (Jenkins)
2011-10-25X60/T60: remove superflous h8_set_audio_mute()Sven Schnelle
muting is handled by h8 code, no need to do it here. Change-Id: I3f152e99f30701cd032b03105cbe3ae778865305 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-23SB800: Hide unused gpp portsKerry Sheh
Add configure option SB_GPP_UNHIDE_PORTS for mainboard to hide/unhide the unused sb800 gpp ports. Certain gpp port should be hidden, if no device was detected and hotplug feature is disabled for such port. Hidden unused ports makes lspci -vvv get more accurate information under Linux. Test on avalue/eax-785e mainboard. Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-21Remove redunancy in KconfigKyösti Mälkki
Socket Kconfig unconditionally selects CPU_INTEL_CORE. Change-Id: I5eb7dd17047a2a031dd7345390d7f5f756055e18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/307 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-20T60: Add support for Ultrabay Legacy I/O devices (40Y8122)Sven Schnelle
Those modules have basically the same Super I/O capabilities as the Docking station. Unfortunately, the Super I/O in the module shares the same I/O address as the Docking station, so we're not allowed to connect the LPC Docking Bus if such a module is present. To be able to detect this device and use it as early console for coreboot, we have to initialize the GPIO Controller before, as this device is detected via GPIO06. Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/282 Tested-by: build bot (Jenkins)
2011-10-19asrock/e350m1: Enable the superio ACPI device in devicetree.cbPeter Stuge
This makes the power_on_after_fail NVRAM option work correctly. Change-Id: I96f05f82d7f133b343cf8d4ef09db50a3db7a83d Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/292 Tested-by: build bot (Jenkins)
2011-10-17Re-worked devicetree.cb for DL145 G1Oskar Enoksson
After a lot of experimentation this commit improves some hardware features that were not recognized or incorrectly configured before. The only thing not tested is SCSI-option board (I dont have one). Misleading errors in comments have been corrected. (Note BTW that the DL145 G1 mainboard is identical to AMD Serenade which was supported in early versions of coreboot but was dropped for some reason.) Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: Ibbd97fafad22196b1e18d0b257731490339f113e Reviewed-on: http://review.coreboot.org/237 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Refactor option rom initialization code in coreboot.Stefan Reinauer
- move int15 handler out of the generic code into the mainboard directories of those mainboards that actually use it. - move vbe headers to vbe.h - move function prototypes used in native oprom code to x86.h Change-Id: Idfff5e804ea328f7b5feebac72497c97329320ee Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/255 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Use default table creator macro for all SSDTsStefan Reinauer
Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/262 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13siemens/sitemp_g1p1: Don't mess with virtual wire settingsPatrick Georgi
That function broke SMP on Linux 2.4, now it works. Change-Id: I4ddd25fef57bed64877959ca96cca68170042bca Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/243 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13siemens/sitemp_g1p1: Get rid of bus_isa and bus_typePatrick Georgi
Each variable is essentially unused or incorrect. Change-Id: I4d2a10c9b45306ac6e6026a31765d3b912fd855c Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/242 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor mptable generation some morePatrick Georgi
The last couple of lines of every mptable function were mostly identical. Refactor into common code, a new function mptable_finalize. Coccinelle script: @@ identifier mc; @@ ( -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); | -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); -return smp_next_mpe_entry(mc); +return mptable_finalize(mc); ) Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/246 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Get rid of fixup_virtual_wirePatrick Georgi
As stated in some code files, fixup_virtual_wire was established to avoid touching 200 invocations of the mptable code. Let Coccinelle do it: @@ type T; identifier v; @@ -void fixup_virtual_wire(T v) -{ ... } @@ expression A; identifier v; @@ -v = smp_write_floating_table(A); +v = smp_write_floating_table(A, 0); @@ expression A; identifier v; @@ -v = smp_write_floating_table(A, 0); -fixup_virtual_wire(v); +v = smp_write_floating_table(A, 1); Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/245 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13mptable: Refactor lintsrc generationPatrick Georgi
We copied pretty much the same code for generating mptable entries for local interrupts (with some notable exceptions). This change moves these lines into a generic function "mptable_lintsrc" and makes use of it in many places. The remaining uses of smp_write_lintsrc should be reviewed and replaced by mptable_lintsrc calls where possible, and smp_write_lintsrc made static. This patch was generated using Coccinelle: @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @@ expression mc; expression isa_bus; @@ -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0); -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, isa_bus); @m@ identifier mc; expression BUS; @@ -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin)); ... -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); +mptable_lintsrc(mc, BUS); Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/244 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13Make Asus A8V-E SE better ACPI citizen.Rudolf Marek
Use the SSDT autogen infrastructure to support the automatic reserved resources, automatic P-state generation and automatic _CRS PCI0 method. Change-Id: Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/251 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-12avalue/eax-785e: Get SATA Mode from Kconfig optionKerry Sheh
Change-Id: I67aab3ba7de85337e2cf83b6d1be63cb04bf0fcd Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/233 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12persimmon: complete the sb800 devicetreeKerry Sheh
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. So the missing sb800 USB3 devicees was add to the mainboard devicetree. Because of no physical usb connector connected to USB3, the USB3 device setting was off. Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/232 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11mainboard: complete the sb800 devicetree even device is offKerry Sheh
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2 enable_dev() function. If the devicetree don't have this device, then sb_Before_Pci_Init will not get called. Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/230 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-11persimmon: sb800 sata mode configure updateKerry Sheh
persimmon configure sb800 sata mode according to the southbridge kconfig selection. Change-Id: I44a9c36ca68b4a0e1086f04c4338d3a5f536fdca Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/227 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-03TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platformsenok71
The hp/dl145_g1 motherboard did not work since commit 1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (svn 6124). That commit added TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process stopped very early (no console output whatsoever). The same symptom was reported on other AMDK8 based boards with amd8111 southbridge chips. This commit seems to fix the bug. It adds a bootblock.c under src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the problem was that enum_ht_chains needs to be called before the southbridge bootblock.c function, not after. Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4 Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/235 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-21Use ACPI text fields consistently with all other boardsStefan Reinauer
LXBIOS and LXB-DSDT are not used in other parts of the tree. Make names consistent across the tree. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43 Reviewed-on: http://review.coreboot.org/224 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-17Persimmon doesn't have HDMI so the GNB HD Audio should be disabled.Marc Jones
Change-Id: Ic960fe09fbed2c8a31c7c9ac2c54f6c88efebed3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/219 Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com> Tested-by: build bot (Jenkins)
2011-09-17Enable SATA AHCI for faster boot with SeaBIOS.Marc Jones
Change-Id: Ibd87422680350c112eabe1bb73b237031c3e9d6b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/220 Tested-by: build bot (Jenkins) Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
2011-09-16Persimmon updates for AMD F14 rev C0efdesign98
These are the changes for the AMD Persimmon mainboard required to support the update of the AMD Family 14 cpu to rev C0. There are many warning fixes; the agesa- wrapper.c file has been changed to fix the amdinitlate and amdlaterunaptask routines, and more. Change-Id: I6de43379a2819cea5169db5f21d4841f9a4942a7 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/137 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15AMD Inagua platform updatesefdesign98
These changes update the Inagua platform. The changes include modifying the Kconfig to suggest video bios and ahci rom implementations, changing the dimm spd code to use the correct bus addresses, cleaning up the makefile a bit, and fixing a duplicate definition warning associated with the BIOS_SIZE value. Change-Id: Idab88dda48f08877dbbd2de3136bdf0e54e31247 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/136 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15AMD Torpedo platform updatesefdesign98
This update fixes warnings and supports as necessary the Agesa infrastructure changes required to support the AMD Family 14 cpu update to rev C0. Change-Id: Ib08b49695b925b81f796bf299141fe6f845fdef8 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/138 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14Update to Asrock E350m1 for AMD F14 C0efdesign98
This updates the E350m1 Agesa wrapper code to fix an issue with AmdLateRunApTask. It now passes the function parameter through to the Agesa routine. There is also a change to the platform_cfg.h file that makes the definition of BIOS_SIZE dependent on whether or not it was defined earlier. Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/139 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14mainboard: add avalue/eax-785 ITX mainboardKerry She
It's AM3 Socket, 880M + SB850 chipset, similar with advansus/a785e-i. Onboard device UART, VGA, SATA, PCI Slot, 2 X16 PCIe slot, 4 X1 Pcie slot, Lan, audio, PS2 keyboard/mouse and USB are verified. Change-Id: I483363f5ff9fbfc5cda2f0521660751212f3e326 Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/208 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-12Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methodsTobias Diedrich
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2 uses the same acpi wakeup vector as S3. Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink the power LED while sleeping. acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because it is used in both romstage and ramstage after patch 3/3, whereas i82371eb_early_pm.c is used only in romstage. I used the name acpi_get_sleep_type instead of acpi_is_wakeup_early because I think acpi_is_wakeup_early is a bit misleading as a name since it doesn't return a boolean value. Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the added check for acpi_slp_type == 2 (resume from S2) should not change behaviour of other boards: northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type; northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0; northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3; northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0; southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type; southbridge/via/vt8237r/vt8237r_lpc.c:238: acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; southbridge/via/vt8237r/vt8237r_lpc.c:239: printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/188 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07AMD SB800 southbridge updateKerry She
This patch enables access to the registers of the hardware monitor logical device in the superio via isa ports 0x295/0x296. Previously this was not enabled in the SB8xx LPC device. This is required for initialisation in init_hwm() in src/superio/winbond/w83627hf/superio.c and also by OS-level sensor monitoring such as lm-sensors to access temperature, fan monitoring and control and voltage registers. asrock/e350m1 and advansus/a785e-i mainboard changes are included herein. Change-Id: I2176885549277b335c0c41b48457d09b9b76b703 Signed-off-by: Per Hansen <perh52@runbox.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/159 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07AMD F14 southbridge updateKerry She
This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein. Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Signed-off-by: Kerry She <kerry.she@amd.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/135 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-04Disable dev3 on ma78gm-us2hWang Qing Pei
Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot. Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/187 Tested-by: build bot (Jenkins)
2011-08-26X60/T60: remove obsolete dmi.hSven Schnelle
Change-Id: Id0e8bcc1b93a629f0620b84a060d7ff99a82de78 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/174 Tested-by: build bot (Jenkins)
2011-08-26Add automatic SMBIOS table generationSven Schnelle
Change-Id: I0ae16dda8969638a8f70fe1d2e29e992aef3a834 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/152 Tested-by: build bot (Jenkins)
2011-08-25Minor ma785gmt clean-upAlec Ari
Change-Id: I9e889a6c475fb3283fa11f8b3de5baaf54235589 Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/167 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-25Fix up various dsdt.asl filesAlec Ari
Change-Id: I46eb27847deb3a903ac9af347992a9954e50ff6e Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/166 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-24Remove dead codeAlec Ari
Remove dead code, copy and pasted from tilapia's mainboard.c file into various asus mainboard.c files Change-Id: Ic715ccaad8ac0210401d4a99ecb11e943f6afe58 Signed-off-by: Alec Ari <neotheuser@ymail.com> Reviewed-on: http://review.coreboot.org/168 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-18X60: use EC events 0x50/0x58 instead of GPIO GPE for Docking/UndockingSven Schnelle
Change-Id: I674e5166f5fb7ba299e6f1231f30434a5bf731c5 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/161 Tested-by: build bot (Jenkins)
2011-08-09Do not compile nuvoton superio for all boardAlexandru Gagniuc
The nuvoton WPCM450 code is compiled for all boards regardless of whether or not they use it. Compile it only for boards needing it. Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/129 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-08-06ms7135: add ACPI supportJonathan A. Kollasch
Change-Id: I64a74d3dc0ea2d006ed4b25657d531fb243c2993 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-04Add voltage control of southbridge and RAM on ms7135Jonathan A. Kollasch
Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-03Remove debugging code, or convert it to be selected by kconfigJonathan A. Kollasch
Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/130 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-03Use preferred style of fixed-width integer typesJonathan A. Kollasch
Change-Id: I1abaaa2af4de940584039f9b8c348bb57fb611e0 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/125 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-22Add xhcbios and ahcibios rom handlingefdesign98
This change adds xhci and ahci bios rom handling that is similar to the vgabios rom handling in the arch/x86 Makefile.inc to the Persimmon and Torpedo mainboards. It also adds the basis for AHCI BIOS rom handling to the Persimmon Kconfig. Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/109 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Add the SuperMicro H8QGI platformefdesign98
This set adds support for the SuperMicro H8QGI mainboard. It is a publicly available 4 socket board using AMD Family 10 cpus and AMD SR5650 and SB700 bridges. Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/108 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22Update AMD SR5650 and SB700efdesign98
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-16Workaround the errata #181.Rudolf Marek
We use LDTSTOP# to trigger the FID/VID change on K8M890, because the FID/VID SMAF is blocked by not yet configured internal VGA. The memory controller is enabled later, nor the workaround makes any harm to non-affected CPUs. This update unbreaks compilation by declaring the tmp variable. Change-Id: Icf5d126b8c8cd9ece6af41d3129315a777c8cef2 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/69 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-14Move AMD SB800 early clock setup.Scott Duplichan
Move the AMD SB800 early clock setup code that is needed for early serial port operation from mainboard/romstage.c to sb800/bootblock.c. This prevents code duplication and simplifies porting. Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/96 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-13Enable SMI on M2V-MX SERudolf Marek
Finally the SMI routines are in good shape on AMD, lets enable this and later implement ACPI on/off SMI commands. Change-Id: I9848a7be908780353eead30c16fd2df8ea48f77e Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/83 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-07-11T60: enable GPIO before using GPIO I/O port rangeSven Schnelle
Change-Id: I39369e6f8a39f53f58a4b7fbe357637a79f5b596 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/93 Tested-by: build bot (Jenkins)
2011-07-11T60: dont use X60 USB init flagSven Schnelle
ec byte 0x03, bit 2 seems to be only used on the X60s for USB switch initialization. Don't touch it on T60. Change-Id: Icb89a514757a0e06ccea200fde62a778fa8c268e Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/92 Reviewed-by: Peter Stuge <peter@stuge.se> Tested-by: build bot (Jenkins)
2011-07-10ASRock E350M1: ACPI-related BSOD fixScott Duplichan
On installing/starting Windows (tested with Win7 Ultimate) the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error. From Scott Duplichan: To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT must be corrected. The attached patch does this. It uses the older patching method, and not the (possibly preferred) AML generation method. To simplify the patching operation, I moved the AML item 'TOM1' to the start of the SSDT. The patch also includes code to confirm the AML variable TOM1 is at the expected offset before patching. Also tested & working with Linux. Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/91 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-07T60: handle EC events in SMM if ACPI is disabledSven Schnelle
Change-Id: I6f9e90015cafef3da896453ef8e3588434ae3554 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/89 Tested-by: build bot (Jenkins)
2011-06-29Added support for Aaeon PFM-540I RevB PC104 SBCMark Norman
The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU. More infomation about the board available at www.aaeon.com. Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd Signed-off-by: Mark Norman <mpnorman@gmail.com> Reviewed-on: http://review.coreboot.org/30 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-29amd southbirdge sb800 wrapper, pci bridge fixKerry She
sb800 pci bridge SHOULD enabled by default according to the chipset document, but actually not enabled on some mainboard. enable sb800 pci bridge when told to enable in devicetree.cb. tested on ibase persimmon mainboard. Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3 Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/63 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28Add the AMD Torpedo mainboardefdesign98
The Torpedo mainboard is the reference platform for the AMD Family 12 cpus and the AMD Hudson-2 (SB900) southbridge. Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/54 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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