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2021-08-30mb/google/brya/var/felwinter: Update gpio tableEric Lai
Based on latest schematic to update the gpio table. BUG=b:197308586 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0d91199ffd2128a136ea0a33dfe7affa77ae61d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-30mb/google/brya/var/felwinter: Update device treeEric Lai
Based on latest shcematic to update the device tree. BUG=b:197308586 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I59601571c5e4c2d19738cb333605fb22e1ea0d2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-30mb/google/brya: Enable TCSSDeepti Deshatty
Enable flag SOC_INTEL_COMMON_BLOCK_TCSS. BUG=b:187385592 TEST=type-C pendrive/Gen-2 SSD detected as Super speed. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ie3cb8b8836b17fa00ab0089d03fca9f22c4d702e Reviewed-on: https://review.coreboot.org/c/coreboot/+/54090 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/google/dedede/var/driblee: Configure thermal sensor settingFrank Wu
According to schematics, TSR2 thermal sensor is not present in driblee. BUG=b:191732473, b:197180925, b:195868075 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I343a6161f71f66b77d23f1fa2f581aaee5eddf1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57091 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30mb/google/dedede/var/driblee: Configure audio settingFrank Wu
Update the combination audio CS42L42 and amp. MAX98360. BUG=b:195619349, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I264c680ed5638b71c912253a38c27152a9015d4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-28mainboard/intel/harcuvar: Remove hardcoded lapic 0 from devicetree.cbMariusz Szafrański
This change follows other Intel SoCs common way to support SKUs with bsp lapic_id != 0 by removing hardcoded lapic 0 from devicetree.cb and allowing its detection at boottime. It completes support for HCV/DNV after base SoC patch: commit ba936ce5db819d5ecb34e83a998b2390ecbdc4b9 soc/intel/denverton_ns: Ensure CPU device has a valid link Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/ "A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)." Change-Id: I88f60f64d2beb2768ec9833de582d7901f456b11 Signed-off-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-28mb/google/{dedede,hatch}: Remove unneeded documentationFelix Singer
This documentation doesn't add any more value. Thus, remove it. Change-Id: I0402bc736c6cc77d88a836bddce8eadae8ec5d7c Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the default by changing its enum value to 0 and remove its configuration from all related devicetrees. If `common_soc_config.chipset_lockdown` is not configured with something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT` is used. Also, add a release note for the upcoming 4.15 release. Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-28mb/google/brya/variants/primus: update USB 2.0 controller Lane ParameterCasper Chang
Modify USB 2.0 port5 parameter to improve SI diagram measurement. BUG=b:187992881 TEST= Pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I1eff05a7ad6563898744c24f9657e28625319873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28mb/google/dedede/var/drawcia: Add fw_config probe for ALC5682-VD/ALC5682-VSWisley Chen
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:194356991 TEST=ALC5682-VD/ALC5682-VS audio codec can work Change-Id: I71b824c42c13cc2a8bebe0072de4a65ce238f074 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/dedede/var/boten: Generate SPD ID for supported partstanley.wu
Add supported memory part in the mem_parts_used.txt and generate the SPD ID for the part. The memory part being added is: MT53E512M32D1NP-046 WT:B BUG=b:194223174 BRANCH=dedede TEST=Build the boten board. Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I36fcbf7333fd9e85b28baa64676f8435aca63889 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/brya/var/anahera: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E1G32D2NP-046 WT:A H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR MT53E512M32D2NP-046 WT:E H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B BUG=b:197850509 TEST=build pass Change-Id: Ib7bdab1396138d728ae053c30656a9c80dddaff8 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-28mb/google/dedede/var/driblee: Configure I2C ports and touchpadFrank Wu
Update the I2C ports and touchpad based on the schematic. BUG=b:195622489, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I8778ad6564e526e029c46c36c78e38f764e3c6b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56998 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/driblee: Configure USB port settingsFrank Wu
Update the USB port configuration based on driblee schematic. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 1 USB2 [3]: None USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: None USB2 [7]: None USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: None BUG=b:195622487, b:191732473 BRANCH=keeby TEST=FW_NAME="driblee" emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id9f4f8db98cb20db1c3936c65689a847a7802b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56997 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/(amd,google): Update SPI Kconfig settings based on devicetreeMartin Roth
This takes the devicetree SPI settings and moves them into Kconfig. BUG=b:195943311 TEST=boot guybrush & majolica and verify spi settings. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed Reviewed-on: https://review.coreboot.org/c/coreboot/+/56885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/brya: Add two sensors for DPTF functionalitySumeet Pawnikar
Add two thermal sensors for fan and wwan for DPTF based thermal control. BRANCH=None BUG=b:181271666 TEST=None Change-Id: Idc9bd6040c9bb316ec7e314f5e9c937c75cfc95a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com>
2021-08-28mb/intel/adlrvp_m: Enable touchscreenBernardo Perez Priego
This will add ACPI information to enable WACOM touchscreen. TEST=Boot DUT and issue command: $ ls -al /sys/bus/i2c/devices WACOM PWB-D893 device should be listed and touchscreen should be functional. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I37c0831485135fda3284dda6b61f4825b7fc51a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-28mb/google/dedede/var/corori: Generate RAM ID and SPD fileIan Feng
Add the support RAM parts for Corori. Here is the ram part number list: DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) K4U6E3S4AA-MGCR 0 (0000) lp4x-spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR BUG=b:196744958 BRANCH=keeby TEST=emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ia11b5db145deeea838a8f5949accdb11e13342f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56988 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure thermal sensor settingIan Feng
According to schematics, TSR2 thermal sensor is not present in corori. BUG=b:197281317 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Id69f9d6ace738ef1e792addd782d05c2d03d2b3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57110 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure I2C ports and touchpadIan Feng
1. Support Elan touchpad. 2. Follow schematic to disable I2C1, I2C2 and I2C3. BUG=b:197052531 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Ideef57c275432e21f8580d4c5c937909b168d91f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57031 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure audio settingIan Feng
Select the drivers for ALC5682 codec and MAX98360A spk amp BUG=b:197037090 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I0659a05fbcc28702d922a23d74885ba65a4254f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57015 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure USB port settingsIan Feng
Follow schematic to modify USB port settings. USB2 [0]: USB Type C Port 0 USB2 [1]: None USB2 [2]: USB Type A Port 0 USB2 [3]: None USB2 [4]: None USB2 [5]: Camera UFC USB2 [6]: None USB2 [7]: Integrated Bluetooth USB3 [0]: USB Type C Port 0 (M/B side) USB3 [1]: None USB3 [2]: USB Type A Port 0 (M/B side) USB3 [3]: None BUG=b:196998272 BRANCH=keeby TEST=FW_NAME="corori" emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I2045b2be9d79bfd394fa4520faa0fb552a704206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57010 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-28mb/google/dedede/var/corori: Configure GPIO settingsIan Feng
Updated the GPIO pins based on the latest schematic. BUG=b:196867404 BRANCH=keeby TEST=FW_NAME=corori emerge-keeby coreboot Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I683a7da4fcb2e4e0efdb3547b1de15796c6b55e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-28mb/google/brya: Create anahera variantWisley Chen
Create the anahera variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:197850509 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ANAHERA Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Id7649d56a8d6f85d12208f7ddaf2f71a7fe98e8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-27mb/google/butterfly: Put braces around `else` branchAngel Pons
Ensure braces are consistent on all branches of a conditional statement, as per the coding style. Tested with BUILD_TIMELESS=1, Google Butterfly remains identical. Change-Id: I34f3b22486e0f0712bc248477acb43012b21c5ee Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-27mb/amd/majolica/Kconfig: add EFS SPI settingsFelix Held
This keeps the default of EFS_SPI_SPEED at 66.66Mhz for the non-EM100 case, but switches the EFS_SPI_READ_MODE setting from Dual IO (1-1-2) to Quad IO (1-1-4) for the non-EM100 case. This patch adds a special config for the EM100 emulator case that has limited SPI frequency support. Tested on Majolica by Martin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8996c2bf606ccd21686092beac8d96b22c0b7869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56815 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27broadwell: Drop weak `mainboard_fill_spd_data` definitionAngel Pons
Make `mainboard_fill_spd_data` mandatory and adapt mainboards to define this function accordingly. Change-Id: Ic18c4c574e8c963bbb41c980f43bdbacc57735af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55806 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/intel/broadwell: Move `mainboard_fill_spd_data`Angel Pons
Move the `mainboard_fill_spd_data` function out of romstage, in preparation to confine `pei_data` usage to as few files as possible. Change-Id: I6447da4d135d920f9145e817bfb7f9056e09df84 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55805 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27Broadwell boards: Do not assign unused SPD addressesAngel Pons
The `pei_data` struct is already zero-initialised. Change-Id: If539cddc007f32a04389bc3b3b06c43cb5c86e10 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55804 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/auron: Refactor memory-down SPD handlingAngel Pons
Variants only need to provide the SPD index and whether said index corresponds to a dual-channel configuration, which can be achieved without using `pei_data`. Add two functions that return the values and use them in `spd.c` at mainboard level. Change-Id: I9bc4527057d4a771883c8cc60da2501516d6fb94 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-08-27mb/google/brya/variants/primus: Enable SaGv supportAriel Fang
This patch enables SaGv support for primus. BUG=b:196286180 Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: I00074e348dd6347602c18dcfd231a890153b4685 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-27mb/intel/adlrvp: Enable SaGv supportV Sowmya
BUG=b:187446498 TEST=Boot and verify memory trains at all the SaGv points through FSP debug logs. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I883ae50b07e7b1d5554763fd79079d40b264b721 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-08-27mb/google/cherry: Support audio codec RT1011Trevor Wu
Add GPIO "rt1011 reset" and i2c2 initialization for RT1011. Add CHERRY_USE_RT1011 and CHERRY_USE_RT1019 to Kconfig, so we can spearate code for the specific codec by config. Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Change-Id: I18939a2a2caae0444ce17f4712764647975121ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/57157 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/dedede/var/driblee: Configure GPIO settingsFrank Wu
Updated the GPIO pins based on the latest schematic. BUG=b:191732473, b:195619827 BRANCH=keeby TEST=FW_NAME=driblee emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I20baeb6b13c8c0a70c7555aa8f7f5557768c0083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56996 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/dedede/variant/drawcia: Include SPD for MT53E512M32D1NP-046 WT:BWisley Chen
Add SPD support to drawcia for MT53E512M32D1NP-046 WT:B. This part is already in global_lp4x_mem_parts.json.txt, and use /util/spd_tool/lp4x/gen_part_id to assigns DRAM IDs. BUG=b:196951879 BRANCH=firmware-dedede-13606.B TEST=FW_NAME=drawcia emerge-dedede coreboot chromeos-bootimage Change-Id: Ic42e6357943ba651ffd92fb2974e9ea52fa19020 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56905 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27mb/google/dedede/var/sasukette: Add FW_CONFIG probe for EXT_VRZhi Li
commit df520855 (soc/intel/jsl: Add disable_external_bypass_vr config) Add FW_CONFIG probe for don't stuffing ANPEC APW8738BQBI IC. BUG=b:190727416 BRANCH=dedede TEST=test for enter S0ix and resume normally by powerd_dbus_suspend Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: I15ab30f14df9dc02157009091aa8398e2fa75188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56804 Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26mb/google/octopus: add CBI SKU RAM ID 5Sheng-Liang Pan
add CBI sku RAM ID 5 for 4GiB Capacity with dual channel and dual rank with 4gb dram density. BUG=b:178665760 BRANCH=Octopus TEST=build fw and flash to the dut with RAMID 5, dut can boot up successfully. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I922a518cffc4dac71caec68e6f7a55c6c5717438 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56982 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26mb/google/dedede/var/bugzzy: Configure USB portsSeunghwan Kim
Override USB port configurations based on the latest bugzzy schematics. BUG=b:192521391 BRANCH=None TEST=Built test coreboot image Change-Id: I4368946f4175f4f065a3483dc7ca6068c6de3123 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-26mb/google/var/redrix: Correct the WWAN_PERST_L settingWisley Chen
WWAN_PERST_L (GPP_E0) is wrongly configured to NC in ramstage. So, remove it. BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: If8e96045a0d78a942f77d8d8e371ab75dff0c202 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-26mb/google/brya/variant/redrix: Correct MAX98390 AMP settingWisley Chen
4 MAX98390 Speaker Amps are connected to i2c0 and device addresses are 0x38/0x39/0x3a/0x3b BUG=b:191931762 TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Ie8f01e6a7e09e18f6d34f3ceb1db8e2e238197bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/57114 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26device/mipi: Move to drivers/mipiJulius Werner
Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-26mb/google/guybrush: Create dewatt variantBhanu Prakash Maiya
Create the dewatt variant of the guybrush reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:196460993 BRANCH=None TEST=util/abuild/abuild -p none -t google/guybrush -x -a make sure the build includes GOOGLE_DEWATT Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Change-Id: I57860a7cad1bf202bd3ef3eed5f498fbf1d29af8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57108 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25mb/roda/rv11/acpi: Use lower case format for hex valuesFelix Singer
Change-Id: I3bea9e1f9cc25a4476ddbaa8bd8e434609eb28f7 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-25mb/roda/rv11/acpi: Use Printf ()Felix Singer
Change-Id: Iec6ec8bbf3cc5c9230ba6bcb0126ff6085f26464 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-25mb/google/brya/variants/gimble: Correct I2C slave address and update gpio.cMark Hsieh
1. According to the Maxim's comment and schematic diagram of proto, Modify I2C slave address to 0x38, 0x3c. 2. According to the schematic diagram of proto, Change GPD11 to NC. BUG=b:191811888, b:1191213263 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ibf8adf2ed8dda9ae6da06e7e995bef9395cdee35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57059 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25mb/google/dedede/var/galtic: modify touchscreen to native I2C protocolFrankChu
Touchscreen will be no function with R93-14092.19.0 image or be later. It just happened to work because elants_i2c driver would bind to the device first based on "ELAN0001" HID ID BUG=b:195994810 TEST= verify only update RW FW can fix touchscreen no function issue 1.Build test firmware 2.prepare DUT enviroment (R93 image + update RW to test firmware) 3.verify touchscreen function normally Signed-off-by: FrankChu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ie9e0fe726854d0128ad1bb430544640dc8f034ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/57011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
2021-08-25mb/google/dedede/var/sasukette: Update DPTF parametersZanxi Chen
Update DPTF parameters from internal thermal team. BUG=b:180875580 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: I06d8a543dbd77137cb97c4ea695a1f2b9f8ee76c Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57116 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-25mb/goog/bry/var/redrix: Enable Genesys GL9755 settingWisley Chen
BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I45ecab8c036a7e75cc0c564867119c027175ed06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-25mb/google/brya/primus: modify HID to MX98357A to enable audio functionCasper Chang
Primus has MX98360A, which Linux kernel 5.10 currently does not support and, therefore, audio does not work. As the device is compatible with the MX98357A, use that until Linux’ SoF driver supports the new version (https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268). BUG=b:194749863 BRANCH=none TEST=build coreboot and audio function works Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I893d9a31dc2c7726599c150be01b9585fb6c8a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-25mb/google/brya: Fix PL4 limitsTim Wawrzynczak
Commit e7f3e6a0558 added PL4 limits for brya0, but the units were mW, whereas the `tdp_pl4` field is expected to be in whole Watts, therefore divide all of the settings by 1000. BUG=b:197468828 TEST=boot brya0 to OS Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6da6bae4eb8c83188d813828cdc4f7c1e20f1b5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-08-24mb/google/brya/variants/kano: Init devicetree for kanoDavid Wu
Init basic override devicetree based on schematics BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I283517427612e24eabe2ce736d677253065c7859 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24mb/google/brya: Enable SaGv supportV Sowmya
This patch enabled the SaGv support for brya0 baseboard. BUG=b:187446498 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I2a71e159fa49f677660af8279f2b582a3916eee2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for primusMalik_Hsu
Enable DRIVERS_GENESYSLOGIC_GL9755 support for primus. BUG=b:195611000 BRANCH=None TEST=build pass Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I0c60979a2d42f836e0f0261c42fcfc36c41e113a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24mb/google/dedede/var/cret: Add new G2Touch touchscreenDtrain Hsu
Add G2Touch G7500 touchscreen into devicetree for cret. BUG=b:180547621 BRANCH=dedede TEST=Built cret firmware and verified touchscreen function. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I57638bf8a3eb4efcd819f5433fa54c22b7af3054 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-24mb/google/brya/var/felwinter: Generate RAM ID and SPD fileEric Lai
Add the support RAM parts for felwinter. Here is the ram part number list: DRAM Part Name ID to assign K4U6E3S4AA-MGCR 0 (0000) K4UBE3D4AA-MGCR 1 (0001) H9HCNNNBKMMLXR-NEE 0 (0000) MT53E1G32D2NP-046 WT:A 2 (0010) BUG=b:197308861 BRANCH=None TEST=emerge-brya coreboot Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I76febefc251b02a047819242e23c02dc50891c2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24Revert "soc/intel/broadwell/pch: Replace ACPI device NVS"Furquan Shaikh
This reverts commit 68d8357dab55660058ad1ab8dca34fd03e0adbb5. Reason for revert: Device NVS is expected by mainboard samus in payload depthcharge: https://chromium.googlesource.com/chromiumos/platform/depthcharge/+/932c6ba2704987c0db64dbdfe03c158482c7ab11/src/board/samus/board.c#60 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Icb5fa6da3412a51aae56c3658163e5b98d57bab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-23mb/google/hatch: Create moonbuggy variantRehan Ghori
Create the moonbuggy variant of the puff reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=191356135 BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_MOONBUGGY Signed-off-by: Rehan Ghori <rehang@google.com> Change-Id: Iaf545dcd5ff537afdf029f510553d16a1239763e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-23mb/google/dedede: add gooey variantstanley.wu
gooey is the same design as boten, and differs only in replacing Cr50 with discrete TPM. BUG=b:193366710, 197247706 TEST=FW_NAME=gooey emerge-keeby coreboot Signed-off-by: stanley.wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I2a54f872a7d5c0bee76a9e6e309613d9357b380b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-23mb/google/guybrush: Enable PCIe L1 SubstatesMatt Papageorge
This change enables L1.1 and L1.2 on all real Guybrush PCIe devices. BUG=b:188123142 TEST=Boot to ChromeOS and verify L1SS are functional by dumping the settings with "lspci -vv". Leave system on for 20 minutes and no hang. Also perform 20 reboots and suspend operations Cq-Depend: chrome-internal:4012927 Change-Id: I40d19be78bfcb9a30fb59f48530a4413dadbefbc Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-23mb/google/dedede/var/bugzzy: Configure GPIO settingsSeunghwan Kim
Override GPIO pad configurations based on the latest bugzzy schematics. BUG=b:192521391 BRANCH=None TEST=Built test coreboot image and boot on bugzzy board Change-Id: I7c3580e7eb34efed0441ead243343d2d7875d50f Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-22mb/google/brya/var/brya0: Align comments in overridetreePaul Menzel
Change-Id: Id3eb18cae2dd9a7b148bc9f3dcaf387f35dbd2fb Fixes: 312fb716 ("mb/google/brya: Add ALC1019_NAU88L25B support") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-08-22AGESA f15tn: Factor out common OptionsIds.hAngel Pons
Subsequent commits will add Kconfig options to configure IDS. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: I861762280b274566ce14969a30e2e0c98e120a69 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-08-22AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED`Angel Pons
The `ASSERT` macro is already defined in `src/include/assert.h`, and AGESA's definition is never used. On Asus A88XM-E, toggling the value of the `IDSOPT_ASSERT_ENABLED` macro does not change the resulting binary when using reproducible builds. Attempting to use AGESA's definition of the `ASSERT` macro results in build errors: In file included from src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c:56: src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuDmi.c: In function 'GetType4Type7Info': src/vendorcode/amd/agesa/f15tn/Include/Ids.h:371:33: error: statement with no effect [-Werror=unused-value] #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE)); Given that coreboot's definition of `ASSERT` is more useful, drop AGESA's broken definition and the useless `IDSOPT_ASSERT_ENABLED` macro. Also remove the `IdsAssert` function, as it is no longer used anywhere. Tested with BUILD_TIMELESS=1, Asus A88XM-E remains identical. Change-Id: Ia4e5dbfd3d2e5cec979b8b16fbc11d1ca8a0661e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-08-22AGESA f15tn boards: Sync IDS option valuesAngel Pons
In preparation to replace OptionsIds.h with Kconfig options, use the same settings on all AGESA f15tn boards. The only difference this makes is that the `IDS_LATE_RUN_AP_TASK` macro no longer expands to nothing. It is expected that the impact this difference makes is minimal. Note that the `IDSOPT_TRACING_ENABLED` option currently fails to build. Tested on asus/f2a85-m, still boots. Change-Id: Iedd4d1f255650012f3efd9a27718e18c1c904dc1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53982 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-20qualcomm/sc7180: Switch to common MIPI panel libraryJulius Werner
This patch changes the sc7180 boards to use the new common MIPI panel framework, which allows more flexible initialization command packing and sharing panel definitions between boards. (I'm taking the lane count control back out again for now, since it seems we only ever want 4 for now anyway, and if we ever have a need for a different lane count it's not clear whether that should be a property of the board or the panel or both. Better to leave that decision until we have a real use case.) Also, the code was not written to deal with DCS commands that were not a length divisible by 4 (it would read over the end of the command buffer). The corresponding kernel driver seems to pad the command with 0xff instead, let's do the same here. (Also increase the maximum allowed command length to 256 bytes, as per Qualcomm's recommendation.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I78f6efbaa9da88a3574d5c6a51061e308412340e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56966 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-20mb/google/brya: Add ALC1019_NAU88L25B supportEric Lai
Add ALC1019_NAU88L25B DB support. BUG=b:195891240 TEST=audio is functional when playing youtube. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9209c4cab00fc03b2a6107b5c32804786cd2e242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-20mb/google/zork: only enable RTD2141 when presentPeter Marheine
An MST hub is only present on some devices that are configured with a particular daughterboard indicated by EC fw_config, so add a fw_config probe that matches the USB daughterboard ID from CBI to only enable it on devices where present, using variant-specific daughterboard IDs. BUG=b:185862297 TEST=RTD2141 remains in ACPI tables on a berknip with Dali DB, and is not present on the same system if probe is changed to enable it for picasso DB. BRANCH=zork Change-Id: I4ada9b492ab221fa98350bf2faf27a23342f3a55 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2021-08-19mb/intel/adlrvp: Drop INTEL_CAR_NEM Kconfig select on ADL-P RVPSubrata Banik
This patch enables eNEM flow for Alder Lake SoC hence drop INTEL_CAR_NEM Kconfig from ADL-P RVP. ALDERLAKE_CAR_ENHANCED_NEM Kconfig will select all relevant Kconfig required to enable eNEM for Alder Lake. Additionally, select INTEL_CAR_NEM Kconfig for ADL-M RVPs from Kconfig.name. BUG=b:168820083 TEST=Able to build and boot ADL-P RVP using eNEM mode. Change-Id: I08561c8f50bbc4afe2bcdff4cc50e74d8fa2f68e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48345 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19soc/intel/alderlake: Move INTEL_CAR_NEM selection from SoC to mainboardSubrata Banik
This patch decouples the selection of eNEM feature enablement from SoC to ensure the ADLRVP does the validation first prior enabling this feature on OEM/ODM reference designs. BUG=b:168820083 TEST=No changing is being observed in .config with and without this CL. Change-Id: I709185159d9869501b1d8e8d00f6d25ec77838bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19mb/google/dedede/var/driblee: Generate RAM ID and SPD fileFrank Wu
Add the support RAM parts for Driblee. Here is the ram part number list: 1. Hynix H9HCNNNBKMMLXR-NEE 2. Micron MT53E512M32D2NP-046 WT:F 3. Samsung K4U6E3S4AA-MGCR 4. Micron MT53E512M32D1NP-046 WT:B BUG=b:195619346 BRANCH=keeby TEST=emerge-keeby coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I683acb91ec13cbd772e732d7f81152ceb3cefc1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56924 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19mb/google/brya: set tcc_offset value to 10Sumeet Pawnikar
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature. This value is suggested by Thermal team. BUGb=b:195706434 BRANCH=None TEST=Built for brya platform and verified the MSR value Change-Id: I22573e8ca935d99a16b0876768df169db4e61c4d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57000 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19mb/google/brya/variants/primus: Fix GL9755S power sequenceMalik_Hsu
- Enable EN_PP3300_SD - Configure SD_PE_RST_L correctly BUG=b:195625340 TEST=Able to boot with SD card Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I33c17e88cabdc9b13634fc8f341aa6a09b7bfde5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19mb/google/brya: Enable ADL_ENABLE_USB4_PCIE_RESOURCES for primusMalik_Hsu
primus supports USB4 and so needs to reserve bus numbers and prefmem and mem resources for potential hotplugs of devices. BUG=b:193377625 BRANCH=None TEST=build pass Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Change-Id: I1d1f8cc3460c1b89dade4f01690c77efcd799098 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19google/trogdor: Read SKU ID as binary-first base3 strappingJulius Werner
We're running out of SKU IDs in the base2 system, so convert it to binary-first base3. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia7f749fa042d3eac76bfe1e74531905c6e279ad2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57004 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-18mb/google/dedede/var/sasukette: Add fw_config probe for ALC5682I-VD & VSZhi Li
Update the `_HID` value of device in SSDT depending on the fw_config. According to value of AUDIO_CODEC_SOURCE field in fw_config(SSFC) which stored in CBI: AUDIO_CODEC_ALC5682: _HID = "10EC5682" /* ALC5682I-VD */ AUDIO_CODEC_ALC5682I_VS: _HID = "RTL5682" /* ALC5682I-VS */ BUG=b:193623380 BRANCH=dedede TEST=ALC5682I-VD or VS audio codec can work normally Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Ic8840454e4934162ea59c742634a56f70b153238 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
2021-08-18mb/google/guybrush: Enable STT in device treeJason Glenesk
Enable Skin Temperature Tracking with initial configuration settings. BUG=b:190732595 TEST=Confirm that AGT tool can successfully complete data collection Change-Id: I37b5da1b56586ef75ad17f6766cd00ddac87aa5a Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55434 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-18device: Move MIPI panel library from mainboard/google/kukui into commonJulius Werner
All boards that are trying to use MIPI panels eventually run into the problem that they need to store physical parameters and a list of DCS initialization commands for each panel, and these commands can be very different (e.g. a large amount of very short commands, a few very large commands, etc.). Finding a data format to fit all these different cases efficiently into the same structures keeps being a challenge, and the Kukui mainboard already once put a lot of effort into designing a clean, flexible and efficient solution for this. This patch moves that framework into a common src/device/mipi/ library where it can be used by other boards as well. (Also, this will hopefully allow us to save some duplicated work when using the same panel on different boards at some point.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I877f2b0c7ab984412b288e2ed27f37cd93c70863 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-08-17mb/google/octopus/var/phaser: Change IRQ trigger method to levelJoey Peng
The change from Synaptics S7817 to Elan 3915N and pin distribution of touch IC is the same. The original Elan section was copied from reference design and was never used before. According to vendor spec definition IRQ trigger method needs to change to level. BUG=b:190574692 TEST=Build coreboot and check that device works Change-Id: I44ee779242779c78ceafdddd34dca2571e714dd3 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56380 Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-17mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 WT:BWisley Chen
Add SPD support to lantis for MT53E512M32D1NP-046 WT:B BUG=None BRANCH=firmware-dedede-13606.B TEST=FW_NAME=lantis emerge-dedede coreboot chromeos-bootimage Change-Id: I22c50a55dd3b8bbda64ba1b607c8b22cc6592f98 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-17mb/google/dedede/var/cappy2: Fix the DUT with cirrus codec PLT failSunwei Li
irq(ACPI_IRQ_LEVEL_LOW) -> ACPI_DESCRIPTOR_INTERRUPT -> IO-APIC, will assert interrupt frequently; irq_gpio(ACPI_GPIO_IRQ_EDGE_BOTH) -> ACPI_DESCRIPTOR_GPIO -> INT34C8; will not assert interrupt frequently; Because IRQ configuration can't be setted to both EDGE trigger. BUG=b:195635555 BRANCH=dedede TEST=Cirrus audio codec PLT pass Signed-off-by: Sunwei Li <lisunwei@huaqin.corp-partner.google.com> Change-Id: I65bca519f75af84848284f039b6ad67cb1887823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56973 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16trogdor: Fix "TPM interrupt" lb_gpio to be ACTIVE_HIGHJulius Werner
"Latched" GPIOs like this one are a virtual representation of the pending interrupt flag for the edge-triggered pin and not a direct representation of line state, so they should always be marked ACTIVE_HIGH or depthcharge will incorrectly negate them. This has always been wrong and meant that depthcharge doesn't correctly wait for Cr50 flow control responses on these platforms. Thankfully it doesn't seem like we've seen any practical issues from this, but it's still very wrong. BRANCH=trogdor BUG=none TEST=Booted CoachZ (no visible difference) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ie1586b0e10b64df0712e28552411c4d540a7e457 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
2021-08-16mb/google/guybrush/var/baseboard: Set Clk request for WLAN/SD/WWAN/SSD devicePatrick Huang
Setting the clock source depends on clock request pin for WLAN/SD/SSD device. Also turn off the unused (4/5/6) clock sources. In guybrush, clock source 0/1/2/3 are routed for WLAN/SD/WWAN/SSD device. BUG=b:186384256 BRANCH=none TEST=Verify the config setting can update to the GPPCLKCONTROL registers. Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: I240543e92cbc178cee034c37d7c26da0a6bbb7f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56895 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cbMAULIK V VAGHELA
For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC IDMAULIK V VAGHELA
coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56954 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/intel/adlrvp_m: Enable CR50 TPM support over SPIThejaswani Puta thejaswani.putta@intel.com
Add Kconfig options and enable TPM device in devicetree BUG=None TEST=Booted the image and checked the successful TPM communication in verstage,romstage & ramstage from coreboot logs. Signed-off-by: Thejaswani Puta thejaswani.putta@intel.com <thejaswani.putta@intel.com> Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-08-16mb/google/dedede: Create driblee variantFrank Wu
Create the driblee variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:191732473 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DRIBLEE Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I1ad9a4e0cf7999337b55d62d5cc94e4f6c2e98f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-16mb/google/dedede: Create corori variantIan Feng
Create the corori variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:194356176 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CORORI Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I8380d5aab61c99d545625789ff1251ec1caa84a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56796 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/google/poppy/variants/atlas: stop setting touchscreen probed=1Matthew Blecker
All Atlas devices have the touchscreen controller, so probing for its presence is unnecessary. Removing the probe requirement allows the touchscreen ACPI device in Linux to re-enumerate when rebinding its I2C adapter device. Without this change, after rebinding the touchscreen's I2C adapter device using sysfs the touchscreen ACPI and HID devices are absent, and the touchscreen is unresponsive. With this change, the touchscreen ACPI and HID devices are re-created after rebinding its I2C adapter device, and the touchscreen becomes responsive again. BUG=b:177350937 TEST=Tested on 2 Atlas DUTs running Chrome OS R94 top-of-tree builds with Linux 4.4 and 5.4. Built new AP FW from Atlas Chrome OS firmware branch with this change applied. Tested shipping RO + new RW, and new RO + new RW. Test sequence: 1) Boot DUT, verify basic touchscreen functionality. 2) $ cd /sys/bus/platform/drivers/i2c_designware 3) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}} lrwxrwxrwx. 1 root root 0 Aug 12 01:07 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6 drwxr-xr-x. 4 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00 drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002 drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw/hidraw1 4) $ echo i2c_designware.0 > unbind 5) Verify touchscreen is unresponsive (as expected after unbind). 6) $ ls -ld i2c_designware.0 ls: cannot access 'i2c_designware.0': No such file or directory 7) $ echo i2c_designware.0 > bind *** Without this change: *** 8) Touchscreen remains unresponsive. 9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00}} ls: cannot access 'i2c_designware.0/i2c-6/i2c-ACPI0C50:00': No such file or directory lrwxrwxrwx. 1 root root 0 Aug 12 01:18 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 4 root root 0 Aug 12 01:18 i2c_designware.0/i2c-6 *** With this change: *** 8) Touchscreen is functional again. 9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}} lrwxrwxrwx. 1 root root 0 Aug 12 01:09 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6 drwxr-xr-x. 4 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00 drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003 drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw/hidraw1 Signed-off-by: Matthew Blecker <matthewb@chromium.org> Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db Reviewed-on: https://review.coreboot.org/c/coreboot/+/56928 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/google/brya/var/redrix: Generate SPD ID for supported partsWisley Chen
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I61377e6cdd3af9d6d80b9e1e68191b39f43358ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/56969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya: Add I2C parameterEric Lai
Add I2C parameters to make sure each bus speed is around 390kHz. BUG=b:188793264 TEST=Measure by scope. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib47228b8684c44f6acfec9e9e4b6e7b18ba6f6c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya/variants/kano: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for kano BUG=b:192370253 TEST=FW_NAME=kano emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4d6099fa8d17bebf798ddf236a68886087e2a95e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya: Configure EN_FCAM_PWR to highVarshit B Pandya
Recent change "7a8c68a: mb/google/brya: Configure H21 as GPO and A17 as low" turned EN_FCAM_PWR low since EN_FCAM_PWR is turned ON and OFF by IPU driver while MIPI UFC probing. However USB UFC also requires 3.3V which is enabled by A17. This caused USB UFC enumeration to fail BUG=b:196014678 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I88c204ec07b1f7511f0d88074e336cfc9116a7d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56882 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16mb/google/brya/primus: Fix G2 touchscreen reset GPIO polarityCasper Chang
modify reset_gpio as active low to meet touchscreen spec BUG=b:195490284 BRANCH=none TEST=build coreboot and touchscreen works Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I7ce1b3025db8abebf5693b34da846a7e969246fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/brya: allow MKBP devices and disable TBMC deviceBoris Mittelberg
Enable MKBP (Matrix Keyboard Protocol) interface for all Brya family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:170966461 TEST=manual test on Brya P1: Volume Up/Down buttons Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ic9c707f57871f388c363e01c9ab78a3b358ce728 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-16mb/google/guybrush: Update GPIOs for fingerprint MCUMartin Roth
Add mainboard finalize and shutdown call to match zork. Deassert EN_PWR_FP in bootblock, power up correctly in finalize. | Phase | SOC_FP_RST_L | EN_PWR_FP | S3 resume | |-----------|--------------|-----------|----------------------| | Bootblock | **Low** | **Low** | Maintain High / High | | Romstage | Low | Low | Maintain High / High | | Ramstage | Low | **High** | Maintain High / High | | Finalize | **High** | High | | | Shutdown | **Low** | **Low** | | BUG=b:191694480 TEST=Build, verify GPIO configuration. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iaae5feec60abb2480777d1f99174254c5132bb43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-15mb/google/brya: set PL4 value dynamically for thermalSumeet Pawnikar
Set PL4 value dynamically for brya board based on CPU SKUs which is detectable at runtime. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000) Change-Id: I20b98ccd8493ed238de647cda8ceb25f62029133 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-15mb/google/brya/{redrix,taeko}: Deduplicate lockdown configFelix Singer
Lockdown configuration is done in their baseboards. Thus, remove the setting from the variants overridetree. Change-Id: Iadb1201718466503987e4f6bd72bf711a2d3128e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-13mb/google/guybrush: Create nipperkin variantKarthikeyan Ramasubramanian
Create the nipperkin variant of the guybrush reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=None BRANCH=None TEST=util/abuild/abuild -p none -t google/guybrush -x -a make sure the build includes GOOGLE_NIPPERKIN Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie525ea501e6c3d5d94e67c1db1d4e307fb7ccba7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56921 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-13mb/google/brya/variants/brya0: add PL4 values for different SKUsSumeet Pawnikar
Add PL4 values for brya0 board for different CPU SKUs. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 with below messages, On brya (282): Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000) PL4 (100000) On brya (482): Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000) PL4 (105000) Change-Id: I095e9eda6665fd1927f35ee57d52922eddd8227a Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-13mb/google/guybrush: update USB 2.0 Lane Parameter settings for USB port5Ivy Jian
Tune the USB phy settings to update TXVREFTUNE0/COMPDISTUNE0 to higher value for USB port 5 (Type-A). BUG=b:194053549 TEST= Pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Id1ede34bdbee0c1f9f7d10fc7ffbc9648af31e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56925 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>