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This change adjusts all I2C speed to lower then 400KHz. The rise_time_ns
and fall_time_ns values for each port are capured by a scope.
BUG=None
BRANCH=dedede
TEST=built and verified adjusted I2C speed < 400KHz
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I9504608dd8d9a5f5a3848ef34691557942c21023
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add ELAN touchscreen support for magneto.
BUG=b:203122673
TEST=Build and verify that touchscreen works.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Update charger performance control table of DPTF for bugzzy.
Since the EC change chromium:197776876 modified maximum charging current
to reduce skin temperature, this change adjusts the charging performance
table with the modified value.
BUG=b:197776876
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=None
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Ie967ef7fbc19886c631e634a0b0c3f2cf1e490af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This drops VBOOT_NO_BOARD_SUPPORT.
There is little impact of always having recovery_mode_switch()
implemented in bootmode.c. A weak write_protect_state() is not
necessary as there is no BOOT_DEVICE_SPI_FLASH with the emulation.
Call to fill_lb_gpios() is already guarded with CONFIG(CHROMEOS)
so the weak implementation would not be referenced.
Change-Id: I3c00b30c5233ae3556b7622f97c3166668c8ab12
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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When MMIO functions are available, the pci_s_* functions do exactly
the same thing. Drop the redundant pci_mmio_* versions.
Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Avoid indirect <vc/google/chromeos/chromeos.h> as the
files really only need <security/vboot/vboot_common.h>.
Change-Id: Ic02bd5dcdde0bb5c8be0e2c52c20048ed0d4ad94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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SPI speed override is not related to ChromeOS, thus the
location in chromeos.c was poor choice.
Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Return 0 instead of -1 in case of error. Both values indicate an error
has happened. Adapt `cpu_bus_scan()` accordingly.
Change-Id: I0f83fdc41c20ed3aae80829432fc84024f5b9b47
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I882c567e6bca0982a0d3d44c742777c4d7bd5439
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add NOR-Flash drivers to pass verification of flash at verstage.
TEST=boot to romstage
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iee3dd336632b0cf998f5f7c1d118e01e8270e815
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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This patch sets the enable the external voltage rails since taeko
board have V1p05 and Vnn bypass rails.
BRANCH=None
BUG=b:204832954
TEST=FW_NAME=Check in FSP log and run PLT test
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I20ff310d48d3e7073fe5e94d03d29cc55a46d1f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Type C port2 uses EC mux port0 as per schematics.
BUG=b:204230406
TEST=No error message in depthahrge.
update_port_state: port C2: get_usb_pd_mux_info failed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.
Change-Id: I329efcb42a444b097794fde4f40acf5ececaea8c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
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Add OEM product names from public sources.
Change-Id: Ic051aa9c8afabd47e7e9f6ac878190d9904ef757
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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All the mainboard variants of mc_ehl do not use the external switches
for the bypass rails. Disable the matching UPDs and all the low power
modes of the PMC.
Change-Id: I08f4effe5c4d5845bed01dfe1bd1251c58012b7f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58895
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to get a reliable real-time performance disable all P-States
for all mc_ehl based mainboard.
Change-Id: I22857cc0f1476483ca82c1c872e4519e4b350ea9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Disable all C-states other than C0/C1 for CPU and package.
Change-Id: I2c163f859dab4b0dc02896c70122e993cdd3db72
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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There are a bunch of devices in the devicetree that are disabled in
FSP-S and not used on this board. Having them around in the devicetree,
even if disabled, is not necessary and leads to a message in the log
(left over static devices...check your devicetree).
This commit cleans up devicetree.cb and removes all unused and disabled
devices.
Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58887
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently link_speed_capability is not specified within the DXIO
descriptors sent to FSP. This value specifies the maximum speed that
a PCIe device should train up to. The only device on Monkey Island that
is not currently running at full speed is the NVME but this may not
always be the case.
BUG=b:204791296
TEST=Boot to OS and check link speed with LSPCI to verify
NVME link speed goes from 2.5 GT/s to 5 GT/s
Change-Id: Ibeac4b9e6a60567fb513e157d854399f5d12aee9
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1)
Set GPIO GPP_S0 ~ GPP_S3 to NF4 and GPP_R6 ~ GPP_R7 to NF3.
BUG=b:204844177 b:202913826
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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All of these names came from public sources.
Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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As a prevention of Row-Hammer attacks enable the FSP-M parameter
'RhPrevention'.
Change-Id: I52f68525e882aee26822d9b3c488639c00f27d17
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This configures GPIO GPP_G5 as an input pin for SD card detect.
Change-Id: I708eb112fa054f2f88857001c409fb62493b6206
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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PCIe root ports #4 (00:1c.3) and #6 (00:1c.5) are currently not used on
this mainboard and are not routed either, so remove them from the
devicetree completely. PCIe root port #7 (00:1c.6) is connected and
used. Add the missing settings for L1 substates and latency reporting to
disable these features for this port as well.
Change-Id: I47e8528bea993ed527a0aecdbc93b94bbd9a7a49
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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On mc_ehl2 there are currently four of the six PCIe clocks used to drive
PCIe devices. None of the used clock output is dedicated to a special
device. Therefore do not use a port mapping of the clocks to avoid a
stopping clock once a device is missing and the matching root port is
disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free
running clock.
In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.
Change-Id: I81419887b7f463a937917b971465245c1cb46b94
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
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Setting the PM_ESPI_CS_USE_DATA2 bit in PM_SPI_PAD_PU_PD results in the
eSPI transactions being sent via the SPI2 pins instead of the SPI1 pins.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed
that the native function names don't have the EMMC_ prefix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The HECI device needs to be enabled to send the commands to have the
CSME change between Soft Temporary Disable mode and Normal mode.
Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Use the `AZALIA_RESET` macro, write hex values in lowercase and remove
redundant comments. Also express verb length in decimal.
Tested with BUILD_TIMELESS=1, Purism Librem 15 v4 remains identical.
Change-Id: Id9f5ff9614a8f8c0b7f3a3c633a1dcdda8c5876c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Rewrite the HDA configuration using macros for clarity.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I987a41329425a5c8c7169a7fa66a34de5742532e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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BUG=b:204272905
BRANCH=master
TEST=emerge-trogdor coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ie13ddfef6adfd53adb0a0d3a98995fb00b8a45e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add mainboard folder and drivers for new reference board 'Corsola'.
TEST=build pass
BUG=b:200134633
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe
devices. None of the used clock output is dedicated to a special device
(CLK0 drives several devices on the mainboard, CLK1 and CLK2 are
connected to a PCIe switch). Therefore do not use a port mapping of the
clocks to avoid a stopping clock once a device is missing and the
matching root port is disabled. Instead set the mapping to
'PCIE_CLK_FREE' to have a free running clock.
In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.
Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58740
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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https://tech-docs.system76.com/models/oryp8/README.html
Tested with TianoCore (UeifPayloadPkg).
Working:
- PS/2 keyboard, touchpad
- Both DIMM slots
- Both M.2 SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack*
- S3 suspend/resume
- Booting to Pop!_OS Linux 21.10 and Windows 10 20H2
- Flashing with flashrom
Not working:
- Discrete/Hybrid graphics
Not tested:
- Thunderbolt functionality
- S/PDIF output
Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I55a827f8d6a5421c36f77049935630f4db4ba04d
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ia277b3ad50c9f821ab3e1dcb8327314ba955fa79
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie203883cc9418585da4f9c7acd89e7624234caf1
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I25464d3a2dd02e613a8392db90b1eaf0f9b3ca70
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ib455951d1d26ddfa010d4eb579905235bd1385a9
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I6d8a97d71ff3b4408f5e11230ed3ff00357f7123
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Id00a45a6a6acf0880934c55f1a3f18e63f2aed43
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The Oryx Pro 6 has the same board layout as the next model in series,
Oryx Pro 7. The primary difference between the two is the dGPU (20
series to 30 series). Convert oryp6 to a variant setup in preparation
for adding the oryp7.
Change-Id: I976750c7724d23b303d0012f2d83c21a459e5eed
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This reverts commit 287cc02c007fd47b515d19389ea00ea0461fd5a1.
Reason for revert: it will break s0ix.
BUG=b:201266532
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable MKBP (Matrix Keyboard Protocol) interface for all volteer family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.
BUG=b:171365305
TEST=manual test on Volteer:
Volume Up/Down and Power buttons, Tablet Mode switch
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I2bb2e895af17fa4280113e57e2b0ca780af8840e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO
can be used to check EC status
trusted (LOW: in RO) or untrusted (HIGH: in RW).
Branch=none
Bug=none
Test=Issue manual recovery and confirm DUT is entering recovery mode on
ADL-M RVP.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Update guybrush STT (Skin Temperature Tracking) configuration settings
to values provided by power team after tuning.
BUG=b:203123658
Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Our boards do not boot if power_on_after_fail=Disable. Drop the option
and use the default of powering on.
Change-Id: Ia1857e52f838337048f79f8ca5c12d669cae321a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Currently, the address size field of AT24 NVM is incorrect, and
Linux v5.10 kernel logs the message below:
at24 i2c-PRP0001:01: Bad "address-width" property: 14
The valid size of the AT24 NVM is 16 bits so modify the value from
0x0E to 0x10.
TEST=Boot brya and check the kernel log and see "Bad address-width"
error message is not shown.
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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In order to let the ec passing the key event like recovery and power key
to the OS, we need to include EC_ENABLE_MKBP_DEVICE to generate the MKBP
device.
BUG=b:204519353, b:204512547
BRANCH=None
TEST=pressed recovery key and power button in the OS and checked the UI
behavior.
Change-Id: Ia1d0b9b301994ad9a0f4bf28b75ab0310a1d63a0
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this
mainboard and are not routed either, so remove them from the devicetree
completely. PCIe root port #7 (00:1c.6) is connected and used. Add the
missing settings for L1 substates and latency reporting to disable these
features for this port as well.
Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58568
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are a bunch of devices in the devicetree that are disabled in
FSP-S and not used on this board. Having them around in the devicetree,
even if disabled, is not necessary and leads to a message in the log
(left over static devices...check your devicetree).
This commit cleans up devicetree.cb and removes all unused and disabled
devices.
Change-Id: Ia5ffb382e3524e61b8583aca801063942fe2f247
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Hynix H5ANAG6NCJR-XNC
2. Micron MT40A512M16TB-062E:R
3. ADATA 4JQA-0622AD
BUG=b:199469240
BRANCH=firmware-zork-13434.B
TEST=FW_NAME=vilboz emerge-zork coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I57cca403800d9731a7b689ac9773a7940e83904e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS
field, as newer Intel platforms do.
Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS"
BUG=b:202463494
BRANCH=dedede
TEST=ALC5682I-VD or VS audio codec can work normally
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: Ib808ddadef1029d3f06eb2d68164243c386d4905
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Some brya0 units have HPS fitted and connected to PCH I2C2, rather than
a user-facing camera.
Because HPS uses I2C address 0x51, which may conflict with the
user-facing camera EEPROM, introduce a new fw_config bit to indicate
whether HPS is present.
BUG=b:202784200
TEST=FW_NAME=brya0 emerge-brya coreboot chromeos-bootimage
TEST=ectool cbi set 6 0x28191 4 # set bit 17 for HPS
TEST=flashrom -p internal -w image-brya0.serial.bin
Signed-off-by: Dan Callaghan <dcallagh@google.com>
Change-Id: I322548bcfccf16ba571396bc88fd6fc03c036a4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58646
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable DRIVERS_GENESYSLOGIC_GL9755 support for brask.
BUG=b:197385770
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If421e0df058b6f2b87267d5e3822940b90062f71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add probe function for the "VS" version of the audio amplifier so taeko
can recgonize MAX98357 with ALC5682I_VS.
BUG=b:202913837
TEST=FW_NAME=taeko emerge-brya coreboot and check taeko can recgonize
MAX98357 with ALC5682I_VS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Id4ff2003ee6a6f6f4ad98694996689e1a84092c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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Add wifi sar for kracko
BUG=b:194460420
TEST=emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage
Change-Id: I83bca544c9f71142f95ea1137f732c182b3f29b7
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
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GPP_B14 is used by buzzer and should be set to NF1 'SPKR'.
BUG=b:198998974
TEST=emerge-brask coreboot depthcharge and verify if the buzzer beeps.
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I84978af152a7117c1f3398a9b7adde161db058dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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With cr50 fw 0.3.22 or older version, it needs to disable autonomous
GPIO power management and then can update cr50 fw successfully.
BUG=b:202246591
TEST=FW_NAME=anahera emerge-brya coreboot chromeos-bootimage.
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I9137b6264ee80bc9e00dfdc3ab3926bccb4bf47c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M
BUG=b:201266532
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If6783e0df1404c9a353061fb564210aa0d12896e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Set the `PcieRpLtrEnable` option to enable the LTR capability on all PCH
PCIe root ports.
TEST=Verify LTR capability enabled in `DevCap2` using `lspci -vv`
Change-Id: I07ea37d178ea61d904c4f131fdea31479e899ef3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58326
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Map each PCIe clock source to the corresponding root port. Also, correct
the CLKREQ# mapping for clock sources not associated to any CLKREQ# pin.
The default `PcieClkSrcClkReq` value of 0 corresponds to CLKREQ# 0.
TEST=Check that Linux sees the same PCIe devices with this commit:
- All 5 onboard Ethernet NICs
- BMC
- Two random graphics cards in PEG0 and PEG1 slots
- M.2 M NVMe SSD
Change-Id: I0515877a36d42fb8858a0f0b3c0af1199a18d9af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Correct the PCIe clock source configuration as per the schematics.
Apparently, FSP does not turn off unused PCIe clock sources when using
SPS (Server Platform Services) firmware, but it does when using CSME
firmware.
TEST=BMC and Ethernet NICs get detected when using CSME firmware.
Change-Id: Id25a34816f512510640db95251a7a792c1eebe62
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This reverts commit 0a1602217fd0d60c59a497cb83a23b44cf4973d9.
EC region is required in order to provide unified coreboot image for
Chrome and Windows SKU RVP's. Also removing EC region causes a regression
for ADL-P platforms.
With this patch EC region is included back into flash map.
Change-Id: I0f7f2b5dd392b08e1978a3b3f3236eac0dab1f12
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Add fw_config probe for MIPI OVTI2740 camera
BUG=b:194926283
TEST=FW_NAME=kano emerge-brya coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ic5a7cebf1f5c847c01e951a237af691e0ad6c73d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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BUG=b:202784200
TEST=FW_NAME=taeko emerge-brya coreboot chromeos-bootimage
Signed-off-by: Dan Callaghan <dcallagh@google.com>
Change-Id: I400719d762b001811f809f9549fd030dff9928d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Not all platforms need to generate power resources, but the code does
not get optimized out at build time because the devicetree gets
compiled into a linked list. As this code pulls in some heavy ACPI
dependencies that is even implemented with weak empty function it
makes sense to optimize out this code using a Kconfig constant.
This saves 1.5K in ramstage size on gigabyte/ga-945gcm-s2l.
Change-Id: I82289aa7e6e82318417f3b827b86182891dfc2a6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58657
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, the AMD SDLE stardust test fails with incorrect VDD/SOC
scale/offset value, it needs to update the two load line slope
settings for the telemetry.
AGESA sends these values to the SMU, which accepts them as units of
current. Proper calibration is determined by the AMD SDLE tool and the
Stardust test.
VDD scale: 92165 -> 73457
VDD offset: 412 -> 291
SOC scale: 30233 -> 30761
SOC offset: 457 -> 834
BUG=b:200194315
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
pass AMD SDLE/Stardust test
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: If53c173000a276a80247ccb08736280a25948939
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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EN_PWR_FP is used to enable power to the FPMCU. This frees up GPIO_32
for other uses.
This move applies to all board except:
* Guybrush
* Nipperkin board version 1
Add callbacks for variants to override fpmcu shtudown gpio table and
fpmcu disable gpio table.
BUG=b:202992077
TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure fingerprint
still works.
Change-Id: I4501554da0fab0cb35684735e7d1da6f20e255eb
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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GSC_SOC_INT_L gpio is used by Google Security Chip (GSC) to interrupt
SoC when the SoC is in S0 state. Hence use GPIO_85 which is in S0 domain
and save the GPIO_3 in S5 domain for other use-cases. This move applies
to all board except:
* Guybrush
* Nipperkin board version 1
Update the GPIO configuration, device tree configuration accordingly.
BUG=b:202992077
TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure that the SoC
<-> TPM communication is working fine.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I019f10f2f457ab81bcff77ce8ca609b2b40cb2ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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GPIO overrides are defined for verstage. But the overrides are neither
enabled nor applied during verstage. Enable the overrides and apply them
during verstage.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform suspend/stress, warm and
cold reboot cycling for 10 iterations each. Ensure that all the PCIe
devices are enumerated fine.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I510313bf860d8d55ec3b04a9cfdfa942373163f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M
BUG=b:200918380
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I83cc1a5d80bf23d052e83c9791ef866966a3d9b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58626
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Hynix H54G46CYRBX267
Samsung K4U6E3S4AB-MGCL
BUG=b:204015941
TEST=run part_id_gen to generate SPD id
Change-Id: I78ec575d354a5ae7c014a6050364d0a5214e4e92
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
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Add new memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. K4U6E3S4AB-MGCL
2. H54G46CYRBX267
BUG=b:204023388
BRANCH=firmware-keeby-14119.B
TEST=FW_NAME=driblee emerge-keeby coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I1b40e24faf8d85f32839a3d44fd936ca7ee7e09f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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In-band controls work to enable/disable the WWAN module. Hence
WWAN_DISABLE_GPIO is not critical and can be marked as not connected.
BUG=b:188415287
TEST=Build and boot to OS in Guybrush. Ensure that the WWAN module is
enumerated on boot and reboot.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7fefba3de9c749971911b21ed4712e950cef5a6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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On all upcoming variants and board versions of existing variants,
SD_AUX_RESET_L signal moves from GPIO_69 to GPIO_5. This means all
boards except:
* All board versions of Guybrush
* Nipperkin Board Version 1.
Also in Nipperkin, LCD_PRIVACY_PCH signal moves from GPIO_5 to GPIO_18.
Configure the gpios accordingly in baseboard, guybrush and nipperkin
variants accordingly. Also update the DXIO port descriptor for SD PCIe
engine with the corresponding AUX reset GPIO.
BUG=b:202992077
TEST=Build and boot to OS in Guybrush & Nipperkin. Ensure that the SD
Controller and SD Card are enumerated fine. Ensure that the enumeration
is successful after a suspend/resume cycle.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: If28810747e6b4eaae2a693a98e1adc830f80bcf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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The baseboard enables PCIe RPs 6, 8 and 9, but kano doesn't use
these. Having them enabled will occasionally cause suspend
attempts to fail, therefore disable them in the overridetree.
BUG=b:203389490 b:192370253
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie2b82cff6d910c961eeb56704dcbae2bdc2a8c53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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On Guybrush, pen is stuffed and GPIO_5 is used to enable Pen power. On
Nipperkin board version 1, pen is not stuffed and instead the GPIO is
used to control LCD Privacy settings. On upcoming Nipperkin board
versions and other variants, GPIO_5 is not used. Configure GPIO_5
accordingly.
BUG=b:202992077
TEST=Build and boot to OS in Guybrush. Ensure that the configuration is
retained on existing boards.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2aa2f16282b91f157701212ee27ddd2e89918767
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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The `SMBIOS_PROVIDED_BY_MOBO` Kconfig option is already selected through
the `SECUNET_DMI` option. So, there's no need to select both of them.
Change-Id: I784df87893043a011906af8808aff27d636c7626
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58625
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Hynix H54G46CYRBX267
Samsung K4U6E3S4AB-MGCL
BUG=b:204014463
TEST=run part_id_gen to generate SPD id
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I43df98d84c6a274d6f96c8818ce6acff9337d8d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Micron MT53E512M32D1NP-046 WT:B
Hynix H54G46CYRBX267
Samsung K4U6E3S4AB-MGCL
BUG=b:204015944
TEST=run part_id_gen to generate SPD id
Change-Id: Icf2f7352a4bd6a58e3e7abdcaac823b863984732
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1).
BUG=b:197385770
TEST=emerge-brask coreboot and verify it builds without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia3813306f8c7b69fe5cf0e188c55256b68d329ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch set disables the external voltage rails since kano
board doesn't have V1p05 and Vnn bypass rails implemented.
BUG=b:192370253
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia1f3f4b2ada0154c716aedd521d4151124411ba3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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To prevent unexpected alert from eSPI to SOC, configure this alert pin
to in-band.
BUG=b:199458949,b:203446084
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I18d38fe504bd9f2069b9977d5a35729691f672d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Follow up the G2 spec: G7500_Datasheet_Ver.1.2
BUG=b:203607764,b:202090378
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
TS is functional
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I98dd3095043ab537d91e81b84944779240b203ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change adds sub-regions to SI_ME in chromeos.fmd. These are
required to support stitching of CSE components.
BUG=b:189177538
Change-Id: Ife48aafcec43555175aad44f8b6307beeaea9184
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58592
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS"
BUG=b:197694580
BRANCH=dedede
TEST=ALC5682I-VD or VS audio codec can work normally
Signed-off-by: Yongkun Yu <yuyongkun@huaqin.corp-partner.google.com>
Change-Id: I422f206b8f1f3705a65808041f1a1544c461b431
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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There's no need to have an overridetree with a single board variant.
TEST=Compare static.c and observe only device order has changed.
Change-Id: I2097e247c27d5d0c5479cb533b477cd490a4c827
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Move per-port PCIe settings inside the corresponding PCIe root port
device. Also, remove several unnecessary and/or redundant comments.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I3f64d56b3b2c592194b18ae7b7c63ef41a1e060f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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turn off WLAN ASPM L1.1/L1.2 as a short-term w/a for WLAN AP probe failure.
BUG=b:198258604
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
AP is able to be probed by wlan module
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ic7be523626b0ff6e4b1c66ba6af13b15061ef4cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Enable CnviBtAudioOffload UPD
BUG=b:199180746
TEST=emerge-byra coreboot
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Change-Id: Ic507b1d0f7c2f38de8d24247cd677b897a7463f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I01ee0ba99eca6ad4c01848ab133166f8c922684d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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For coreboot proper, I/O APIC programming is not really required,
except for the APIC ID field. We generally do not guard the related
set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC).
In practice it's something one cannot leave unselected, but maintain
the Kconfig for the time being.
Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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For SMP operation IOAPIC needs to be configured.
For a build with MAX_CPUS=1 emulation might still decode
the IOAPIC MMIO window, it does not really matter to have
it always reserved.
Change-Id: Ia340fc418cd9ceda56a2a10972e130d9f289c589
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Each CPU/SoC checks the return value of the mp_init_with_smm and prints
the same error message if it wasn't successful, so move this check and
printk to mp_init_with_smm. For this the original mp_init_with_smm
function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm
function is created which then calls do_mp_init_with_smm, prints the
error if it didn't return CB_SUCCESS and passes the return value of
do_mp_init_with_smm to its caller.
Since no CPU/SoC code handles a mp_init_with_smm failure apart from
printing a message, also add a comment at the mp_init_with_smm call
sites that the code might want to handle a failure.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Using cb_err as return type clarifies the meaning of the different
return values. This patch also adds the types.h include that provides
the definition of the cb_err enum and checks the return value of
mp_init_with_smm against the enum values instead of either checking if
it's non-zero or less than zero to handle the error case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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