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2016-01-17google/lars: Enable 20K PU on LPC_LAD 0-3david
At S0, S0ix and S3 LPC LAD signals are floated at 400~500mV. BRANCH=none BUG=chrome-os-partner:48331 TEST=Build and boot on lars Change-Id: I5582007e5caaf444740fa71c9761c27614aafee2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b855fd5834056a3f7d4aef91d634066006990a38 Original-Change-Id: I3a54f9f83f055e433cc1fea38169437ee7f9188f Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317071 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12965 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17google/lars: Remove/Disable Wake on landavid
Remove the WakeConfigWolEnableOverride to disable WOL override configuration in the General PM Configuration B (GEN_PMCON_B) register BRANCH=none BUG=none TEST=Build and boot on lars Change-Id: I48d3b706517b6ea6bda44800f61bb11da64503fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eab69f2d725df739e5e0e5901a581ad58732cdf9 Original-Change-Id: I42c5a87150638171526ee67f194c1cd9d155203b Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/317080 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12962 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16google/lars: add nhlt supportSubrata Banik
Provide an option for including the NHLT blobs within the lars mainboard directory while also adding the ACPI NHLT table generation that the current hardware supports. BUG=chrome-os-partner:44481 BRANCH=None TEST=Built and booted lars board. Audio worked with MAXIM audio card. Change-Id: I1b7836c685ebbe1498f3dbaa2eb64d5e0d4faabb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 401f1a7b23dca19712517ed1588e1390769d1271 Original-Change-Id: I6a937872a9e10d2c5ea15d5952d23e98416df092 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316092 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12961 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16mainboard: Drop abuild.disabled files for Skylake boardsStefan Reinauer
Make sure the latest & greatest Intel targets actually build in our build system. intel/sklrvp is still failing for reasons unrelated to the rest of the skylake boards. Leaving that disabled for now. Change-Id: Ie784628a57257cea30e5e47074648198b884f6db Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12857 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2016-01-16intel/kunimitsu: remove/disable Wake on lanRizwan Qureshi
remove the WakeConfigWolEnableOverride to disable WOL override configuration in the General PM Configuration B (GEN_PMCON_B) register BRANCH=none BUG=none TEST=Build and booted in kunimitsu Change-Id: Ia523e7956c06c9f4a60e0a2296f771cc3c70bc25 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 12a07eebfb8fa4ee8013fbbb12283a0b429cacfd Original-Change-Id: I2be6c5b0114e4c7d8a7b9ceb59ee32f28f61769f Original-Reviewed-on: https://chromium-review.googlesource.com/316717 Original-Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12958 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16google/lars: Add new configuration parametersdavid
Follow kunimitsu setting of https://chromium-review.googlesource.com/#/c/313309/ BRANCH=none BUG=none TEST=Build and boot on lars. Change-Id: I77a4454b3702dc58dc70a7b981b25a656e97f534 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c390322b4c770a0206549257dd34d1ef1242cc3 Original-Change-Id: I612e799433a396a6cce5742adb6de72a305b5df1 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316270 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12954 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16google/lars: Disable SD 3.0 Controller [D30:F6]Subrata Banik
LARs design don't have SD Connector over native SD Controller. BUG=chrome-os-partner:48190 BRANCH=None TEST=Build & boot LARs. Use "lspci" doesn't list 0x1E:06 device in list. CQ-DEPEND=CL:315420 Change-Id: Idff7243a6aaf4b8d5f49e4bf215a77131f716485 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca769138b97b404598c4a6bfa6c2ff5c1c3ec896 Original-Change-Id: I71416ac89a8c91ab272d6737d1b46c8045567e17 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315423 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12947 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16intel/kunimitsu: Add VrConfig UPD parametersRizwan Qureshi
Cofigure VR settings for kunimitsu BRANCH=none BUG=chrome-os-partner:45387 TEST=Build and booted in kunimitsu CQ-DEPEND=CL:311317 Change-Id: Ib2afe7694d2a807cea1befa73349bd21a3e7d909 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c3548d7cb3a00826377e819f20d07167b4eb2c65 Original-Change-Id: I6b80f509bc0ab6f65f26eec0651a3b44fb38fbf9 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313068 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12945 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/kunimitsu: Add new configuration parametersRizwan Qureshi
Add new configuration parameters eg. #SLP_S3 assert width BRANCH=none BUG=chrome-os-partner:44075 TEST=Build and booted on kunimitsu, verified that CB is doing the Lockdowns which were previously done by FSP. CQ-DEPEND=CL:310869 Change-Id: I782df49bbf73c121b191f0661907173c4fd29b64 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de0742869b1b148597d3714a3bc29a0dc08642aa Original-Change-Id: I2b4041cdc22a29e79d2ff7f2cc49f51f80da5567 Original-Reviewed-on: https://chromium-review.googlesource.com/313309 Original-Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12942 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/kunimitsu: Enable 20K PU on LPC_LAD 0-3pchandri
At S0, S0ix and S3 LPC LAD signals are are floated at 400~500mV. BRANCH=chrome-os-partner:48331 BUG=None TEST=Build and Boot kunimitsu Change-Id: I2e2654ac89f8e0c8d6ab1af31d0bd5a0d4c43db8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6f4b902e220dcde73df56970208c45fe3148b70e Original-Change-Id: I597d4816d09d0cfd9b0ec183a9273551aed8688a Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316529 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-on: https://review.coreboot.org/12957 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/lars: Set DPTF critical temperature to 99Cdavid
DPTF may power off the system when it starts if the CPU temp is >90C. Since TJmax is 100C set the critical threshold to just below that value. BRANCH=none BUG=none TEST=Build and boot on lars. Change-Id: I3abf946ae09c3c691480e468d0c1d74730dc6c06 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7c2230009edb840e88a20c2d8a87f942c09b6bf3 Original-Change-Id: Iee1a3596dbbe934f68637f012c02c078c3751eeb Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316102 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12955 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/lars: Disable kepler devicedavid
Disable kepler device, it is removed and was not used on proto anyway. BUG=none BRANCH=none TEST=build and boot on lars proto Change-Id: I137b82b8dca23f5b40adcc6a056e77a4ff54d4d5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 44d63453a9b31331d13d05f8f86d4218af0f0aa1 Original-Change-Id: Ib0892bf93b1d0cda1c0143d2b16cd58aeda83131 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315950 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12950 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/lars: Add support for MAX98357A audio amplifierSubrata Banik
Adding support for Maxim 98357A audio amplifier. Removed SSM4567 support from LARs. BUG=chrome-os-partner:44481 BRANCH=None TEST=Build & boot on LARs. Verify audio playback works using MAXIM amplifiers. Change-Id: I2cd8b20e936319b434017b6dd73d4739684d21d3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 76cbc20826c884194a144f6b6bc644900e5d475d Original-Change-Id: I1156096b6aa367c0b8d8e3952d92f0eb5cf2820f Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/314543 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12960 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/kunimitsu: Correct the output for crossystem wpsw_bootArindam Roy
The write protect GPIO is not being configured early enough. This is leading to coreboot reading incorrect value, and writing the incorrect value in vboot shared file. This is leading to "crossystem wpsw_boot" always returning 0 even with the write protect screw in place during boot. BUG=chrome-os-partner:48292 BRANCH=None TEST=Boot with the write protect screw in place. Issue crossystem wpsw_boot. It should show 1. Change-Id: I3a333a4dcce31be9afe28cf11b127090cc7b9421 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 462dd0229c2d3b81cd34bdd2e36bea844f58586c Original-Change-Id: Ib7e0539845575b32322e243e89b81ffee077eb81 Original-Signed-off-by: Arindam Roy <arindam.roy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316009 Original-Commit-Ready: Arindam Roy <rarindam@gmail.com> Original-Tested-by: Arindam Roy <rarindam@gmail.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12952 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/lars: Update the PL1 value as TDPdavid
Currently, the Power Limit 1 (PL1) value is 6W which is low for high performance KPIs. This patch updates PL1 value as TDP. SKL-U has 15W TDP. BRANCH=none BUG=none TEST=Build and booted on lars. Change-Id: Ic1313385e0aa1760b473a34c853a95c76257eecf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a47faee53e08da81602b485937621fd49eb2ddbf Original-Change-Id: I7c91dcdc82525a6d2b706f8f504ba48601097ef7 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316370 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12953 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/chell: Fix the P/N number for samsung K4E6E304EE-EGCFWisley
modify the P/N in samsung K4E6E304EE-EGCF SPD from K4E6E304ED-EGCE to K4E6E304EE-EGCF BRANCH=none BUG=chrome-os-partner:48299 TEST=build chell and use gooftool to probe and P/N match Change-Id: Ie560e5c0d4b9a3cfb34c3856911930fb8159764e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dabe5eaa8abf54f4e4a5492062adca6ef9b4634d Original-Change-Id: Ie8d44ac6032e5213928bfae2a2ac5877d4193d62 Original-Signed-off-by: Wisley <wisley.chen@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316100 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12951 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/kunimitsu: Add support for MAX98357A audio amplifierRohit Ainapure
Adding support for Maxim 98357A audio amplifier. BUG=chrome-os-partner:44481 BRANCH=None TEST=Build & boot on Skylake kunimitsu Fab4 with MAXIM codec. Verify audio playback works using MAXIM. Change-Id: I4f020ccae540b02d5d533704a52cebb7805715fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c0a81300e02e917500fa3c0241c95dd795abaf04 Original-Change-Id: I8875c9a55f09b1ec353203cfcb2186dc5fd66542 Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309894 Original-Tested-by: Rohit M Ainapure <rohit.m.ainapure@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12949 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/chell: add nhlt supportAaron Durbin
Provide an option for including the NHLT blobs within the glados mainboard directory while also adding the ACPI NHLT table generation that the current hardware supports. BUG=chrome-os-partner:44481 BRANCH=None TEST=Built and booted. Headphones, speakers, and mic on camera emits and creates sound albeit not the greatest. Change-Id: Iaf910041453695b7125b254ca5d71e8ccbd0b02f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ea77d326ba1c33b100c34066ed361a55dfa14ce3 Original-Change-Id: I5d93c3a7fa4cf68ba91f1398b4bd04504a28fef2 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/315520 Original-Tested-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12948 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/glados: add nhlt supportAaron Durbin
Provide an option for including the NHLT blobs within the glados mainboard directory while also adding the ACPI NHLT table generation that the current hardware supports. BUG=chrome-os-partner:44481 BRANCH=None TEST=Built and booted. Headphones, speakers, and mic on camera emits and creates sound albeit not the greatest. Change-Id: I6e36c0a99a73cdcb2bf6ccfbfc886a594f989a39 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5b0383a93f054011dd7c18519ece4e6f1944366d Original-Change-Id: I6f8bd15c72fa89756382af99bddb6cb6abe89905 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313794 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12939 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/kunimitsu: Update the PL1 value as TDPSumeet Pawnikar
Currently, the Power Limit 1 (PL1) value is 6W which is low for high performance KPIs. This patch updates PL1 value as TDP. SKL-U has 15W TDP. BRANCH=None BUG=None TEST=Built and boot on kunimitsu. Check for the PL1 value over sysfs interface "/sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw". Load the system with Aquarium 1000 Fish, average FPS should be meeting target 60 with this change. Change-Id: I8e083192e8018edc2cf8b88530df1e05ede10bde Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: eb9aa00a4271875b5471c33883aa7da022f1cb0e Original-Change-Id: I0c61fe1a9f76a9cf9a306240fb66d4c081d2bb5e Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/314416 Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/12934 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15google/lars: Disable eMMC HS400 capabilitydavid
BUG=chrome-os-partner:48017 BRANCH=none TEST=Verify eMMC is working fine. Change-Id: If02d969029a9eb8d05148ee958fd34225c8a88fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dca385c2bbf11c9eb79fd0761b2b335f8fdff491 Original-Change-Id: I371036426f17530409b46af285b18f4522739ee7 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313912 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12618 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14mb/lenovo/x200: Add panel power sequence valuesNico Huber
Values are taken from the vendor BIOS of my X200s. Notable effect: Stops display from flashing during native graphics init / Linux mode setting. Change-Id: Ie5d9efc010a78dd46317b6bbdb7bfacc2c9d2cbf Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-14mainboard/lenovo: reserve century byteAlexander Couzens
The century byte is used by most RTC (default 0x32@nvram). Even the century byte can disabled via ACPI it's more safe to reserve it's space. Because some RTC will act with that byte anyhow. Some OS overwrite it when syncronize the RTC. Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/11853 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
This continues what was done in commit a73b93157f2 (tree: drop last paragraph of GPL copyright header) Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13intel/skylake platforms: Add MAINBOARD_HAS_LPC_TPM in KconfigMartin Roth
Because these platforms haven't been getting build testing, they've missed out on some of the improvements that the other platforms have gotten. Enable MAINBOARD_HAS_LPC_TPM so that they will build. Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12865 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-13[WIP] mb/roda/rk9: Enable CONFIG_HAVE_ACPI_RESUMENico Huber
Change-Id: Ifa7dd593f70921a99d937104960e26100de28089 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/12421 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-12google/guado: initial upstream migrationMatt DeVillier
Migrate google/guado (Asus Chromebox CN62) from Chromium tree to upstream, using google/auron and google/panther as refs. TEST=built and booted guado with full functionality Change-Id: If7a500fb408197a61c9619b9d5ea1458d1f4d702 Tested-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12800 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-10lenovo/x220: Enable USB 3 controllerMarian Tietz
Since only X220 with i7 have the USB3 controller this was probably overlooked. Before this patch lspci on Linux would not show the NEC USB 3 controller as well as the PCI bridge it is behind. After, both the bridge and the NEC controller can be found in the output: 05:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller (rev 04) Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331 Signed-off-by: Marian Tietz <mtcoreboot@gmail.com> Reviewed-on: https://review.coreboot.org/12882 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-01-07mainboard: Drop abuild.disabled files for Braswell boardsStefan Reinauer
Make sure the latest & greatest Intel targets actually build in our build system. Change-Id: I479ad473c260fc914d224cb58f4be1837aff2502 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12463 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07Correct some common spelling mistakesMartin Roth
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07google/cyan, intel/strago Kconfig: Only ask to display SPD onceMartin Roth
Change-Id: Ic3df9bf7d7f3c4c39789f3f496bcb7fc2ee50931 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12827 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07mainboard/asus/kgpe-d16: Enable romstage microcode spinlocksTimothy Pearson
Change-Id: I93687efc5405359286d3197f0e59ec3b118c5100 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12809 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-06intel/braswell: Build in both C0 and 'other' vbiosMartin Roth
The Braswell CPU seems to have two different Video BIOS roms, one for the C0 revision, and one for other revisions. Build them both into the coreboot image, and let coreboot sort out which one should be used at runtime. This should allow one rom to be used for all revisions. The initial reason for this patch was that the Kconfig symbol C0_DISP_SUPPORT didn't exist, and was causing issues. This seems like the best way to eliminate the need for that symbol. Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12826 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-31lenovo/x200: Revise onboard IRQ routingNico Huber
All southbridge interrupt pin and routing registers (D*IP and D*IR) are left at their default values (see ICH9 datasheet) and this file just has to reflect them. Change-Id: I687262556d918311757fda9afda9ebfdd7edf947 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/12813 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-31imgtec/pistachio: disable default RPU gate register valuesIonela Voinescu
The RPU Clock register defaults to on for all clocks. This is modified to OFF, and the MIPS clock control modified to ON, by default. This is because the linux kernel will manage the clocks at all times, but the RPU can only disable clocks if the WIFI module has been loaded. Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-30gigabyte/ga-g41m-es2l: Add mainboardDamien Zammit
Board uses x4x native raminit Board boots into Debian 8 with full graphics IRQ9: nobody cared, gets disabled (PIC needs IRQ settings?) VGA: - VGA native init works in grub with analog connector - Fails to boot with both channels of ram populated Change-Id: I7417813456817529b8cbaace45cefe47467d0a82 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/11306 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-27mainboard/google/urara: change SYS PLL to 700MHzIonela Voinescu
This requires changes the interface that sets up the system PLL to support a given reference devider value and given feedback value. Also, this requires a change in the dividers used for UART, USB, I2C setup. Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12765 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-26IT8772F: Clean up it8772f includes and add a LED APIdavid
- Remove it8772f c includes - Add a new LED API, it8772f_gpio_led - Stumpy: using it8772f_gpio_led BUG=chrome-os-partner:28232 BRANCH=Guado TEST=emerge-guado coreboot chromeos-bootimage Change-Id: I08de52515d3c1e7e85d1761c09a0cebffda7dda3 Signed-off-by: David Wu <David_Wu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/241813 Tested-by: David Wu <david_wu@quantatw.com> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: David Wu <david_wu@quantatw.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12797 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-18mainboard/asus/kgpe-d16: Enable CBFS spinlocksTimothy Pearson
Change-Id: I8f6226d3e74ac5c7f29f708128a7502ced1287bf Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12062 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-18siemens/mc_tcu3: Set GPIO_S0_SC[75] to outputWerner Zeh
The usage of the pin has changed and therefore this pin needs to be set up as output and drive low initially. Change-Id: Ie3eb9cc703f7f73d59fad52ea9e514997d84606a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/12754 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-17google/veyron: Add commercial board names in Kconfig.nameDenis 'GNUtoo' Carikli
The correspondence between engineering code names and commercial names can be found on chromium.org website at: https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices This it to make the names more relevant: towiki (in util/board_status/to-wiki/towiki.sh) will pick such names, which end up in the supported board list at: http://www.coreboot.org/Supported_Motherboards Change-Id: I2d705672d7202964fea3f62a5bd61a231d3f14c0 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/12652 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-12-17google/veyron: Indicate which boards are laptops.Denis 'GNUtoo' Carikli
This is to make towiki pick that information, to make these boards end up in the laptop list at: http://www.coreboot.org/Supported_Motherboards Change-Id: Ibf8bf4bf6566080a34687e36675d4c4c8b89f334 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/12716 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-16intel/fsp_baytrail: rename include folder baytrail to include/socBen Gardner
This is to match the layout of the non-fsp baytrail to make comparisons easier and possibly remove duplicate files. Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12686 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-16southbridge/amd/sb600: Update HPET base address with #defineMartin Roth
The SB600 code had the base address of the HPET hardcoded throughout. It looks like the plan was to have it be updated in ACPI if needed, but this wasn't ever implemented. The variable names being used to do this update were the same, causing an IASL warning. Because of this, the operation to update the HPET address actually did nothing. This was fine, because it didn't actually need to be updated. - Replace all that code with a #define. - Add and update some comments in the same area. Fixes IASL warning: dsdt.aml 1505: Store(HPBA, HPBA) Warning 3023 - ^ Duplicate value in list (Source is the same as Target) Change-Id: I9ba5fe226a4a464e0045ce7d3406898760df5e5a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12705 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-12-15x86 acpi: remove ALIGN_CURRENT macroAaron Durbin
The ALIGN_CURRENT macro relied on a local variable name as well as being defined in numerous compilation units. Replace those instances with an acpi_align_current() inline function. Change-Id: Iab453f2eda1addefad8a1c37d265f917bd803202 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12707 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-15mainboard/asus/kgpe-d16: Enable romstage spinlocksTimothy Pearson
Change-Id: Iac1adbeacdcded7faff2443b78a491cbb8a90fe8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-15google/oak: Move CHROMEOS specific Kconfig objects under CHROMEOSMartin Roth
The symbols CHROMEOS_VBNV_EC, EC_SOFTWARE_SYNC, and VIRTUAL_DEV_SWITCH should only be selected if CHROMEOS is selected. Change-Id: I07ef631d63be53cf99a6bf61d0e91b88728dbba3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12659 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10emulation/qemu-arm7: Fix Kconfig symbols for stage compilersMartin Roth
These had typos ARM_STAGE_ARM7 instead of ARCH_STAGE_ARM7 Change-Id: Iffe8fecb3e52a50ff02b774478a10c353093688b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12660 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10ACPI: Fix IASL Warning about unused method for _S3 checkMartin Roth
According to the ACPI Spec for CondRefOf, the result argument is optional. In all of these locations, it was getting set but not used, creating a warning in new versions of IASL. Since it's an optional argument, just remove it. dsdt.aml 640: If (CondRefOf (\_S3, Local0)) Warning 3144 - Method Local is set but never used ^ (Local0) Change-Id: I758d198c33e585a6a4ad2c1c70f2370a01af5138 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12693 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10ACPI: Work around IASL warning reading/writing same registerMartin Roth
The newer versions of IASL are unhappy when an operator has the same object as both source and destination. The warning can be completely disabled with a command line argument, but in general, I'd really rather not just disable warnings. The bits in this register are write 1 to clear, so reading and writing the same register is what we want to do. Instead, store it in a temporary register then write it in a second operation. Fixes warning: dsdt.aml 1396: Store(PWST, PWST) Warning 3023 - ^ Duplicate value in list (Source is the same as Target) Change-Id: I52d73d4431db237be83016d67cd397f31b53d9c6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10ACPI: Fix IASL Warning about unused method for _OSI checkMartin Roth
According to the ACPI Spec for CondRefOf, the result argument is optional. In all of these locations, it was getting set but not used, creating a warning in new versions of IASL. Since it's an optional argument, just remove it. dsdt.aml 22: if(CondRefOf(\_OSI,Local1)) Warning 3144 - ^ Method Local is set but never used (Local1) Change-Id: I07f49ac5a3708838d1c4a7216dfb11acc415c881 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10cbfs/vboot: remove firmware component supportAaron Durbin
The Chrome OS verified boot path supported multiple CBFS instances in the boot media as well as stand-alone assets sitting in each vboot RW slot. Remove the support for the stand-alone assets and always use CBFS accesses as the way to retrieve data. This is implemented by adding a cbfs_locator object which is queried for locating the current CBFS. Additionally, it is also signalled prior to when a program is about to be loaded by coreboot for the subsequent stage/payload. This provides the same opportunity as previous for vboot to hook in and perform its logic. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. CQ-DEPEND=CL:307121,CL:31691,CL:31690 Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12689 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-09mohonpeak/Kconfig: Fix whitespace issuesMartin Roth
Auto-indent did me wrong, and I didn't notice it. Change-Id: I5a736cf53a3bdbe57b28b2d6a55befd341d8dfd8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12655 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-09google/oak: define flash sizePatrick Georgi
We never defined the flash size for this board, so the (too small) default was used. Instead, adopt the size given in depthcharge's fmap description. Change-Id: I63782922ee05a9595d6c0de56750460ebb67aec6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12674 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-12-08intel/strago: Remove CONFIG_ from CONFIG_GOP_SUPPORT inside KconfigMartin Roth
The CONFIG_ is only used for Kconfig symbols outside of Kconfig. If used inside Kconfig, you'd end up with CONFIG_CONFIG_GOP_SUPPORT when it was used in the C code. Change-Id: I572323ef08fdd937d33ded1c27a418b3ad856147 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12664 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08lenovo/t500: Add clone of Lenovo T400Francis Rowe
The existing code for the Lenovo T400 works without changes on the Lenovo T500. Same HDA verbs are provided by Lenovo BIOS on both laptops. Change-Id: I300408a8a0ed00476aee6061925befc2822fb505 Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: https://review.coreboot.org/10545 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-08intel/littleplains: Update with recent changes to mohonpeakMartin Roth
- Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE. - Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset. - Remove fixed microcode location. Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12635 Tested-by: build bot (Jenkins) Reviewed-by: David Guckian <david.guckian@intel.com>
2015-12-07mainboard/asus/kgpe-d16: Use I/O PCI access in bootblockTimothy Pearson
The existing code incorrectly used standard PCI access calls in the bootblock. Use the I/O PCI access calls as the normal PCI access mechanisms have not yet been set up. Also ensure the recovery jumper GPIO has been set to input mode before reading it. Change-Id: Id626d01526427004b2404e4d9b44d7c987d172d1 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12651 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-12-06pcengines/apu1: Supply _HID object for ACPI GPIO devicesMartin Roth
The _HID was present for the top level BTNS and LEDS Devices, but was missing in the individual devices. The alternative would be to supply the GPIO being used as an _ADR object, but since it looks like the driver already has another method of handling that, it isn't required. Fixes these IASL warnings: dsdt.aml 1522: Device (BTN1) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 1567: Device (LED1) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 1576: Device (LED2) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 1587: Device (LED3) Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) Change-Id: I67c48084a6ee2a104ffff2b5a986d24a51ee49e1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12582 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06intel/fsp_rangeley: change non-existent config options to #definesMartin Roth
Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO were never added to the coreboot codebase when the Rangeley code was brought in from Sage. These symbols disabled ACPI code that was unused because it caused dmesg warnings due to conflicts with drivers trying to claim the same addresses as the ACPI code. Because it could be used on some other platforms, it was left in instead of being completely removed. - Change the Kconfig symbol names to simple #defines in the mainboard code. - Add the #defines along with comments to the reference platform. - Hook everything together in dsdt.asl - Update new mainboard littleplains the same way. Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12552 Reviewed-by: David Guckian <david.guckian@intel.com> Tested-by: build bot (Jenkins)
2015-12-06hp/pavilion_m6_1035dx: Fix IASL warning - Missing _HID objectMartin Roth
- Add System board _HID object. - Remove Kconfig default disabling IASL warnings as errors Fixes warning: dsdt.aml 64: Device (MB) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) Change-Id: I4fa6ab2a6744d58ded8b0feb361e002d90e11474 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12532 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06Rangeley: Change A, A, A, A INT routing to A, A, A, BMartin Roth
Devices that have their interrupt routing set to A, A, A, A don't get any interrupt values assigned because that series evaluates to 0. The code that sets the interrupt values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused interrupt lines from A to any other value, it assigns the values correctly. This issue did not affect ACPI interrupt routing. This is just a workaround, and the root issue still needs to be fixed. Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12630 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06fsp_baytrail: Change A, A, A, A IRQ routing to A, A, A, BMartin Roth
Devices that have their interrupt routing set to A, A, A, A don't get any interrupt values assigned because that series evaluates to 0. The code that sets the interrupt values checks to make sure a value is set by verifying that it's not 0. On Bay Trail, these are all single-function graphics devices, so by changing one of the unused interrupt lines from A to any other value, it assigns the values correctly. This issue did not affect ACPI interrupt routing. This is just a workaround, and the root issue still needs to be fixed. Change-Id: I78866e3e0079435037e457a4fb04979254b56ee2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12629 Tested-by: build bot (Jenkins) Reviewed-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06intel/eagleheights: Fix IASL warningsMartin Roth
The eagleheights platform had 3 warnings: The SIO device needs an _ADR object to specify the address in addition to the operating region. Not all the paths through the _OSC method returned a value. According to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized GUID. dsdt.aml 341: Device(SIO) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 140: Method (_OSC, 4) Warning 3115 - ^ Not all control paths return a value (_OSC) dsdt.aml 140: Method (_OSC, 4) Warning 3107 - ^ Reserved method must return a value (Buffer required for _OSC) - Remove Kconfig default disabling IASL warnings as errors. Change-Id: Iab52f19b96468e142b06430d99ba1d9f367d126e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12522 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04google/oak: Add timestamps in romstageYidi Lin
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: Idf74265c9c1ab3a1a74fd18dfd289fccad25177e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 569c433886b19cd08d168e995bf34156c2ba6963 Original-Change-Id: I07fda6a0719d49e2c07249276ae2cc0b57fdfeda Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12610 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04mediatek/mt8173: Add mt6391 PMIC driverhenryc.chen
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I2b9e1fc16183a29ba308313d347f2f0e948e96a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ee56cab3b5c04838af80690c21d3aa160d71501a Original-Change-Id: I2eaa0a406c29b7c9012e3c9860967fc3f27a48a5 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292669 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12608 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04esd/atom15: import esd atom15 boardMichael Tasche
This patch adds esd atom15 board with Intel Atom E3815 SoC. Change-Id: I430a40ad8ab3316d34ec5567329370f69db3f15e Signed-off-by: Michael Tasche <michael.tasche@esd.eu> Reviewed-on: https://review.coreboot.org/12632 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04intel/minnowmax: Fix IRQ connection for legacy uart at 0x3f8Michael Tasche
The E38xx legacy uart fires IRQ4, not IRQ3. PCI based IRQ A is switched from IRQ4 to IRQ3, to get a working IRQ for the legacy uart. Change-Id: Ibc8e824c92bf1b9a92594ddc5d8a06726c9f1744 Signed-off-by: Michael Tasche <michael.tasche@esd.eu> Reviewed-on: https://review.coreboot.org/12622 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-12-04mainboard/biostar/am1ml: Force basic SPI read modeSergej Ivanov
This patch force AGESA to use basic SPI read mode. Without it board hangs during spi configure if W25Q32 chip is used. Change-Id: I3e17cd21702626be5061d2fc14adc0c22f167efb Signed-off-by: Sergej Ivanov <getinaks@gmail.com> Reviewed-on: https://review.coreboot.org/12580 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-03intel/mohonpeak: Change SEABIOS_MALLOC_UPPERMEMORY to config_seabiosMartin Roth
Instead of the SEABIOS_MALLOC_UPPERMEMORY option, use a saved SeaBIOS .config file to do the same thing. Change-Id: I29110a382b7770329ef938876426e571fbbbb339 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12569 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-03google/oak: Add board_id() and ram_code() implementationCC Ma
BRANCH=none BUG=none TEST=Oak build pass Change-Id: Ic2fd9b2ec0592d1f7195d72c60dab15961de0a9e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d0b00a779b87b0b625cc2bccd8f7470b79e6410 Original-Change-Id: Id9f17d64e9e30946817b86ec8cdfe67ea3dbc798 Original-Signed-off-by: CC Ma <cc.ma@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292675 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Implement the code which reads GPIOs for ChromeOS.Yidi Lin
BUG=none BRANCH=none TEST=emerge-oak corebootk Change-Id: Ic1a0d640cac7fd98acd06d619736303fa449c0a1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce465e8cbdf6465c072e476a91a400d78c959218 Original-Change-Id: Iade51db02f45264fdffe387e0563b60e637c0710 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292674 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12606 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/oak: Initialize the necessary pinsBiao Huang
BRANCH=none BUG=none TEST=verified on Oak rev2 & rev3 Change-Id: I35776f5bdf54243236afba860ae8e9117a160cde Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b46bd9a079107ab78964f7e39582b3b5c863b559 Original-Change-Id: I6696972d07adbf3da5967f09c1638bb977c10207 Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292673 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12605 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/chell: update dptf TSR1 & TSR2 critial pointsWisley
update dptf TSR1 & TSR2 critial points from 70 to 75 TSR1 & TSR2 are reach 68 degree that is close to 70 degree afer SVPT test, change the point will avoid to trigger critial in our factory run in test BRANCH=none BUG=none TEST=build and boot chell DUT Change-Id: Ie5b8b24d82e929a7bd254967b70b61fda2c8bd0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf29fee19edf425010cc76af95b7a8e73a3d82bb Original-Change-Id: Idb9dd77432cfd246c1c612e52c6f945352e265ca Original-Signed-off-by: Wisley Chen <Wisley.Chen@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313967 Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Chen Wisley <wisley.chen@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Chen Wisley <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/12604 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/kunimitsu: Coreboot GPIO changes for FAB 4.Saurabh Satija
This patch adds GPIO mappings for PCH_BUZZER, AUDIO_DB_ID, AUDIO_IRQ and BOOT_BEEP. BUG=chrome-os-partner:47513 BRANCH=none TEST=Built for kunimitsu but not verified on Fab 4. Change-Id: I0172df3aa2a5c4bfc24422aa0bfb7e5f677d37c9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ba66bef6d402a1040f0f13bc828de400bc6371b7 Original-Change-Id: I1f2ed8fc283883a523a77e07de14ed90057b719b Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311806 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/12600 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/glados: Disable kepler deviceDuncan Laurie
Disable the kepler device to save power and enable S0ix testing. It has been disabled in the ME image and was not working anyway.. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: I6640c7a09d418ba4b4de6f16138c124436dd8758 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6490769a32539cb6ef429717f021519c152a4a54 Original-Change-Id: If6e384dd2218c6a110747a489329a59fa6433c02 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313827 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12599 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-12-03google/chell: Update mainboard for EVTDuncan Laurie
- Disable kepler device, it is removed and was not used on proto anyway. - Enable GPP_D22 as GPO to control I2S2 buffer for bit-bang PDM. - Disable HS400, this is breaking some devices on proto boards and is being disabled to reduce risk for EVT build. - Change Type-C USB2 port drive strength. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on chell proto Change-Id: Icf31f08302c89b2e66735f7036df914c0a0b9e8c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d00abc12efa69a99e6b0272228f52fb29e6b9180 Original-Change-Id: I63bda0b06c7523df9af9aed9b82280133b01d010 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313825 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12598 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03google/lars: SPD change for Proto boarddavid
Update Memory ID for Proto board Update detection of single/dual channel memory to use SPD Index (Memory ID) Remove boardid.h as it is no longer needed BUG=None BRANCH=None TEST=Build and Boot Lars (Proto) Change-Id: I100b0fec4bf555c261e30140109cb0f36576130c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24a4fddf4f1a4441fca8783cfa451e220ff986d8 Original-Change-Id: I636e881cb3fb9a0056edea2bc34a861a59b91c8f Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313903 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12593 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/kunimitsu: Updated Micron SPD dataBrandon Breitenstein
Updated Micron SPD data to correct values BUG=none BRANCH=none TEST=Tested on FAB 4 with Micron Dimm CQ-DEPEND=CL:312546 Change-Id: Iffe2917f083e4de7944c7f249cbf55bd199f6282 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 00234d81df38139312145c89cbf38d8ac3af5735 Original-Change-Id: Ifcc85cd1aae61e02b820cb25733dfb0680410107 Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313003 Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com> Original-Tested-by: Freddy Paul <freddy.paul@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12592 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/kunimitsu: FAB 4 update for Rcomp Target tableBrandon Breitenstein
Changed index 3 to be an exception of the default Rcomp Value BUG=None BRANCH=None TEST=Tested on FAB 4 SKU 1 Change-Id: I154c254835c4f6995183840cc241feeb9a448cdb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f08eba3cf623b5869a7bb03fb3b6ba084cdd1622 Original-Change-Id: I0fbcff2c3526c4ed7cf90088ca23b43774cb9f8f Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312715 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/12591 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/Kunimitsu: FAB 4 SPD changesBrandon Breitenstein
Updated Memory IDs and SKU IDs for FAB 4 Updated detection of single/dual channel memory to use SPD Index (Memory ID) Added spd files for new dimms Removed boardid.h as it is no longer needed BUG=None BRANCH=None TEST=Tested on FAB4 SKU1 and SKU3 Change-Id: I60403c0e636ea28797d94cff9431af921631323e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ce39dc3b0b9448635f878ce8c1aea5b4743594c4 Original-Change-Id: I870b3dfa2c4f358defb9263e759de477bb32e620 Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312546 Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com> Original-Tested-by: Freddy Paul <freddy.paul@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/12590 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03mediatek/mt8173: Add a stub implementation of the MT8173 SoCYidi Lin
BUG=chrome-os-partner:36682 TEST=emerge-oak coreboot BRANCH=none Change-Id: I748752d5abca813a0469d3a76e4d40fcbeb9b959 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ece2f412d94f071a6f5f1dbed4dfaea504da9e1a Original-Change-Id: I1dd5567a10d20840313703cfcd328bec591b4941 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292558 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12587 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02lippert/frontronner-af & toucan-af: Fix IASL warningsMartin Roth
Not all the paths through the _OSC method returned a value. According to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized GUID. Fixes warnings for both platforms: dsdt.aml 1143: Method(_OSC,4) Warning 3115 - ^ Not all control paths return a value (_OSC) dsdt.aml 1143: Method(_OSC,4) Warning 3107 - ^ Reserved method must return a value (Buffer required for _OSC) Change-Id: Ibaf27c5244b1242b4fc1de474c371f54f930dcb6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12530 Tested-by: build bot (Jenkins) Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02mainboard/intel/d510mo: Add Intel D510MO mainboardDamien Zammit
Board uses Pineview native raminit Board boots from grub to linux kernel VGA needs work, currently headless machine Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/10074 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-01mainboard/asus/kgpe-d16: Enable GART by defaultTimothy Pearson
Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12067 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-30mainboard/intel: Add Little PlainsMarcin Wojciechowski
This adds a new mainboard: Little Plains for Intel's atom c2000 It was based on Mohon Peak board with some minor changes This board is not available as standalone product It is a managment board for Intel Ethernet Multi-host Controller FM10000 Series The FSP package is available from Intel: https://www.intel.com/fsp Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350 Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com> Reviewed-on: https://review.coreboot.org/12503 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHzTimothy Pearson
The CPU <--> CPU HT wiring on this board has only been validated to 2.6GHz. While higher frequencies appear to function initially, and in fact function when only one CPU package is installed, dual CPU package systems will lock up after around 6 - 12 hours of uptime due to presumed HT link errors at the higher (>= 2.8GHz) HT clocks. If applications are not being used that stress the coherent fabric, then the uptime before hang may be much longer. Users attempting to overclock the HT links are advised to "burn in test" the HT links by running memtester locked to a node with no local memory installed. Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12064 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-30bachmann/ot200: Remove DRIVERS_I2C_IDREG Kconfig symbolMartin Roth
As far as I can tell the Kconfig symbol DRIVERS_I2C_IDREG never actually existed in the coreboot codebase. I didn't see anything that it might have been a typo of. Change-Id: Ib17de670e38e07ab4a4745143c42fa85da1754e1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12563 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2015-11-27ibase/mb899: Fix IASL warning and remarkMartin Roth
- Add an empty Operating Region for the empty _REG method - Move Named objects out of _CRS Method - Remove Kconfig default disabling IASL warnings as errors Fixes these items: dsdt.aml 1449: Method (_CRS, 0) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 1458: Method (_REG, 2) Warning 3079 - ^ _REG has no corresponding Operation Region Change-Id: I801a84468097687c91d6ee3f44cec06243355fac Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12531 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-27kontron/986lcd-m: Fix IASL warning and remarkMartin Roth
- Add an empty Operating Region for the empty _REG method - Serialize _CRS Method - Remove Kconfig default disabling IASL warnings as errors Fixes IASL Warning and remark: dsdt.aml 1451: Method (_CRS, 0) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 1460: Method (_REG, 2) Warning 3079 - ^ _REG has no corresponding Operation Region Change-Id: I4aa59468a89c4013146ab34004476a0968c60707 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12521 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-11-26mainboard/asus/kgpe-d16: Add missing IOMMU setupTimothy Pearson
Change-Id: I9a00bdbcd47804b6d83c0231cd515773d02ff951 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12527 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-26mainboard/asus/kgpe-d16: Add IOMMU nvram configuration optionTimothy Pearson
Change-Id: I45b04e8fbdfc65603e1057f7b0e5a13d073fe348 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12048 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24lenovo t400: Fix IASL warning and remarkMartin Roth
If any path in a method returns a value, IASL expects that all paths within that method will return a value. Presumably, the ATPX would not need a return value if Arg0 is anything other than 0, so just return a zero. - Serialize ATPX method to make IASL happy. This means that it can only be used by one thread at a time. Fixes these issues: dsdt.aml 2581: Method (ATPX, 2, NotSerialized) { Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 2581: Method (ATPX, 2, NotSerialized) { Warning 3115 - ^ Not all control paths return a value (ATPX) Change-Id: I14aeab0cebe4596e06a17cffc36cc01b953d7191 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12518 Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24google/rambi: Fix IASL warnings _CRS must return a valueMartin Roth
The Touchpad and Touchscreen _CRS methods do not return an interrupt value if the I2c busses that the devices are on are not in PCI mode. Previously they didn't return any value if they weren't in PCI mode. This patch has them return an empty resource template. Fixes these warnings: dsdt.aml 2813: Method (_CRS) Warning 3115 - ^ Not all control paths return a value (_CRS) dsdt.aml 2813: Method (_CRS) Warning 3107 - ^ Reserved method must return a value (Buffer required for _CRS) dsdt.aml 2832: Method (_CRS) Warning 3115 - ^ Not all control paths return a value (_CRS) dsdt.aml 2832: Method (_CRS) Warning 3107 - ^ Reserved method must return a value (Buffer required for _CRS) Change-Id: I02a29e56a513ec34a98534fb4a8d51df3b70a522 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12519 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24iwave/IWRainBowG6: Fix IASL warning and remarkMartin Roth
- Add an empty Operating Region for the empty _REG method - Serialize _CRS Method - Remove Kconfig default disabling IASL warnings as errors Fixes IASL Warning: dsdt.aml 1362: Method (_REG, 2) Warning 3079 - ^ _REG has no corresponding Operation Region Fixes IASL remark: dsdt.aml 1353: Method (_CRS, 0) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) Change-Id: Iff01613a6e3238469c1fcb8d74f5e98d18420aaf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12515 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24ec/lenovo/h8: Fix IASL warningsMartin Roth
If any path in a method returns a value, IASL expects that all paths within that method will return a value. Presumably the MKHP method wouldn't get called unless there were a pending event, but if no event is found, return a zero. Fixes IASL warning: dsdt.aml 1785: Method (MHKP, 0, NotSerialized) Warning 3115 - ^ Not all control paths return a value (MHKP) This was the only IASL warning in most lenovo mainboards. Change-Id: Id93dcc4a74bd4c18b78f1dde821e7ba0f3444da3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12517 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24superio/smsc/mec1308: Fix IASL warningsMartin Roth
The SIO device needs to provide an _ADR object with the IO address as well as the address in the OperationRegion. ACPI provides two different Resource Descriptor Macros to describe the I/O areas required for a device. The FixedIO macro is only valid for 10-bit IO addresses. Use the IO macro instead. Thank you to recent IASL that allows for addition in the ASL file. :) Fixes these warnings: dsdt.aml 2276: Device (SIO) { Warning 3141 - ^ Missing dependency (Device object requires a _HID or _ADR in same scope) dsdt.aml 2390: FixedIO (0xa00, 0x34) Warning 3060 - ^ Maximum 10-bit ISA address (0x3FF) dsdt.aml 2394: FixedIO (0xa00, 0x34) Warning 3060 - ^ Maximum 10-bit ISA address (0x3FF) Lumpy now compiles its ASL tables with no warnings. Re-enable Warnings as errors. Change-Id: Id26e234eadaa3b966e8f769cb9f9fb7ea64fc9e3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12520 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24intel/d945gclf: Fix IASL warning and remarkMartin Roth
- Add an empty Operating Region for the empty _REG method - Serialize _CRS Method - Remove Kconfig default disabling IASL warnings as errors dsdt.aml 1445: Method (_CRS, 0) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 1454: Method (_REG, 2) Warning 3079 - ^ _REG has no corresponding Operation Region Change-Id: I2b64609c929af62c2b699762206e5baf58fbdb8b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12523 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24AMD/bettong: Add UART supportZheng Bao
The function delay in uart8250mem.c is not enough for hudson. I guess there are some problems in lapic_timer(). I uploaded a patch to gerrit to show the way to enable UART feature. http://review.coreboot.org/#/c/12343/4 Currently the HUDSON_UART is unchecked by default. Select HUDSON_UART to enable this feature. The UART is test at BIOS stage. Since it is not a standart UART device, the windows internal UART driver doesnt support it. I guess we need a driver to use it on windows. Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11749 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-24amd/amdfam10: Control Fam15h cache partitioning via nvramTimothy Pearson
Add options to control cache partitioning and overall memory performance via nvram. Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>