| Age | Commit message (Collapse) | Author |
|---|
|
Rather than hardcoded values, simply change these to -25% of the
defaults for Power Saving, and +25% for Performance.
Change-Id: I16aeb4d5dc25a3f240a775509276c9d3189e9699
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84661
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The Windows driver only checks PCI0, so move the window accordingly
so that it can be used.
Tested on `starlite_adl` by booting Windows 11 installation medium.
Prior to this patch, it would flag that the security requirements
were not met - it now happily installs.
Change-Id: I5d0d062502af99104690f9a9affec09f42b5bc71
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84663
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
This pin is used by the DisplayPort connector for Hot Plug.
Change-Id: I3c63e2e3e168a915daee81afd6a9084a3f01b986
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84662
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Override the PL4 to the maximum power the battery can provide
without a charger connected to prevent drawing too much power.
Change-Id: I2945e1ed0f33ab6692631e327c1457980b353c06
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84660
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The wrong definition was used, so the code had no effect.
The ID for the processor used is `b06e0`.
Change-Id: I36e13074a77b93871c1d86664e35a33afe39a402
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84659
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Some boards use hubs for devices, so correct the ACPI configuration
for these ports. Also, add more information to the comments for the
ports.
Change-Id: I8472130aba8e777557cf68280fa0058dbeb77df9
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
|
|
Change-Id: I6fb228bab06b050ac1a51de46ffe5c0d3d80adfb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
|
|
Make the I2C speed user configurable from CMOS. Both the touchscreen
and accelerometer support running at 100MHz or 400MHz. They perform
better at 400MHz but use more power - this patch lets the user choose.
Change-Id: Ia1b08d7ec6212418bb95d0a52077f01c930f8830
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
|
|
Change-Id: Ibe47f242ce12fc4906baeee89393a34a56eaca76
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83881
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
None of these boards support or use S0ix so c6dram isn't needed, so
disable it.
Change-Id: I8124899a1f7ce20442f28919f7315ee7e52355e5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84632
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There is only 1 Type-C port, the rest are Type-A.
Tested on Linux by verified the correct names are shown in dmesg.
Change-Id: Iaf5a29f3d25f299658116fa61ae488775e2b70a2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84642
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Port 2 is a hub, used for the internal keyboard and the card reader.
Adjust this to a hub.
Change-Id: I3a9b9e6803934291b46fb502ff1b3b088c047703
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
|
|
Change-Id: I8ea01c21ec03c11e9599684dbe51d103c07c172a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84640
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The existing GPIO configuration was IRQ heavy; tweak this to reduce
the number of interrupts.
Change-Id: I6d23bea5ec12e86a3606186edb29636540283fa3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84639
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
A debug configuration was left in the patch when it was uploaded,
remove this.
Change-Id: I3ab8137d3841dfa200750a97969af5dca477d7e2
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
|
|
The wireless GPIOs don't need to be configured in the bootblock,
so set them up in ramstage.
Change-Id: Iab399884edde29891e66ffc097cf6f3dff71c351
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84637
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add options to disable the card reader and fingerprint reader.
Change-Id: Iee985aa2db3da5c2d393b8dc2dc722e990c43272
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84631
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These aren't used so remove them.
Change-Id: I0e8ef5e3c992f8ff51e4755b80379acfe0361e99
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84630
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h
to static.h"), sources that require access to the devicetree should
directly include static.h so that it can be removed from device.h,
eliminating unnecessary dependencies on static.h for files that only
need the types and function declarations in device.h.
Change-Id: Ia793666fda47678764fd33891fddb4aecf207bd4
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This isn't required by these boards as they both use PTT.
Change-Id: I66b3f614914e51116f3cabe457205fb6b3528387
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84629
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tested on 24.04, disabling Turbo Boost increases power consumption
which doesn't align with the aim of the Power Saver profile.
Change-Id: I19e8189ee6c44d19bf222c921429284ed1e1aa2a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84628
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I68b285ff098127b7becf4aa8736e66fd6b2c4a32
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: Ibb92d76f15be71ecb1e2187c7e235235585f8793
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: I5beda22208fe17338d4136f9d38fd50e55054b01
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: I140d597750001ad22e2bb1b6971011d2b3bb2bbc
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84272
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Tested on Ubuntu 24.04 by verifying dmesg output and that USB
2.0 and 3.0 devices are registered correctly.
Change-Id: I803a23007f49ea45abc68421e867535081e31b3f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84271
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
DPTF is not used on this platform so disable the
PCI device.
Change-Id: I763ab948a79e3a020c1b89c69c714dd0d8f54812
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84270
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
These aren't used so remove them.
Change-Id: I6fd33c5242adb93b1251af9c5b11be3734a7aceb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: I6bab0a316ea7d0f7dfbf599e5c08517cee559635
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
MAINBOARD_HAS_TPM2 should only be selected for the boards
that have memory mapped TPMs. The ones that use Intel PTT
don't need it.
Change-Id: I02b5b0912afbd7c4634c208bb17db16d0ac7ba99
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
DPTF is not used on this platform so disable the
PCI device.
Change-Id: I7fa01936568108dd7707a3c2ea7041a1198533b5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84266
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These aren't used so remove them.
Change-Id: I6b9cf29843047bff9a37f82b899ff1d10b206888
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 24.04
No known issues.
https://starlabs.systems/pages/starfighter-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I046e70845a5201d6f6ab062aee91fa8be9728737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: I063062d875be61875da136228db06a39bc434833
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The platform uses eSPI so these are not needed.
Change-Id: I507aa59fcf2540ae6170896a51aa952f5e73eee8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83691
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: Ibb167b8dc379ca331812255c3e7e049556f2b57b
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Change-Id: I7050a4d12efd65c7026abf3e45961e2061b7170a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
These aren't used so remove them
Change-Id: I340b3474fba1bc7fbde520138ae99c3e355882bf
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: I63612af7320dfdbe57029b898b4cf07e9d6f13b0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 22.04
* Manjaro 22
No known issues.
https://starlabs.systems/pages/byte-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idff2d883a8c29f0fee9d633708aac92061a45132
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: Icc01852dc5bd04cfa151e8fa7c5bcc160ed978c6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84156
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I4fc824bef1daf8c12eb671c58de9019ce5a23a2e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
|
|
Remove the ITE mirror functionality; all devices will mirror
automatically when they exit G3, and this is good enough.
Change-Id: I9b82e1b1386b4607dfe7da9b25ba432ec0303cf8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83629
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This reverts commit 2eb5c1e83ef5206f384846d7514c3aebcaec5bb8.
Reason for revert: The latest release of FSP will not boot
without a display being connected using this VBT. The original
VBT does not have this issue, nor is the original issue that
commit 2eb5c1e83ef5206f384846d7514c3aebcaec5bb8 fixed.
Revert it to restore booting when there is no display.
Change-Id: I05f9037cd68b8b29e69156e2372a544985f4442e
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
Change-Id: I27568d1205216f697b48ffb09ce5208505718978
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83863
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The property `has_cdm` only existed in an early patchset, the version
that was merged only requires `cdm_index` so remove the former that
was added in c6c75dfbaeff208c17bb47fdede855286e12d857.
Change-Id: I62a9456e9a4f1571328ba6fd09ae383a8fd11767
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83796
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Remove some unused GPIOs and configurations for GPIO's that
aren't even connected.
Change-Id: I5b4691a0b5e8b1348304d11c1d59aa60517041ec
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83626
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The GPIOs for WiFi and Bluetooth are also connected to the EC.
They are controlled from there so remove the configuration here.
Change-Id: I7aef1b821420daf5ea9f6ae107021e5d406a5ec3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
The platform uses eSPI so these are not needed.
Change-Id: I81470658263f4b601c9964ff5bed86b22d24df3b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83624
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use the USB ACPI to add entries for the USB and TCSS ports.
Change-Id: Iab8b6e03c8c05e459fb354bc008109c873a4846f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83623
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 22.04
* Manjaro 22
No known issues.
https://starlabs.systems/pages/starlite-specification
Change-Id: I8724e578c21353032b844b20b868348580ff561b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: I3c4a963b233f549c7a76c76333af87c887550ac3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
The Windows drivers require the subsystem ID to match on the PCI
device, so set these to allow the driver to install.
Change-Id: I01b36554d5322018efc72734a8e749cc06263577
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83621
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Not setting tcss_aux_ori in devicetree is the same as
setting it to zero so remove it.
Change-Id: Ia0e90179dd05b23f1f36935be51327250c5a8684
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
In order to clean up a bit, drop devices which are equivalent to the
ones from chipset devicetree.
Change-Id: I92765b404508901c7e84fad0bca30489cf69abac
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83456
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
The cpu_cluster device is defined in the chipset devicetree. So drop it
from the mainboards.
Change-Id: Ib84e7804c03f1c0779ab7053a09e397a267a3844
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83523
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The cpu_cluster device is defined in the chipset devicetree. So drop it
from the mainboards.
Change-Id: I65bfeaf0b8771c123c0615531c2cc608b222949b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83440
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I7114612e686a0bf3cfc241f45fa62077fad16f5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: Ia3df14ebd365c00902b5d2ba300d8ade4c2d6c26
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Add Kconfig strings for the battery:
* Model
* OEM
* Technology
Change-Id: Ibbce87ad54874f490af45c41f31956a7e9e996f3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81401
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These values were configured based on a default value of 110, but for
CML, it's actually 100.
Adjust it accordingly.
Change-Id: Ibffeeab67a7277625db9bdedca36d759ff0e72f6
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81414
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure the TCC Offset based on the active power profile
Change-Id: I58940441a7cefc7a2a07e5e9f7e8a15cb8730ef3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
All other variants use a function and definitions to get the power
profile. Make this board to the same.
Change-Id: I07ce71e20bd71229bb0cd3438ab59140cd0d8b42
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81412
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I27062c38c10df1d03f563b2f5391f79a3b6ee4fe
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81411
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the
same value and conveys additional information to the reader. Done with a
bulk search and replace operation.
Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
Change-Id: I972516443bc57e193aefd54516ca994087d92054
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Change-Id: Ib8f7ac7e586390a1d25cbe84d6d4c3ba31ff078f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81811
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I7626fe9d4740e9f141a674fa457b0714fc38ed91
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Certain SSDs are not detected in the default time window, so
change this to 50ms to allow these SSDs to be detected.
Change-Id: I60e66096ef9ea0146a1bc72c5c74234353509439
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81398
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The CPU port is not used so disable it.
Change-Id: Ia150f99c4679323f08e44b0885af04113dfabd87
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Change-Id: I8dc80c5bdde61f3c2dc5c9dc67fbc752de7a103f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
This reverts commit 8902dfa2bdf33b8ae69fa0d5161b28f67f8c0881.
This was originally assumed to be an FSP/Descriptor/PMC mismatch
but it turns out that the problem was coreboot incorrectly
detecting ASPM support on devices.
Revert so that a proper fix can be applied.
Change-Id: I3f83e79c1b21a6c3799abed4a279b8bd59ac3570
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81395
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adjust the size of the ME partition to match the descriptor
Change-Id: Ibdec5121518452ec16cebcc4f2fb563355373be3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81394
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
No variants were ever built with CNVi cards, so disable
this device.
Change-Id: I3725465eae0c7ade3dafa03add151353818ee761
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
The tcss.asl doesn't just relate to tcss, it is required for core
scheduling, so include it for all platforms.
Change-Id: I781ba8756e06133799e8d6d91302968cc3ea0a56
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80485
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib7beed7218f317bc2352b65a6191ef1cdaa0742d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
Change-Id: Ied455ff29b151fb5f4bca26a189b1d4104d8cede
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80595
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure PMC mux in devicetree. This allows PD controllers to be
used for both video and power delivery.
Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD
display can supply power and display video output.
Change-Id: I580b148b036e62fbcab50d1ca2ab1ed021cfed6b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Configure PMC mux in devicetree. This allows PD controllers to be
used for both video and power delivery.
Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD
display can supply power and display video output.
Change-Id: I9e49612d7f165a9c9604093535f7b141a4c7048c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79426
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The TCC offset is configured in devtree.c, so remove it from
the devicetree.
Change-Id: I044a68854cc142b057cf31b4e2456d2ad1d0dd3a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.
This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4790adb41cb62c8c8dd44261a2926dfb6350955a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80111
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
|
|
Use the references from the chipset devicetree as this makes the
comments superfluous.
Change-Id: Ia004de6606a1685822d5567123887c60d89e3119
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3a317d031e71f86afc50b229d1b97197552f4fa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
|
|
Change-Id: I41b3ed4926fe77c5729672fd7a7bcb8ca0c5c216
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79033
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
POWER_STATE_OFF_AFTER_FAILURE can't be directly selected since it's a
choice, so instead set POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n, as
it's functionally equivalent. This fixes the warnings generated by
the pre-commit hook Kconfig check.
It is necessary to override and set default n in the mainboard Kconfig
as it is set to default y in src/soc/intel/common/block/pmc/Kconfig.
TEST=select starlabs/starbook_adl in menuconfig and verify the default
power-on setting is S5/soft off.
Change-Id: I3ce33517dcc0af693b8db8d1de2926117ad3c16b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78627
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Disable the GpioOverride UPD in FSP M, and comment out the Clock Request
GPIOs to ensure that coreboot doesn't touch them.
This solves behaviour that can only be described as weird:
* Devices connected to Root Ports don't initialise
* Hang seen when entering S5
* Hang when edk2 is reached
Change-Id: Idf8d2112a1c44064af73bb54fd3e1a1a429e0649
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
This Kconfig option is used as a failback when `get_uint_option`
fails. It will fail after coreboot is flashed, as the cfr code has
not yet setup the options.
Change the default to OFF, so when it does fallback, it's the correct
behaviour.
Change-Id: I5d06047fe23322520e9c84ded8f1941f6d716a51
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: Id42d07aabfd08c6c7a38515f9cf4b749750deecd
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78202
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is required for the HDA device to work.
Change-Id: I5fd3617c4cb1e69b7e0ecf6cddf4c143da99b927
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78201
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Certain devices are enabled in Alder Lakes chipset.cb, so remove
them from the devicetree.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78198
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I1b0052b569b575fec7893322dec0280c9f1ed79f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78197
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Updating FSP to v4301.01 caused a strange flicker when connecting
an external display. Update the VBT to 251 from 242 with the exact
same settings to resolve this.
Change-Id: I36bb2cc92e744e761ec6af9c026c429373c1750a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Enable the PD interrupt GPIO, GPP_B11, so that HPD works when
Thunderbolt is disabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie37976d58921b7a12dff16d93d7ac9bdd92edbea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
A19 was incorrectly labelled as TCP0 HPD. It is not connected
so configure it accordingly.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5aea723c2e8c0758d413bbc4bfd0ce92b22d0c87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Certain devices are enabled in Alder Lakes chipset.cb, so remove
them from the devicetree.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I929af0bed6c2e1024b4787424a8fe466edce5a36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
With the Tc-cold handshake, there's a fast flicker when connecting
external displays. With it disabled, it's just one "flick", so use
this as it's lesser of two evils.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie42b935d3e69beff6a1e503a8dee69554123b4f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
For Thunderbolt to be disabled, `UsbTcPortEn` and `TcssXhciEn`
also need to be disabled.
Change-Id: Ie02c1e0ea7583bbd78e25c8184e2cdf2b6281741
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
