Age | Commit message (Expand) | Author |
2020-09-19 | apollolake boards: Enable CSE in devicetree | Subrata Banik |
2020-09-10 | mb/siemens/mc_apl2/gpio: Fix code style | Maxim Polyakov |
2020-09-10 | mb/siemens/mc_apl2/gpio: Undo set DRIVER for GPO | Maxim Polyakov |
2020-06-30 | src: Remove whitespaces before tabs | Elyes HAOUAS |
2020-06-19 | Kconfig: Escape variable to accommodate new Kconfig versions | Patrick Georgi |
2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
2020-04-04 | mainboard/siemens: Use SPDX for GPL-2.0-only files | Angel Pons |
2020-03-31 | security/vboot: Decouple measured boot from verified boot | Bill XIE |
2020-03-18 | mainboard/[^a-p]*: Remove copyright notices | Patrick Georgi |
2019-11-12 | src/mainboard/siemens: Use PTN3460 chip driver | Uwe Poeche |
2019-11-12 | mb/siemens/mc_apl6: Enable VT-d feature | Werner Zeh |
2019-11-11 | mb/siemens/mc_apl6: Add TPM to devicetree | Werner Zeh |
2019-11-11 | mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller | Werner Zeh |
2019-11-11 | mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge | Werner Zeh |
2019-11-11 | mb/siemens/mc_apl6: Enable VBOOT per default | Werner Zeh |
2019-11-11 | mb/siemens/mc_apl6: Add new mainboard based on mc_apl3 | Werner Zeh |
2019-10-18 | mb/siemens/mc_apl{3,5}: Remove __weak symbol from GPIO functions | Werner Zeh |
2019-09-25 | mb/siemens/mc_apl{2,4,5}: Enable VBOOT | Werner Zeh |
2019-09-05 | mb/siemens/mc_apl5: Disable IGD if no EDID data available | Mario Scheithauer |
2019-07-18 | mb/siemens/{mc_apl1,...,mc_apl5}: Fix GPIO settings | Mario Scheithauer |
2019-07-18 | mb/siemens/mc_apl1: Disable all UHS-I SD-Card speed modes | Mario Scheithauer |
2019-07-12 | mb/siemens/mc_apl3: Enable LPSS UART 1 | Mario Scheithauer |
2019-07-11 | mb/siemens/{baseboard,mc_apl3,mc_apl4,mc_apl5}: Fix GPIO_168 | Mario Scheithauer |
2019-07-11 | mb/siemens/{mc_apl1,...,mc_apl5}: Reduce eMMC bus speed mode | Mario Scheithauer |
2019-06-21 | siemens/mc_apl5: Change PTN interface settings | Mario Scheithauer |
2019-06-21 | siemens/mc_apl5: Enable TPM support | Mario Scheithauer |
2019-06-06 | siemens/mc_apl5: Add own GPIO table | Mario Scheithauer |
2019-05-29 | src/mainboard: Add missing 'include <types.h>' | Elyes HAOUAS |
2019-05-06 | mb/siemens/mc_apl2: Limit SD-Card speed to DDR50 | Werner Zeh |
2019-04-15 | mb/siemens/mc_apl4: Remove usage of external RTC | Werner Zeh |
2019-04-15 | mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants | Werner Zeh |
2019-04-08 | siemens/mc_apl5: Remove reduced clock rate for I2C0 | Mario Scheithauer |
2019-04-04 | siemens/mc_apl4: Provide CLK on APL Pin PMU_SUSCLK | Uwe Poeche |
2019-03-15 | mb/mc_apl1/variants/mc_apl5: Drop unused '#include <lib.h>' | Elyes HAOUAS |
2019-03-06 | mb/siemens/{mc_apl1,mc_tcu3}: Fix typo on "Display" | Elyes HAOUAS |
2019-03-04 | arch/io.h: Add missing includes | Kyösti Mälkki |
2019-02-13 | siemens/mc_apl4: Enable HW SPI TPM on mainboard mc_apl4 | Uwe Poeche |
2019-02-13 | siemens/mc_apl2: Remove double entry from devicetree | Mario Scheithauer |
2019-02-05 | mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5 | Werner Zeh |
2019-01-30 | siemens/mc_apl2: Change SERIRQ mode | Mario Scheithauer |
2019-01-30 | siemens/mc_apl2: Correct whitespace of devicetree | Mario Scheithauer |
2019-01-30 | siemens/mc_apl2: Activate TPM support | Mario Scheithauer |
2019-01-16 | siemens/mc_apl4: Change UART_FOR_CONSOLE index | Mario Scheithauer |
2018-12-17 | siemens/mc_apl4: Enable RTC RX6110SA on this mainboard | Uwe Poeche |
2018-12-17 | siemens/mc_apl4: Enable LVDS Display on mc_apl4 | Uwe Poeche |
2018-12-17 | siemens/mc_apl4: Add GPIO configuration | Uwe Poeche |
2018-11-29 | siemens/mc_apl5: Disable PCI clock outputs on XIO bridges | Mario Scheithauer |
2018-11-29 | siemens/mc_apl5: Set bus master bit for on-board PCI device | Mario Scheithauer |
2018-11-29 | siemens/mc_apl5: Enable SDCARD | Mario Scheithauer |
2018-11-27 | siemens/mc_apl5: Adjust the settings for the PCIe root ports | Mario Scheithauer |
2018-11-26 | siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN read | Mario Scheithauer |
2018-11-23 | siemens/mc_apl4: Set CPU clock to minimum ratio | Werner Zeh |
2018-11-18 | siemens/mc_apl5: Add new mainboard variant mc_apl5 | Mario Scheithauer |
2018-11-16 | mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VAR | Elyes HAOUAS |
2018-11-16 | src: Remove unneeded include <lib.h> | Elyes HAOUAS |
2018-11-16 | mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree | Peter Lemenkov |
2018-11-16 | siemens/mc_apl4: Clean up ramstage | Mario Scheithauer |
2018-11-16 | siemens/mc_apl4: Overwrite swizzle data for LPDDR4 | Mario Scheithauer |
2018-11-12 | siemens/mc_apl4: Enable SDCARD | Mario Scheithauer |
2018-11-12 | siemens/mc_apl4: Remove external RTC from I2C0 | Mario Scheithauer |
2018-11-12 | siemens/mc_apl4: Enable all PCIe root ports | Mario Scheithauer |
2018-11-12 | siemens/mc_apl4: Remove reduced clock rate for I2C0 | Mario Scheithauer |
2018-11-12 | siemens/mc_apl4: Disable CLKREQ of PCIe root ports | Mario Scheithauer |
2018-11-12 | siemens/mc_apl3: Disable PCI clock outputs on XIO bridges | Mario Scheithauer |
2018-11-12 | siemens/mc_apl3: Set Full Reset Bit into Reset Control Register | Mario Scheithauer |
2018-11-12 | siemens/mc_apl3: Set bus master bit for on-board PCI device | Mario Scheithauer |
2018-11-12 | siemens/mc_apl3: Remove the correction of the Tx signal for SATA | Mario Scheithauer |
2018-11-12 | siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices | Mario Scheithauer |
2018-11-07 | siemens/mc_apl4: Add new mainboard variant mc_apl4 | Mario Scheithauer |
2018-11-07 | siemens/mc_apl2: Adjust GPIO settings for mc_apl2 | Mario Scheithauer |
2018-11-07 | siemens/mc_apl3: Disable I2C7 over devicetree | Mario Scheithauer |
2018-11-07 | siemens/mc_apl3: Enable all PCIe root ports | Mario Scheithauer |
2018-11-07 | siemens/mc_apl3: Remove reduced clock rate for I2C0 | Mario Scheithauer |
2018-11-07 | siemens/mc_apl3: Disable CLKREQ of PCIe root ports | Mario Scheithauer |
2018-11-07 | siemens/mc_apl3: Adjust GPIO settings for mc_apl3 | Mario Scheithauer |
2018-10-30 | siemens/mc_apl3: Add new mainboard variant mc_apl3 | Mario Scheithauer |
2018-10-08 | Move compiler.h to commonlib | Nico Huber |
2018-10-06 | soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD | Furquan Shaikh |
2018-10-01 | siemens/mc_apl1: Activate clock spreading for PTN3460 | Mario Scheithauer |
2018-09-27 | siemens/mc_apl1: Add new mainboard variant mc_apl2 | Mario Scheithauer |
2018-09-27 | siemens/mc_apl1: Make the DDR memory swizzle data configurable | Mario Scheithauer |
2018-08-31 | siemens/mc_apl1: Correct the Tx signal from SATA interface | Mario Scheithauer |
2018-08-28 | siemens/mc_apl1: Extend circuit life by clock gating and power gating | Mario Scheithauer |
2018-08-27 | siemens/mc_apl1: Disable PCI clock outputs on XIO bridge | Mario Scheithauer |
2018-08-24 | siemens/mc_apl1: Select DDR50 mode for eMMC | Mario Scheithauer |
2018-08-23 | siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboard | Mario Scheithauer |
2018-08-23 | siemens/mc_apl1: Move board specific things to mc_apl1 variant | Mario Scheithauer |
2018-06-06 | soc/intel/common/block: Add common chip config block | Subrata Banik |
2018-04-27 | siemens/mc_apl1: Move board specific things to mc_apl1 variant | Mario Scheithauer |
2018-04-26 | siemens/mc_apl1: Provide baseboard and variant concepts | Mario Scheithauer |