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2024-08-26mb/*/*/early_init.c: Remove unused included southbridgeElyes Haouas
Change-Id: Ia3fda208f5cb2e0d8a1e4da2c4392bc0f326d1ed Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84076 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mb/*: Remove old USB configurations from SNB/bd82x6x boardsKeith Hui
Remove USB configurations and data structures from northbridge devicetree (SNB+MRC boards) and bootblock/romstage C code (native-only SNB boards). All USB configurations are drawn from southbridge devicetree going forward. Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-08mb/*: Add consolidated USB port config for SNB+MRC boardsKeith Hui
For each sandybridge boards with option to use MRC or native platform init code, add a copy of the board's USB port config, consolidated between both code paths, into the southbridge devicetree, using special values allocated for this consolidation. These get hooked up in a separate patch. Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-07mb/**/hda_verb: Use `AZALIA_PIN_CFG_NC(0)`Angel Pons
Replace `0x411111f0` with `AZALIA_PIN_CFG_NC(0)`, which evaluates to the same value and conveys additional information to the reader. Done with a bulk search and replace operation. Change-Id: Ibd84daec017bc1ab1ee4edd906fda80231c134cc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-03-26mb/roda: Remove blank lines before '}' and after '{'Elyes Haouas
Change-Id: Id039ad885d2f08bc3fe09aca740a72a5820f7fcc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
2024-02-23arch/x86/ioapic: use uintptr_t for IOAPIC base addressFelix Held
Use uintptr_t for the IOAPIC base parameter of the various IOAPIC- related functions to avoid needing type casts in the callers. This also allows dropping the VIO_APIC_VADDR define and consistently use the IO_APIC_ADDR define instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I912943e923ff092708e90138caa5e1daf269a69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-02-18mb/opencellular to mb/roda: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: Ia2100d26027a7f71739d5445f781b52c517ed966 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80594 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-31device/device.h: Rename busses for clarityArthur Heymans
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-24mb/lenovo to mb/squared: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I4790adb41cb62c8c8dd44261a2926dfb6350955a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80111 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-12-20mainboard: Use same indent levels for switch/caseFelix Singer
Use same indent levels for switch/case in order to comply with the linter. Change-Id: I602cf024ec84b15b783d36014c725826f9d6595e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79418 Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/*: Update SPD mapping for sandybridge boardsKeith Hui
Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree. Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping. Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-10-25SNB+MRC boards: Migrate MRC settings to devicetreeKeith Hui
For Sandy Bridge boards with MRC raminit support, migrate as much MRC settings to devicetree as possible, to stop mainboard code from needlessly overwriting entire PEI data structure, so they will not interfere with upcoming transition to one standard Haswell way of providing SPD info to northbridge. Some exceptions allowed are described below and in code comments. SPD-related items are kept out of devicetree for now. They will be migrated (with a different representation) with the Haswell SPD transition. google/{butterfly,link,parrot,stout} have max DDR3 frequency set in pei_data to 1600 (2*800), but in devicetree to 666. The reason for the difference seems to be problems with native raminit code. These are converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an added "fix me" tag. asus/p8x7x-series also needs the same treatment, based on testing various memory on p8z77-m hardware. TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested. Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-04-08sb/intel/i82801gx/chip.h: Use 'bool' instead of 'int'Elyes Haouas
This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:66:19: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .c4onc3_enable = 1, ^ /cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:75:32: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .p_cnt_throttling_supported = 1, ^ Change-Id: I691b51a97b359655c406bff28ee6562636d11015 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-23nb/intel/snb: Abolish mainboard_should_reset_usb()Keith Hui
Of the 13 mainboards that implement mainboard_should_reset_usb() hook, all but one do the same: Stop MRC from resetting USB when resuming from S3 suspend. This hook turns out is only here to facilitate a USB reset workaround on samsung/stumpy for an old ChromeOS kernel which is no longer needed. Drop the workaround, the hook, and headers no longer used. roda/rv11/early_init.c is left with no useful code after this patch, so drop it entirely from both bootblock and romstage. Change-Id: Ib3a5a00c0a6b1528e39435784919223d16b3914e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-19treewide: Remove useless "_STA: Status" commentElyes Haouas
Change-Id: I99ded00fa6dadb494c1523d00063dbc1fde95614 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73093 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-17mb/roda/rv11: Remove unuseful "_ALR: Ambient Light Response"Elyes Haouas
Change-Id: I3a846d8e4b70ccb3e6fde448c00376cd0088716c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17mb/rodarv11: Remove unuseful "_ALI: Ambient Light Illuminance"Elyes Haouas
Change-Id: I0cbdcd5a787d99e2579a312a51c63d7fc4120462 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-17treewide: Remove unuseful "_HID: Hardware ID" commentElyes Haouas
Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-04mb/*: Replace SNB PCI devices with references from chipset.cbArthur Heymans
Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-25mainboard: Drop invalid `hyper_threading` optionAngel Pons
Drop the `hyper_threading` CMOS option from most boards, as it's most likely not working properly and causing problems. The main reasons to remove the option are: * The used enum is backwards (0 ---> Enable, 1 ---> Disable) * Platform/SoC code does not honor the `hyper_threading` option Also, remove the now-unused enum used by the `hyper_threading` option. Change-Id: Ia8980a951f4751bc2e1a5d0e88835f578259b256 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69523 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-12-27mainboard/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-23mb,x86/smm: Disable unused IO trapsKyösti Mälkki
Only IO trap #3 for lenovo/x60,t60 and getac/p470 have implemented the IO trap handler. Change-Id: Ibadce174f673e88380f4b6745fd9ed8b73177a13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70367 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-07sb,soc/intel,mb: Drop leftover comments and TODOs in ASLKyösti Mälkki
Change-Id: I74f943e9b616458a16aa13c29706cf1551fcbbb2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-07mb/*/smihandler.c: Drop unused <soc/nvs.h>Kyösti Mälkki
Change-Id: I4819909cf9460ca550af38ca73a50220b77a385f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-12-05nb/intel/gm45: Remove apic 0 from devicetreeArthur Heymans
This is added at runtime. Change-Id: Ife2865f91e3d046bc66e423b2054f56176f57fc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69300 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05nb/intel/i945: Remove apic 0 from devicetreeArthur Heymans
This is added at runtime. Change-Id: I1f684c800de6711d8b0a0aea0d59c8e21d22c14a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69299 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-05cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfmArthur Heymans
C5, C6 and slfm depend on the southbridge and the northbridge to be able to provide this functionality, with some just lacking the possibility to do so. Move the devicetree configuration to the southbridge. This removes the need for a magic lapic in the devicetree. Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-02sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}Elyes Haouas
Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-01nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans
Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01nb/intel/gm45: Hook up PCI domain and CPU bus ops to devicetreeArthur Heymans
Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69293 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01cpu/intel/model_206ax: Remove fake lapic deviceArthur Heymans
Instead of using a fake lapic device hook up the cpu cluster to chip cpu/intel/model_206ax. The lapic device is also not needed as the mp init will allocate it for the BSP at runtime. Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-01cpu/intel/sandybridge: Use enum for ACPI C statesArthur Heymans
Also remove the now unnecessary comments from the devicetree. Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-11-30nb/intel/sandybridge: Add a chipset devicetreeArthur Heymans
This only moves CPU configuration to a common place. Other PCI devices can be done in follow-ups. Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-13drivers/generic/ioapic: Drop poor implementationKyösti Mälkki
This disables MP table generation for the affected boards since interrupt routing entries would now be completely missing. The mechanism itself is flawed and redundant. The mapping of integrated PCI devices' INTx pins to IOAPIC pins is dependent of configuration registers and needs not appear in the devicetree.cb files at all. The write_smp_table implementation would skip writing any entry delivering to destination IOAPIC ID 0. This does not follow MP table specification. There were duplicate calls to register_new_ioapic_gsi0(), with another present under southbridge LPC device. Change-Id: I383d55ba2bc0800423617215e0bfdfad5136e9ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69488 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-13src/mb: Update unlicensable files with the CC-PDDC SPDX IDMartin Roth
These files contain no creative content, and therefore have no copyright. This effectively means that they are in the public domain. This commit updates the unlicensable empty (and effectively empty) files with the CC-PDDX identifier for license compliance scanning. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I0b76921a32e482b6aed154dddaba368f29ac2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66497 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16src: Remove unused <cf9_reset.h>Elyes Haouas
Found using: diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<" Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-02-25arch/x86: consolidate HPET base address definitionsFelix Held
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO region which is 0xfed00000 on all chipsets and SoCs in the coreboot tree. Since these two different constants are used in different places that however might end up used in the same coreboot build, drop the Kconfig option and use the definition from arch/x86 instead. Since it's no longer needed to check for a mismatch of those two constants, the corresponding checks are dropped too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-10src/mainboard/{amd,roda}: Remove unused <acpi/acpi.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <acpi/acpi.h>' -- src/) <(git grep -l 'SLP_EN\|SLP_TYP_SHIFT\|SLP_TYP\|SLP_TYP_S\|ACPI_TABLE_CREATOR\|OEM_ID\|ACPI_DSDT_REV_\|acpi_device_sleep_states\|ACPI_DEVICE_SLEEP\|RSDP_SIG\|ASLC\|ACPI_NAME_BUFFER_SIZE\|COREBOOT_ACPI_ID\|acpi_tables\|acpi_rsdp\|acpi_gen_regaddr\|ACPI_ADDRESS_SPACE\|ACPI_FFIXEDHW_\|ACPI_ACCESS_SIZE_\|ACPI_REG_MSR\|ACPI_REG_UNSUPPORTED\|ACPI_HID_\|acpi_table_header\|MAX_ACPI_TABLES\|acpi_rsdt\|acpi_xsdt\|acpi_hpet\|acpi_mcfg\|acpi_tcpa\|acpi_tpm2\|acpi_mcfg_mmconfig\|acpi_hmat\|acpi_hmat_mpda\|acpi_hmat_sllbi\|acpi_hmat_msci\|acpi_srat\|ACPI_SRAT_STRUCTURE_\|acpi_srat_lapic\|acpi_srat_mem\|acpi_srat_gia\|CPI_SRAT_GIA_DEV_HANDLE_\|acpi_slit\|acpi_madt\|acpi_lpit\|acpi_lpi_flags\|acpi_lpi_desc_type\|ACPI_LPI_DESC_TYPE_\|acpi_lpi_desc_hdr\|ACPI_LPIT_CTR_FREQ_TSC\|acpi_lpi_desc_ncst\|acpi_vfct_image_hdr\|acpi_vfct\|acpi_ivrs_info\|acpi_ivrs_ivhd\|acpi_ivrs\|acpi_crat_header\|ivhd11_iommu_attr\|acpi_ivrs_ivhd_11\|dev_scope_type\|SCOPE_PCI_\|SCOPE_IOAPIC\|SCOPE_MSI_HPET\|SCOPE_ACPI_NAMESPACE_DEVICE\|dev_scope\|dmar_type\|DMAR_\|DRHD_INCLUDE_PCI_ALL\|ATC_REQUIRED\|DMA_CTRL_PLATFORM_OPT_IN_FLAG\|dmar_entry\|dmar_rmrr_entry\|dmar_atsr_entry\|dmar_rhsa_entry\|dmar_andd_entry\|dmar_satc_entry\|acpi_dmar\|acpi_apic_types\|LOCAL_APIC,\|IO_APIC\|IRQ_SOURCE_OVERRIDE\|NMI_TYPE\|LOCAL_APIC_NMI\|LAPIC_ADDRESS_\|IO_SAPIC\|LOCAL_SAPIC\|PLATFORM_IRQ_SOURCES\|LOCAL_X2APIC\|GICC\|GICD\|GIC_MSI_FRAME\|GICR\|GIC_ITS\|acpi_madt_lapic\|acpi_madt_lapic_nmi\|ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS\|acpi_madt_ioapic\|acpi_madt_irqoverride\|acpi_madt_lx2apic\|acpi_madt_lx2apic_nmi\|ACPI_DBG2_PORT_\|acpi_dbg2_header\|acpi_dbg2_device\|acpi_fadt\|ACPI_FADT_\|PM_UNSPECIFIED\|PM_DESKTOP\|PM_MOBILE\|PM_WORKSTATION\|PM_ENTERPRISE_SERVER\|PM_SOHO_SERVER\|PM_APPLIANCE_PC\|PM_PERFORMANCE_SERVER\|PM_TABLET\|acpi_facs\|ACPI_FACS_\|acpi_ecdt\|acpi_hest\|acpi_hest_esd\|acpi_hest_hen\|acpi_bert\|acpi_hest_generic_data\|acpi_hest_generic_data_v300\|HEST_GENERIC_ENTRY_V300\|ACPI_GENERROR_\|acpi_generic_error_status\|GENERIC_ERR_STS_\|acpi_cstate\|acpi_sw_pstate\|acpi_xpss_sw_pstate\|acpi_tstate\|acpi_lpi_state_flags\|ACPI_LPI_STATE_\|acpi_lpi_state\|acpi_upc_type\|UPC_TYPE_\|acpi_ipmi_interface_type\|IPMI_INTERFACE_\|ACPI_IPMI_\|acpi_spmi\|ACPI_EINJ_\|ACTION_COUNT\|BEGIN_INJECT_OP\|GET_TRIGGER_ACTION_TABLE\|SET_ERROR_TYPE\|GET_ERROR_TYPE\|END_INJECT_OP\|EXECUTE_INJECT_OP\|CHECK_BUSY_STATUS\|GET_CMD_STATUS\|SET_ERROR_TYPE_WITH_ADDRESS\|TRIGGER_ERROR\|READ_REGISTER\|READ_REGISTER_VALUE\|WRITE_REGISTER\|WRITE_REGISTER_VALUE\|NO_OP\|acpi_gen_regaddr1\|acpi_einj_action_table\|acpi_injection_header\|acpi_einj_trigger_table\|set_error_type\|EINJ_PARAM_NUM\|acpi_einj_smi\|EINJ_DEF_TRIGGER_PORT\|FLAG_PRESERVE\|FLAG_IGNORE\|EINJ_REG_MEMORY\|EINJ_REG_IO\|acpi_einj\|acpi_create_einj\|fw_cfg_acpi_tables\|preload_acpi_dsdt\|write_acpi_tables\|acpi_fill_madt\|acpi_fill_ivrs_ioapic\|acpi_create_ssdt_generator\|acpi_write_bert\|acpi_create_fadt\|acpi_fill_fadt\|arch_fill_fadt\|soc_fill_fadt\|mainboard_fill_fadt\|acpi_fill_gnvs\|acpi_fill_cnvs\|update_ssdt\|update_ssdtx\|acpi_fill_lpit\|acpi_checksum\|acpi_add_table\|acpi_create_madt_lapic\|acpi_create_madt_ioapic\|acpi_create_madt_irqoverride\|acpi_create_madt_lapic_nmi\|acpi_create_madt\|acpi_create_madt_lapics\|acpi_create_madt_lapic_nmis\|acpi_create_madt_lx2apic\|acpi_create_srat_lapic\|acpi_create_srat_mem\|acpi_create_srat_gia_pci\|acpi_create_mcfg_mmconfig\|acpi_create_srat_lapics\|acpi_create_srat\|acpi_create_slit\|acpi_create_hmat_mpda\|acpi_create_hmat\|acpi_create_vfct\|acpi_create_ipmi\|acpi_create_ivrs\|acpi_create_crat\|acpi_create_hpet\|acpi_write_hpet\|generate_cpu_entries\|acpi_create_mcfg\|acpi_create_facs\|acpi_create_dbg2\|acpi_write_dbg2_pci_uart\|acpi_create_dmar\|acpi_create_dmar_drhd\|acpi_create_dmar_rmrr\|acpi_create_dmar_atsr\|acpi_create_dmar_rhsa\|acpi_create_dmar_andd\|acpi_create_dmar_satc\|cpi_dmar_\|acpi_create_\|acpi_write_hest\|acpi_soc_get_bert_region\|acpi_resume\|mainboard_suspend_resume\|acpi_find_wakeup_vector\|ACPI_S\|acpi_sleep_from_pm1\|acpi_get_preferred_pm_profile\|acpi_get_sleep_type\|acpi_get_gpe\|permanent_smi_handler\|acpi_s3_resume_allowed\|acpi_is_wakeup_s3\|acpi_align_current\|get_acpi_table_revision' -- src/) |grep "<" Change-Id: Icb90c70b0fb53175b9aaeabf067485a15fe71457 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-04sb/intel: Use `bool` for PCIe coalescing optionAngel Pons
Retype the `pcie_port_coalesce` devicetree options and related variables to better reflect their bivalue (boolean) nature. Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-01mb/roda/rk9/acpi: Replace Multiply(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Multiply (a, b)` with `a * b`. Change-Id: I8697f62cf5627ace8c4eac0caec7962171bb3541 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60567 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-31mb/roda/rk9/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Add (a, b, c)` with `c = a + b`. Change-Id: If2bb935570b1cb2b7a5e4168d594d735f343369b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/roda/rk886ex/acpi: Use Printf() for debug printsFelix Singer
Change-Id: I6091d81d49e5ae6bf30a03d2fb2d54f0ec6533d1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-29mb/roda/rk9/acpi: Use Printf() for debug printsFelix Singer
Change-Id: Ic461c109b3c6d08cc3cda60f23e673157cd782f9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-19cpu/intel/speedstep: Constify `get_cst_entries()`Angel Pons
Make the `get_cst_entries()` function provide a read-only pointer. Also, constify the actual data where applicable. Change-Id: Ib22b3e37b086a95af770465a45222e9b84202e54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-17drivers/generic/ioapic: Drop enable_virtual_wireKyösti Mälkki
All boards with DRIVERS_GENERIC_IOAPIC select it. Presumably the related configuration of routing IRQ0 when IOAPIC is enabled should be always done to provide i8259 legacy compatibility for payloads. Change-Id: Ie87816271fa63bba892c8615aa5e72ee68f6ba93 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-08ec/acpi: Remove empty "chip" driverNico Huber
There was no code attached to this driver and hence one couldn't hook it up to any device. Even if mentioned in the `devicetree.cb` it was still dead code. Change-Id: I12415ea9e0120b1d00524f8f39f9b2d02f46ba05 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-25mb/roda/rv11/acpi: Use lower case format for hex valuesFelix Singer
Change-Id: I3bea9e1f9cc25a4476ddbaa8bd8e434609eb28f7 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-25mb/roda/rv11/acpi: Use Printf ()Felix Singer
Change-Id: Iec6ec8bbf3cc5c9230ba6bcb0126ff6085f26464 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-07-28ec/roda/it8518/acpi: Don't hard-code GPE offsetNico Huber
The GPE offset of 16 is PCH specific. Built roda/rw11 with `BUILD_TIMELESS=1` and coreboot.rom remains the same. Change-Id: I4ec38fc28d2436f84a090bb4ab38f20612cfd795 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-26mb/*: Specify type of `VARIANT_DIR` onceAngel Pons
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `DEVICETREE` onceAngel Pons
Specify the type of the `DEVICETREE` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16arch/x86/ioapic: Drop irq_on_fsb as a configurable itemKyösti Mälkki
APIC Serial Bus pins were removed with ICH5 already, so a choice 'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG 0x3 is also not documented since ICH5. For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was wrong and ignored as BOOT_CONFIG register emulation was never implemented. For ICH4 and earlier, the choice to use FSB can be made based on the installed CPU model but this is now just hardwired to match P4 CPUs of aopen/dxplplusu. For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined and the only possible operation mode there is APIC Serial Bus, which requires no configuration. Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14mb/*/mptable.c: Use smp_write_pci_intsrc()Kyösti Mälkki
Split parameter '(devfn << 2) | intx' to 'devfn, intx'. Formatted with 'spatch --max-width 96' Change-Id: I17a6b3919b6e55aaa7ca2873ca713b36ebe7d3a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55285 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-14mb/*/mptable.c: Replace magic constantsKyösti Mälkki
Read I/O APIC ID and version from hardware registers. With coccinelle below, and minor fixups. @ r1 @ expression E1, E2, E3, E4; typedef u8; @@ -smp_write_ioapic(E1, E2, E3, E4); +u8 ioapic_id = smp_write_ioapic_from_hw(E1, E4); @ r2 @ expression E1, E2, E3, E4; @@ -mptable_add_isa_interrupts(E1, E2, E3, E4) +mptable_add_isa_interrupts(E1, E2, ioapic_id, E4) @ r3 @ expression E1, E2, E3, E4, E5, E6, E7; @@ -smp_write_pci_intsrc(E1, E2, E3, E4, E5, E6, E7) +smp_write_pci_intsrc(E1, E2, E3, E4, E5, ioapic_id, E7) @ r4 @ symbol mp_INT; expression E1, E3, E4, E5, E6, E7; @@ -smp_write_intsrc(E1, mp_INT, E3, E4, E5, E6, E7) +smp_write_intsrc(E1, mp_INT, E3, E4, E5, ioapic_id, E7) Change-Id: I20799f0c09cf0292661e1f3cb93373b2c68b7314 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-11cpu/x86/lapic: Replace LOCAL_APIC_ADDR referencesKyösti Mälkki
Note that there are assumptions about LAPIC MMIO location in both AMD and Intel sources in coreboot proper. Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mainboard: Use decimal for `device lapic 0x0 on`Angel Pons
Most boards use `device lapic 0 on` with zero written in decimal. For the sake of consistency, update the remaining boards to follow suit. Change-Id: I1d3b1ac107e33aae11189cdd5e719b8e48b10f08 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-13src: Match array format in function declarations and definitionsPatrick Georgi
gcc 11.1 complains when we're passing a type* into a function that was declared to get a type[], even if the ABI has identical parameter passing for both. To prepare for newer compilers, adapt to this added constraint. Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-04-21mb/**/early_init.c: Use get_int_option()Angel Pons
Change-Id: I460cad0cc671be830d0fa0f68a531acaea7effcc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-17mb: guard irq_tables for clang-formatPatrick Georgi
Some (notably older Intel) boards use a tabular description of irq routing that we want to keep pristine no matter what clang-format considers correct (as that's ugly). Change-Id: I259255a9f60208c659b658ecb81535e84a2aaa8c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-12sandybridge MRC boards: Drop channel disable masksAngel Pons
Platform code will overwrite these values anyway, so do not program them in mainboards. Change-Id: I7571d336a1402c6cfae5835a95dc706a28106271 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49751 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
Drop unused sandybridge.h includes to avoid build failures on Ironlake. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-01sb/intel/i82801ix: Factor out common `acpi_fill_madt`Angel Pons
It is the same for all three mainboards. Change-Id: Ic5786bcc29e2549d6fc935d60c699c1cab84b237 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50027 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-26mb/roda/rk9: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl are identical. Change-Id: I3cfa9d3a199a33ac8faddf4dbc1eed0df8703835 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-26mb/roda/rv11: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated build/dsdt.dsl files are identical. Change-Id: Id12c20dbe949c4badfe07578c6d202cd4cfb8191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46211 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-20ACPI GNVS: Drop APIC, factor out MPENKyösti Mälkki
APIC was not referenced anywhere in ASL. MPEN has references under boards: getac/p470, roda/rk9, roda/rk886ex. MPEN has reference also in Intel SpeedStep ASL. Replace static MPEN with detection of multiple CPUs installed. Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18mb/apple,lenovo,roda: Drop reference to OSYSKyösti Mälkki
It is claimed getac/p470 has this implemented and not as a TODO. Change-Id: Ifa9ec5bcb8b25b6334b589e4bc7bcb915e85e349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49349 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-18ACPI: Select ACPI_SOC_NVS only where suitableKyösti Mälkki
Having some symmetry with <soc/nvs.h> now allows to reduce the amount of gluelogic to determine the size and cbmc field of struct global_nvs. Since GNVS creation is now controlled by ACPI_SOC_NVS, drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne cannot have this selected until <soc/nvs.h> exists. Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
2021-01-10mb/x/acpi_tables: Rename to mainboard_fill_gnvs()Kyösti Mälkki
Rename acpi_create_gnvs() functions under mb/ to reflect their changed functionality. Remove now empty mb/acpi_tables.c files. Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06cpu/intel/model_206ax: Rename `cX_acpower` optionsAngel Pons
They aren't specific to AC power operation anymore. Also adapt autoport. Change-Id: Ib04d0a08674b7d2773d440d39bd6dfbd4359e0fb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49089 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06cpu/intel/model_206ax: Unify ACPI C-state optionsAngel Pons
All mainboards use the same values for AC and battery, even desktop boards without a battery. Use the AC values everywhere and drop the battery values. Subsequent commits will rename the AC power options accordingly, and will also clean up the corresponding acpigen code. This is intentional so as to ease reviewing the devicetree changes. Also update util/autoport accordingly. Change-Id: I581dc9b733d1f3006a4dc81d8a2fec255d2a0a0f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-23mb/**/cmos.layout: Indent everything with tabsAngel Pons
Time has shown that using spaces never converges into proper alignment. Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-23mb/**/cmos.layout: Remove crusty commentsAngel Pons
Most of these comments have been copy-pasted or serve no purpose other than to eventually turn into misleading info. While the description of the first 120 bits of CMOS could be useful, it should instead be added to the documentation for the CMOS option infrastructure, or /dev/null. Moreover, trim down newlines to no more than two consecutive newlines. Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-04mb/roda/rk886ex: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I2eea24db6cfd260e0f36243e90a5e01b360f23fb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-09-21mb/roda/rk886ex: Drop unneeded empty linesElyes HAOUAS
Change-Id: I229d3995983a05cdd7fef1609a65f31b9f8f2969 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-17nb/intel/sandybridge: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons
This allows us to drop some casts to uintptr_t around the tree. The MCHBAR32 macro still needs a cast to preserve reproducibility. Only the native raminit path needs the cast, the MRC path does not. Tested with BUILD_TIMELESS=1, these boards remain identical: - Lenovo ThinkPad X230 - Dell OptiPlex 9010 - Roda RW11 (with MRC raminit) Change-Id: I8ca1c35e2c1f1b4f0d83bd7bb080b8667dbe3cb3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45349 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/sandybridge: Drop invalid `DEFAULT_RCBABASE` macroAngel Pons
RCBA is located in the PCH. Replace all instances with the already-defined `DEFAULT_RCBA` macro, which is equivalent. Change-Id: I4b92737820b126d32da09b69e09675464aa22e31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45348 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-08nb/intel/sandybridge: Use an enum for `gpu_panel_port_select`Angel Pons
All boards currently have backlight on either LVDS or eDP. Change-Id: I878bc7f1ff75a2b82b9556e855aff1d4d03e0268 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-05src: Use space after 'if', 'for'Elyes HAOUAS
Change-Id: I5d3a5ede47aefc7cc2ee330f8a0bcded16138764 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44173 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASEAngel Pons
Make it default to 0x400, which is what the touched southbridges use. Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-15i945 boards: Factor out MAX_CPUSAngel Pons
At least one mobile 945 series northbridge supports 4 threads, because the dual-core Atom 330 CPU supports Hyper-threading. Therefore, we use that as the default for this chipset. Change-Id: I899ed1644d9b2da4fc72f09233a421200770110d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41845 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15gm45 boards: Factor out MAX_CPUSAngel Pons
The gm45 northbridge supports at most 4 threads. However, the only two mobile Core 2 Quad models are not BGA956, so account for that as well. Change-Id: Ie198ac4c366ec0bd53ddb337b6f9c03c331c73f5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-15sandybridge boards: Factor out MAX_CPUSAngel Pons
Also update autoport accordingly. Change-Id: I12481363cf0e7afc54e2e339504f70632e8d72e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41839 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10sb/intel/i82801ix: Select COMMON_FADTKyösti Mälkki
Change-Id: Iffdce450b1d4c9984ec5efe11eff62bf9184e314 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41922 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06arch/x86: Declare permanent_smi_handler()Kyösti Mälkki
Advertising SMI triggers in FADT is only valid if we exit with SMI installed. There has been some experiments to delay SMM installation to OS, yet there are new platforms that allow some configuration access only to be done inside SMM. Splitting static HAVE_SMI_HANDLER variable helps to manage cases where SMM might be both installed and cleared prior to entering payload. Change-Id: Iad92c4a180524e15199633693446a087787ad3a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-06mb/roda/rk9: Control SMI related FADT entriesKyösti Mälkki
When no SMI is installed, FADT should not advertise a trigger mechanism that does not respond. Change-Id: Iefa1e7d80367dbe380f69e768238b4124a45626f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41905 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove unused 'include <string.h>'Elyes HAOUAS
Unused includes found using following commande: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|atol\|strrchr\|skip_atoi\|STRINGIFY' -- src/) |grep -v vendorcode |grep '<' Change-Id: Ibaeec213b6019dfa9c45e3424b38af0e094d0c51 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-18mainboard/*/*/*.cb: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: Ia0dbf7b946d42bda11b904a9caff5a402b553b33 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13src: Remove unused '#include <stdint.h>'Elyes HAOUAS
unused includes of <stdin.h> found using following commande: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|uint8_t\|int16_t\|uint16_t\|int32_t\|uint32_t\|int64_t\| uint64_t\|intptr_t\|uintptr_t\|intmax_t\|uintmax_t\|s8\|u8\|s16\| u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|UINT8_MAX\|INT16_MIN\ |INT16_MAX\|UINT16_MAX\|INT32_MIN\|INT32_MAX\|UINT32_MAX\|INT64_MIN\ |INT64_MAX\|UINT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|UINTMAX_MAX' -- src/) |grep '<' |grep -v vendor |grep -vF '.h' Change-Id: Icb9b54c6abfb18d1e263665981968a4d7cccabeb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 17:02:48 +0000