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path: root/src/mainboard/prodrive/hermes/variants
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2021-08-06mb/prodrive/hermes: Update HDA codec subvendor IDAngel Pons
Tested on prodrive/hermes. Change-Id: I72be8bde59d9eb0c1eff8c65dc734c6805732e09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56086 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: <wouter.eckhardt@prodrive-technologies.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16mb/prodrive/hermes: Use serial numbers from BMCAngel Pons
The BMC EEPROM layout has been updated to contain system and mainboard serial numbers. Use these values in SMBIOS Type 1 and Type 2 tables. Change-Id: I55b51a856b4ad28fd56b02015b2e1d49cd629735 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55275 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/prodrive/hermes: Rename EEPROM access functionsAngel Pons
Change-Id: I84b9ef080f1ac91ea6f7273457b882677abf70d3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52885 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28mb/prodrive/hermes: Simplify `read_write_config` signatureAngel Pons
The `write_offset` parameter is always zero. Remove it. Change-Id: Ib63cb25904ad6c1c7424a9c01d8bf1e84c08453b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52884 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28mb/prodrive/hermes: Drop Vref configuration for older boardsPatrick Rudolph
Drop Vref verbs from the baseboard table as it's not required for Rev. 3 and earlier. Change-Id: I41c207f97dad6c9107c1999eb46d2d6304a6c217 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-04-06mb/prodrive/hermes: Properly pack EEPROM structuresAngel Pons
To pack a struct, the `__packed` attribute must come after the `struct` keyword. Moreover, unions cannot be packed (structs inside unions can, though). Correct uses of `__packed` so that EEPROM structs get packed. Change-Id: I39d2c9ebc370605d5623b134189aa95a074ec7c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: <wouter.eckhardt@prodrive-technologies.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-18mb/prodrive/hermes: Disable HDA codec Port E by default on R04+Angel Pons
If the board settings aren't valid, Port E uses the settings for earlier board revisions, which is undesired. Disable Port E by default on R04+. Change-Id: I03bd50b915a2120283b77179debaa735bb7ef027 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51529 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-24mb/prodrive/hermes/hda_verb: Update verb table for latest board revisionPatrick Rudolph
Use different verb tables depending on board revision. For board revision R03 and older use the existing verb tables. For revisions newer than R03 use the new verb tables and also apply the dynamic audio configuration recently added. Also do the following: * Use correct NID port mapping * Fix verb count in ALC888 header * Fix NID in Intel codec verbs Change-Id: I24ea9149eb2cddb815ff82744a351c926a94aaef Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-19mb/prodrive/hermes/eeprom: Add function to read HSI from EEPROMPatrick Rudolph
Will be used to determine the board revision. Change-Id: I41e4c6ad83e23c9d79e6abab3f38ad46bd3bec06 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50788 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19mb/prodrive/eeprom: Add BMC settingsPatrick Rudolph
Add settings describing the BMC. Will be used by the following patch to read the board revision. Change-Id: If464138fc1bdf02a45a21f638b179048d68d974d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50787 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17mb/prodrive/hermes: Write board layoutPatrick Rudolph
The I2C EEPROM on SMBUS needs to be updated with the current board layout, so that the BMC knows the actual configuration. Collect all needed information and update the EEPROM if something changed. Every byte written add a delay of 5 msec. Change-Id: Ic8485e6c700eede75b1e829238ee70da65118ace Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-02-16mb/prodrive/hermes: Improve board config EEPROM handlingAngel Pons
* Check and print errors returned from reading from I2C * Rework offset calculation by using more macros * Get rid of stage-specific preprocessor code * Define the EEPROM layout as struct * Make use of the defined EEPROM layout to calculate offsets * Read the UPD to disable VT-d from EEPROM Change-Id: Iad77811318c7dfd3a3a4f8d523cfa0f457f168b6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48808 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-04mb/prodrive/hermes: Define board settings in EEPROMAngel Pons
Hermes has an EEPROM with firmware configuration data. Add definitions to read and verify the `board settings` from the EEPROM. Subsequent commits will hook up these EEPROM settings. Change-Id: Id86632192ae53fd6b0e4df5b26b5a0a81e972818 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-22mb/prodrive/hermes: Fix 30 second boot delayPatrick Rudolph
The PMC doesn't response any more due to invalid CNVi GPIO configuration. This caused a 30 second boot delay in FSP-S. Use the same values as FSP-S does. Always disable external I2S BT audio and use NF3 for pad GPP_D5 and GPP_D6. Tested on Prodrive hermes: No boot delay can be observed any more. Change-Id: I6f4a954786ec21512b0dce908d333952e96de048 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49678 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-20mb/prodrive/hermes: do UART pad configuration at board-levelMichael Niewöhner
UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Change-Id: I5b99a66fb64683f3647ebff3ab01ceb52058f79c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-24mb/prodrive/hermes: Drop EEPROM address function parametersAngel Pons
Only one EEPROM is used to store the board settings, and its I2C address is constant. Thus, there's no need to pass its address as a parameter. In addition, reduce the scope of the `I2C_ADDR_EEPROM` definition, since using it outside of eeprom.c would bypass the API's abstraction layer. Change-Id: I958304e6ed6df05af923139d44ff4fd1de204738 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-24mb/prodrive/hermes: Use already-defined SMBus macrosAngel Pons
Drop chipset register definitions in mainboard code in favor of existing definitions in a header. These definitions are not mainboard-specific. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I29d6f35ec27bff43cf52ae697e905b6a7b48a8d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-21mb/prodrive/hermes: Update USB 2.0 settingsAngel Pons
Test results show that USB signals look better with these settings. Yes, there's a macro in the devicetree now. All ports use the same settings except for the overcurrent pin, so this avoids redundancy. Change-Id: Ib0dafab88d8dcc05388b724f6a7183c13ac64934 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48694 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14mb/prodrive/hermes: Update PCIe slots in devicetreePatrick Rudolph
* Drop PcieRpSlotImplemented on internal slots * Add PCIe port 15 that connected to CNVi/M.2 E Change-Id: Iaa05affa760b447fc1725e674b12366684a63720 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-05mb/prodrive/hermes: Generalise `check_signature` functionAngel Pons
Allow to specify which signature is to be checked. Change-Id: Ica874b1c4283fdb8dbd702c34ccb3315a2cf160d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-11-30mb/prodrive/hermes: Encapsulate GPIO setupAngel Pons
Having variants' gpio.c call the `gpio_configure_pads` function results in an API that does not need to pass data around, which is much simpler. Change-Id: I1064dc6258561bcf83f0e249d65b823368cf0d31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-30mb/prodrive/hermes: Use C-style commentsAngel Pons
Most of the existing comments are C-style already. Change-Id: I9ca4779f5b0560320e9bce4f33e54766522689f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-11-09soc/intel/*/chip: Remove unused devicetree entryPatrick Rudolph
InternalGfx isn't used so drop it. Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-04mb/prodrive/hermes: Set tcc offset to 1Patrick Rudolph
Prevent early throttling when the ambient temperature is high. Change-Id: Ie6881c9c0942aae3e43509170352271a74244d42 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02mb, soc/intel: Reorganize CNVi device entries in devicetreeFurquan Shaikh
This change reorganizes the CNVi device entries in mainboard devicetree/overridetree and SoC chipset tree to make it consistent with how other SoC internal PCI devices are represented i.e. without a chip driver around the SoC controller itself. Before: chip drivers/wifi/generic register "wake" = "..." device pci xx.y on end end After: device pci xx.y on chip drivers/wifi/generic register "wake" = "..." device generic 0 on end end end Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-26mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-06mb/*: devicetree: drop now unneeded USBx_PORT_EMPTYMichael Niewöhner
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset devicetree settings default to 0 and the OC pin now only gets set when the USB port is enabled (see CB:45112). Thus, drop the setting from all devicetrees. Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-08-23soc/intel/cnl: Configure FSP option PcieRpSlotImplementedNico Huber
Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-08-23mb/prodrive/hermes: Add root port numbers to commentsFelix Singer
Change-Id: I06bb0493999f1f6954854f872cda46dc38930370 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-08-18mb/prodrive/hermes: Enable LPSS ACPI driverPatrick Rudolph
Enable the introduced LPSS ACPI uart driver. Tested on Hermes using Linux 5.6: The UART2 appears as /dev/ttyS2. Change-Id: Ic15be4a807012216e52c848120de7e39522f57b7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-12mb/prodrive/hermes: Add multifunction device for UART 2Christian Walter
On CNP-H, only four I2C controllers are available, so PCI devices 19.0 and 19.1 are missing. However, PCI device 19.2 still exists as UART 2. That function 0 is missing means UART 2 can only be used in ACPI mode. Both devices need to be marked as hidden on the devicetree so that the allocator takes UART 2 into account. Change-Id: Ie77198cc0327414b9f88cf15ba4efaddb4f5cca4 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-04mb/**/{devicetree,overridetree}.cb: Indent with tabsAngel Pons
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-28mb/prodrive/hermes: Relocate device enable optionsFelix Singer
Since there aren't any other variants, we can move things between the devicetree and the overridetree. Built with BUILD_TIMELESS=1, resulting coreboot.rom does not change. Change-Id: I54aac67237a3850dbf11f58bd41aba87505214f3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43927 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23mb/prodrive/hermes: Update VBT fileChristian Walter
Update .vbt file to support two DP outputs. Change-Id: Ifd4163aafe4ef3070d04a72a4699303af72c5102 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-01mb/prodrive/hermes/variants/baseboard: configure sataHotplugJonas Loeffelholz
Configure sataHotPlug in devicetree, as this functionality is now available for this soc. Change-Id: If462e33d1bbef8036d598970fb2774d0fda1fbb1 Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42804 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30src: Remove whitespaces before tabsElyes HAOUAS
Change-Id: I73695152ec8d8ab2dabf8421ef2405f70de0f4ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42795 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-26mainboard/prodrive/hermes: Enable EIST in DeviceTreeChristian Walter
Enable EIST option in the devicetree in order to make Windows aware of using Intel CPU Turbo Technology. Change-Id: Ied3d7e934fcab2d5d491573245d68d392df5ba34 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-06mb/prodrive/hermes: Add new mainboard portChristian Walter
This patch adds support for the Prodrive Hermes mainboard. Tested with CoffeeLakeFspBinPkg FSP 7.0.68.41. Untested: * CNVi * Intel Graphics Tested: * CPU Intel Xeon E2288G * CPU Intel Core i3-9100F * CPU Intel Core i7 9700KF * CPU Intel Core i7 9700E * CPU Intel Core i7 9700F * CPU Intel Core i5 9600K * CPU Intel Pentium Gold G5400 * PCIe Link Width x8 on Slot6 by changing PCIe mux * All four DDR4 slots in different configurations * USB2.0 HDR1 * USB2.0 HDR2 * USB3.0 HDR * Slot1 * Slot2 * Slot3 * Slot4 * Slot6 * M2.M NVMEe * Ethernet PHYs 0-4 * Aspeed BMC PCIe * Aspeed BMC USB * Aspeed Graphics init * USB3 backplane all working * I801 SMBUS Not Working: * Intel HDA Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862 Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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