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2019-11-29mb/lenovo/t400/Makefile: Build gpio w/o subdir makefilesPeter Lemenkov
Change-Id: Ia2e889fe72d746b71d92026e358c7471f56b381f Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-29mb/lenovo/t400/Kconfig: Remove default data.vbt pathPeter Lemenkov
Change-Id: Ib720d9ca57cf1ce640f168cd6aab654b53e92b82 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-22mb/lenovo/t410: Fix I2C SPD addressPatrick Rudolph
Use correct address for second DIMM. Tested on Lenovo T410: * Both DIMMs are found and are usable Change-Id: I8bace47f04a0e185c2901695879d4d4e12d4ce6a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37105 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22mb/lenovo/{x201,x60}/smihandler: Use mdelay instead of udelay for large valuesPeter Lemenkov
Change-Id: I7d20a850f8c2a1fcdee358c9e73d4c04eb3d7de8 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37006 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20mb/lenovo/x201: Remove unnecessary GPIO settingsArthur Heymans
GPIO49 is strapped high, so setting it low likely increases power usage. GPIO53 is hooked to a testpad so there is no reason to set it here. Change-Id: I00fb38c90417b673c2b36191c20279474eb0dc21 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18mb/lenovo/s230u: Don't write BUC and beyondNico Huber
The BUC register is actually only 8 bits wide and setting bit 5 (disabling GbE) is already done by generic code. Change-Id: I4b8e14606c319e8bfc48d6757087f28af1bd5dfb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18mb/{gigabyte,lenovo}: Remove spurious setting of ETR3 bit 16Nico Huber
This bit is used to indicate xHCI routing across reboots. If anything, coreboot should act on it, not set it during boot. ASL code would be supposed to set it. Change-Id: Id14647ac4e591cfa042ca8aad6dfc6ccda35c74a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-18nb/intel/sandybridge: Set up console in bootblockArthur Heymans
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
There is some overlap between romstage and bootblock. LPC setup and BAR initialization is now done twice. The rationale is that the romstage should not depend too much on the bootblock, since it can reside in a RO fmap region. Enabling the console will be done in a followup patch. Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18sb/intel/bd82x6x: Make the pch_enable_lpc hook optionalArthur Heymans
This also changes the name to mainboard_pch_lpc_setup to better reflect that it is an optional mainboard hook. This adds an empty weakly linked default. The rationale behind this change is that without an implementation of the hook some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: Ie8e6056b4c4aed3739d2d12b4224de36fe217189 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18nb/intel/sandybridge: Make the mainboard_rcba_config hook optionalArthur Heymans
This also changes the name to mainboard_late_rcba_config to better reflect what it does. This adds an empty weakly linked default. The rationale behind this change is that without an implementation of the hook some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-18nb/intel/sandybridge: Make the mainboard_early_init hook optionalArthur Heymans
This adds an empty weakly linked default. The rationale behind this change is that without the callback some features might not work but that the result is likely still able to boot, so it can be made optional. Change-Id: I62c8010aa81fc45d208e9293feb2f45b45f34a82 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-17mb/{i945,ich7}: Remove redundant write on V0CTLElyes HAOUAS
RCBA32(V0CTL)= 0x80000001 already done inhere i945/early_init.c Change-Id: Ia775f4e6158a217b48629d289845537e7ccf5e79 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-15nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15nb/intel/i945: Initialize console in bootblockArthur Heymans
Change-Id: Ic6ea158714998195614a63ee46a057f405de5616 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-15nb/intel/i945: Move boilerplate romstage to a common locationArthur Heymans
This adds callbacks for mainboard specific init. Change-Id: Ib67bc492a7b7f02f9b57a52fd6730e16501b436e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36787 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15nb/intel/x4x: Move boilerplate romstage to a common locationArthur Heymans
This adds 3 mb romstage callbacks: - void mb_lpc_setup(void) to be used to set up the superio - void mb_get_spd_map(u8 spd_map[4]) to get I2C addresses of SPDs - (optional)mb_pre_raminit_setup(int s3_resume) to set up mainboard specific things before the raminit. Change-Id: Ic3b838856b3076ed05eeeea7c0656c2078462272 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36758 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14mb/*/*(ich7/x4x): Use common early southbridge initArthur Heymans
One functional change is that southbridge GPIO init is moved after console init. Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36757 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-14sb/intel/i82801gx: Add common early codeArthur Heymans
Remove some of the code duplication on i82801gx. x4x boards are left untouched for now since that northbridge also supports i82801jx. The order of some things has changed: - on i945 early_ich7_init is now done before the raminit - enabling the IOAPIC is done before the raminit Change-Id: Ie39549938891e17667a8819b49a78b9c71c8ec9e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36754 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12sb/intel/i82801gx: Add common LPC decode codeArthur Heymans
Generic LPC decode ranges can now be set from the devicetree. Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-12ec/lenovo/h8: Make dock init in ramstage fully mainboard-specificBill XIE
Discussed in CB:36093, in the past many lenovo boards need to declare an empty h8_mainboard_init_dock() to satisfy h8.c. Now the confusing H8_DOCK_EARLY_INIT might be retired, and if a mainboard needs dock init (done with h8_mainboard_init_dock() in the past) in ramstage, (discussed in CB:4294 where H8_DOCK_EARLY_INIT is introduced) it can just do it in its own chip_ops.enable_dev function. Tested on X200. Testing on other affected targets may be necessary. Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-11src/mb: Remove redundant message befor 'system_reset()'Elyes HAOUAS
Change-Id: Id5a6b7c731b65aafbb88a7c52a1f434dbab41f4a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36694 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-11mb/{x4x}: Remove unused 'include <northbridge/intel/x4x/iomap.h>'Elyes HAOUAS
Change-Id: I82f1d4325ea87585137fa81567aa82b80454c704 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-08arch/x86: Drop some __SMM__ guardsKyösti Mälkki
Change-Id: I64063bbae5b44f1f24566609a7f770c6d5f69fac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-04sb/intel/lynxpoint: Use sb/intel/common/platform.aslArthur Heymans
Change-Id: I86260a374a3f60f16dc73573e7989f0a4ffec818 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04mb/*/*{i82801gx}: Use sb/intel/common/acpi/platform.aslArthur Heymans
Change-Id: Ifc0799d26394a525d764fb4ffc096b48060ee22f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-04mb/*/*{bd82x6x/ibexpreak}: Use sb/intel/common/acpi/platform.aslArthur Heymans
Change-Id: I36095422559e6c160aa57f8907944faa4c192dee Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-04mb/lenovo/{x200,t400}: Add VBOOT supportArthur Heymans
Tested on thinkpad X200 with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW selected, the RW_A slot is properly selected unless the FN button is pressed. 600+ms are spend waiting for the EC to be ready. Change-Id: I689fe310e5b828f2e68fcbe9afd582f35738ed1d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35998 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-03mb/intel/{i82801gx,x4x}: Don't select ASPM optionsArthur Heymans
These are likely not properly set up and L1 is not even supported on the desktop variant of the southbridge. This fixes observed instability on some PCIe GPUs. Change-Id: I70d3536984342614a6ef04a45bc6591e358e3abe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36576 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30mainboard: Add Lenovo ThinkPad T440pIru Cai
The code is based on autoport. This port is tested on a T440p without a dGPU and can boot Arch Linux from SATA disk with SeaBIOS payload. The tested components and issues are in the documentation. Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34359 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-28nb/intel/gm45: Add C_ENVIRONMENT_BOOTBLOCK supportArthur Heymans
The i82801ix_early_init is now called both in the bootblock and romstage. The rationale behind setting this up twice is to ensure bootblock-romstage compatibility in the future if for instance VBOOT is used. This moves the console init to the bootblock. The romstage now runs uncached. Adding a prog_run hooks to set up an MTRR to cache the romstage will be done in a followup patch. The default size of 64KiB is not modified for the bootblock as trying to fit both EHCI and SPI flash debugging needs a more space and 64KiB is the next power of 2 size that fits it. TESTED on Thinkpad X200. Change-Id: I8f59736cb54377973215f35e35d2cbcd1d82c374 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-28mb/lenovo/x200: Correct device tree override logicBill XIE
If a device node should be enabled on some variants, but disabled on others, it had better be declared as disabled (rather than absent) in base device tree (rather than override tree for the variant disabling it), and enabled in override tree for the variant needing it, so that it does not need to be declared once more when adding another variant with such node disabled. Change-Id: I4b28360905ae38149ace9ac5d21cd6d5045b7584 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-27src/mainboard: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I46d131f76ec930d2ef0f74e6eaabae067df10754 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-27mb/(ich7): Use macro instead of magic numberElyes HAOUAS
Change-Id: Ida291ed9f3a509e9b96a5c254433db6f8028bfb2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-25mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant boardMaccraft
- This port should be Reclaim Your Freedom compliant (not certified yet). - Untested on boards with external Radeon graphics adapter. - Some columns on the left-most side of display are completely black on 1400x1050 IPS display[1]. Display works fine on Linux. I don't know why it appears like that. So far it has been observed only with native graphics initialization. - Only GRUB2 and SeaBIOS payloads tested for now. - 2504 docking station USB doesn't work under Linux. Can detect pendrive in GRUB2 payload. - Sometimes it takes 20s of "pretending it's powered off" to run coreboot code. Issue is payload agnostic. Probably caused by missing one capacitor on my unit. [1] https://imgur.com/a/0wpMGsm Change-Id: Ibd9208a5eafd228f8eedbc8fb4f4eb9ed1932a14 Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-25src/mainboard: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: I50cafce0aaf465ee95562ccff6c8f63fb22096c0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-25mb/lenovo/x201/smihandler: Remove mainboard_io_trap_handler functionPeter Lemenkov
An io_trap_handler on this board is unused in SMM. Change-Id: Ie922f8f1a10495ae887221735c96807261508041 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25mb/*/*/smihandler: Remove bogus mainboard_io_trap_handlerPeter Lemenkov
These mainboard_io_trap_handler functions do nothing compared to a weak mainboard_io_trap_handler in src/cpu/x86/smm/. Change-Id: I73ebcc6c3f604a075a946503d51881ccc6820dac Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25mb/lenovo/{t60,x201,x60}/smihandler: Remove SMM reinitializationPeter Lemenkov
Remove SMM reinitialization since it's already done in src/ec/lenovo/h8. Untested on a real hardware. See also commit 8953d4a1 with Change-Id I33fd829a7e34aefa8f76ca6020cc8e802f7aab17 ("mb/lenovo/*/smihandler: Get rid of mainboard_io_trap_handler"). Change-Id: Icc582527db15f3a31cdee8948bc5a190240fdc84 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-25mb/*/*/smihandler: Remove bogus SMM initPeter Lemenkov
I does nothing on these boards. It's just a call a local noop function which only prints a debug-level message. Change-Id: Id3fb2e9074db72d9025b95f7d4918417dd488b9e Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-24mb/lenovo/t410/board_info: Add release year fieldPeter Lemenkov
Change-Id: I24b92977ab1259159d2d21dfb355ea5d53bfb141 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36204 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-23mb/{lenovo/x201,packardbell/ms2290}/acpi: Merge common platform ASL codeVladimir Serbinenko
This code in reality just describes the southbridge features, don't put a copy in every mainboard. This commit follows up on commit e288758b with Change-Id I8cf3019a36b1ae6a17d502e7508f36ea9fa62830 ("bd82x6x: Merge common platform ASL code"). Change-Id: Ic5260461165b794a13efd2c6d968c953f60dd253 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36229 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-23mb/lenovo/t410/dock: Remove unused includesPeter Lemenkov
Change-Id: Ia1df27b6d946d8ef5252cc35bb4fcaaabedbe2c7 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-22mb/lenovo/t410/early_init: Remove unused include delay.hPeter Lemenkov
Change-Id: I22b78a976c6ea43caa326e990a3c3333fef99d61 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-22mb/lenovo/t410/gpio: Use static for const structuresPeter Lemenkov
Autoport generates these structures as static so let's make it consistent. This commit follows up on commit 6752b615 with Change-Id I4e07bd755ca4a65b76c69625d235a879fe7b43cb ("mb/*/*/gpio: Use static for const structures"). Change-Id: Iaf9c796ca41218a9460ca6e0f64ef3e21a2ed2ff Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-22mb/lenovo/t410/Makefile: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. This commit follows up on commit 9265f89f with Change-Id I10b4300ddd18b1673c404b45fd9642488ab3186c ("arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-class"). Change-Id: If0e2a57283689a3cd1b97ee6e3c616fdefc0a028 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-22mb/lenovo/*/acpi: Remove unused include smi.hPeter Lemenkov
Change-Id: I995ef40a04c7705def95c2d5950be940503ee5ab Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-21src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'Elyes HAOUAS
Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-20mb/lenovo/x200: Add ThinkPad X301 as a variantBill XIE
It is similar to X200s, with U-series CPU, slightly different gpio setup, no docking support, and no superio chip. Tested: - CPU Core 2 Duo U9400 - Slotted DIMM 4GiB*2 from samsung - Camera - pci-e slots - sata and usb2 - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from Linux payload (Heads) and Seabios. TODO: repurpose and/or rename flag H8_DOCK_EARLY_INIT (introduced in CB:4294 ) for h8-using devices without a dock. Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-19mb/lenovo/x201/dock.c: Use common southbridge gpio codeArthur Heymans
Change-Id: I885f57f68e30c2a641e84655dc7ea9da141fb83f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36128 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-19mb/lenovo/x200/dock.c: Use common southbridge gpio codeArthur Heymans
Change-Id: I5b527a23aa0b0038936bb4b77176331fdfd6d914 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-17mb/lenovo/x201: Add VBOOT supportArthur Heymans
Tested with CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW to switch between RW_A and recovery, which works quite well as a developer mode to test RW_A with the COREBOOT slot as a fallback. Change-Id: I9d524988e991457032f63a947606d1b3581de5e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-16sb/intel/bd82x6x/lpc: Set up default LPC decode rangesArthur Heymans
This sets up some common default LPC decode ranges in a common place. This may set up more decode ranges than needed but that typically does not hurt. Mainboards needing additional ranges can do so in the mainboard pch_enable_lpc hook. Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-16mb/lenovo/x201: Fix Linux shutting down on s3 resumeArthur Heymans
On some configuration coreboot boots too fast and the EC reports the max temperature, resulting in Linux shutting down immediately. Change-Id: I610c7c9fbf2130566d3c2c758f1796314d3a0973 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2019-10-16src/mb: Remove unused 'include <arch/io.h>'Elyes HAOUAS
Change-Id: I03461cb9e87b4ddd599e5601637a75b012694e7c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-15mainboard/lenovo/t410: Add new portNicolas Reinecke
The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.12.1 * Booting from EHCI * Running GNU/Linux 5.0.0 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Wifi * Sound * USB * Ethernet * S3 resume * VBOOT Testing in progress. Untested: * VGA * Displayport * Docking station Bugs: * AC adapter can't be read from ACPI * TPM not working with VBOOT and C_ENV BB Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/11791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-14sb/intel/i82801ix: Add common code to set up LPC IO decode rangesArthur Heymans
This does the following: - Add gen[1-4]_dec options to the devicetree to set up generic LPC decode ranges in the southbridge code. - Move setting up some default decode ranges to a common place. If somehow a board needs to override this behavior it can happen in the mb_setup_superio() hook (that will be renamed when moving to C_ENVIRONMENT_BOOTBLOCK). Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-13nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
A few notable changes: - Microcode init is done in assembly during the CAR init. - The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size against which the romstage stack guards protected. - The romstage mainboard_lpc_init() hook is removed in favor of the existing bootblock_mainboard_early_init(). Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-11sb/intel/i82801gx: Move CIR init to a common placeArthur Heymans
Some boards with the G41 chipset lacked programming CIR, so this change add that to those boards too. Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-09mb/[google/intel/lenovo]/*: fix posix shell bug with SPD filesGreg V
FreeBSD's sh (basic posix shell) did not interpret the '\%o' escape in the same way bash/zsh do. As a result, the decoded files ended up with ASCII numbers instead of the decoded binary data. Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68 Signed-off-by: Greg V <greg@unrelenting.technology> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-08mb/lenovo/t60: Switch to override treePeter Lemenkov
Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34779 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-08mb/lenovo/{t60,z61t}: Convert to variant boardPeter Lemenkov
Change-Id: I0a3076780ac5cf183235f06e4c56d0707bf5e6ca Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-06mb/{lenovo/x201,packardbell/ms2290}: Remove unused ACPI symbolsArthur Heymans
Change-Id: I3a3174cf20cea60d8b2c4d0311a48ce9ffe1a8a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-06nb/intel/nehalem: Move PCH init to sb/intel/ibexpeakArthur Heymans
This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC generic IO decode up in romstage based on devicetree settings - Remove the ramstage LPC generic IO decode from ramstage as this is now done in romstage.c - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock. Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-06nb/intel/nehalem: Move romstage boilerplate to a common locationArthur Heymans
Move the mainboard_romstage_entry to a common location and provide mainboard specific callbacks. Change-Id: Ia827053617cead5d2cf8e9f06cb68c2cbb668ca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-06sb/intel/ibexpeak: Don't clear PMBASE regs in romstageArthur Heymans
X201 boots fine without it. Change-Id: I20a8e598b07bf0a059dcb47651d1a26456863673 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35769 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06sb/intel/ibexpeak: Implement USB current settingsArthur Heymans
This is based on the sandybridge settings. The current lookup table comes from the x201 vendor lookup table. Tested: USB mouse and webcam still work and current registers are the same as before. USB IR are not but the code follows EDS instead of the register replay. Change-Id: Icea9673623a62e7039d5700100a2ee238478abd1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35762 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06intel/ibexpeak boards: Remove undocumented reset defaults from RCBA replayArthur Heymans
The values read back in those ranges are identical before and after this change and the Lenovo Thinkpad X201 still boots fine. Change-Id: I406510e0573ac97003da7d97181abdfbfd2a872f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35760 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06intel/ibexpeak boards: Remove handled RCBA entries from replayArthur Heymans
The RCBA registers 0x3400-0x3500 are all handled elsewhere in the code, so no need to have a 'replay' of those. The remainder now consist of USB setup and undocumented bits that should likely not be touched at all. Change-Id: I69fc8a5e16f7cf0e1068d0d2ed678a6c2f6e70a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-10-06sb/intel/ibexpeak: Implement PCH function disable in chip_opsArthur Heymans
This does the following: - implement a PCH disable function that will be called by the PCI drivers as part of their chip_ops - removes the iobp_x calls as those don't exist on ibexpeak - complete the devicetree with to be disabled PCI devices for the chip_ops to be called - Clean up some code copied from bd82x6x Change-Id: I78d25ffe9af482c77d397a9fdb4f0127e40baddc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-10-06nb/intel/nehalem: Disable PEG and IGD based on devicetreeArthur Heymans
Tested on Thinkpad X201: PEG device hidden. Change-Id: Ib378458a55e18cc02fc49b3e6d6939d31dd4aa65 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35744 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-06sb/intel/ibexpeak: Add CIR initializationArthur Heymans
This properly sets up the chipset initialization registers, instead of replaying an RCBA dump. The information is taken from the EDS and from the thinkpad x201 vendor BIOS disassembly and from an HP UEFI. TESTED on Thinkpad X201. Seems stable at booting, rebooting and resume from S3. Change-Id: I21c2beaf70da27dbe6a56e2612df2c257c05fc62 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-28mb/lenovo/x131e: enable mSATA slotJames Ye
Per google/stout. Tested with SanDisk SSD U110. Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2 Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2019-09-27mb/lenovo/x131e: correct USB port configJames Ye
Based on schematic and register dumps. Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc Signed-off-by: James Ye <jye836@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-09-17mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controllerBill XIE
Some T430s variants have a Thunderbolt controller wired to PCIe port The controller hotplugs itself to the chipset when a downstream device is hotplugged into it, so the hotplug capability should be enabled on PCIe port #5. TODO: find the correct gpio pin to detect the Thunderbolt controller at runtime. There are 3 variants of mainboard for Thinkpad T430s: Basic type (Wistron LSN-4 11263-1), Boards with an additional discreet GPU, Boards with an additional TB controller (Wistron LSN-4 11271-1), each of which has a different schematic. The gpio27 on the last type is set as set as GPIO-INPUT, compared with GPIO-OUTPUT-HIGH on the basic type boards. Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-17cpu/intel/model_2065x: Don't redefine CPU_ADDR_BITSArthur Heymans
This Kconfig symbol is set at a default of 36 in cpu/x86 and is now only used in the romcc bootblock to set up caching to upgrade the microcode. It's not mainboard specific. Change-Id: I29d3a8308025e586a823603f8d6edafd30cb9d95 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35436 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-17nb/nehalem: Move MMCONF_BASE_ADDRESS to a common placeArthur Heymans
Change-Id: I872959c4a38e28c29220b81c9fe029e7fc553ccf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35435 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15mb/*/{x201,ms2290}/mainboard.c: Remove superfluous ramstage codeArthur Heymans
Change-Id: I0270c50dea2a2ce6c8e6114ed708f06be9d33c0e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-28lenovo/t431s,w530: Add DRIVERS_RICOH_RCE822Kyösti Mälkki
Device is present in devicetree but not included in the build. Change-Id: I8555d94902e94c623d8fbe6f1a4ffe7637988530 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20mb,autoport: Fix GCC 9 Port_List build errorJacob Garber
Port_List is an array of 8 elements, and GCC 9 is warning that there are no 'others' when all 8 elements are explicitly initialized, which is causing the build to fail. Remove the 'others => Disabled' clause to silence this. Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-18mainboards: Remove floating __PRE_RAM__ commentsKyösti Mälkki
Change-Id: I110e54175a81b6a651213e0f18ddc1e3e71160cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-07-19sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supportedPatrick Rudolph
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-18mb/*/*/gpio: Use static for const structuresPeter Lemenkov
Autoport generates these structures as static so let's make it consistent. See also commit 128205fd with Change-Id I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7 ("autoport/bd82x6x.go: Improve gpio.c generation"). Change-Id: I4e07bd755ca4a65b76c69625d235a879fe7b43cb Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33524 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13intel/i945: Fix udelay() prototypesKyösti Mälkki
Change-Id: Ia157c6417bdd9c4ffbdf07683c51d0680e9356c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08sb/intel/ibexpeak: Use common final SPI OPs setupArthur Heymans
This also removes the relevant RCBA replays the mainboard dir. Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Thomas Heijligen <src@posteo.de>
2019-07-07mb/lenovo/g505s: Disable SeaBIOS options unsupported by hardwareMike Banon
G505S doesn't have any SAS or NVMe controllers and couldn't have a TPM, so it makes sense to disable the related SeaBIOS options for this board. This reduces the size of compiled SeaBIOS by 129344-110048=19296 bytes. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ib0183b7786ecd77bb0df923bc84908275f2fe14c Reviewed-on: https://review.coreboot.org/c/coreboot/+/33870 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07mb/lenovo/t60: Align ACPI C-state across the similar boardsPeter Lemenkov
We have 3 similar Lenovo mainboards - x60 (oldest), t60, and z61t (most recent addition). The only one with two consequent 2s as the C-types is t60: static acpi_cstate_t cst_entries[] = { { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } }, { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, }; It seems that 3 could be a better choice for the last line here. UNTESTED on a real hardware. Change-Id: I090e82d5f4ae25c768ff45a01a8dd76ff8a96a90 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-25intel/945 boards: Use smp_write_pci_intsrc()Kyösti Mälkki
Radically reduces line lengths and splits '(bus<<2) | INT' to separate parameters. Change-Id: I0cfd714da3d2773affdb34d1dab2ac32879e2cfd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30740 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-25mb/lenovo/z61t: Remove `fn_ctrl_swap` optionPeter Lemenkov
It seems that the EC on t60/x60/z61t doesn't support it. This wasn't even introduced in z61t so let's remove the remaining bits. This commit follows up on commit a5fcc2e4 with Change-Id Id2964002406a5fcf992f0ffc3627e3f66a2bb13f ("mb/lenovo/x60/t60: Remove `fn_ctrl_swap` option"). Tested on a real hardware. Change-Id: Ifd5e7823af305cc4a0194ee2097a749e43680c55 Signed-off-by: Nico Huber <nico.huber@secunet.com> Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Andrey Korolyov <andrey@xdel.ru>
2019-06-21mb/lenovo/x201: Remove duplicated includePeter Lemenkov
Change-Id: I0917f11091b8c93c21c0e25690440b7dd0e9c8ba Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-06-21sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetreeArthur Heymans
Set up generic decode ranges based on the devicetree settings. Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-21mb/lenovo/x201/smihandler.c: Remove useless smihandler codeArthur Heymans
This code to handle the brightness from SMM is copied from the Lenovo Thinkpad X60 code, but does not work on later generation. The PCI device it tries to address does not even exist on those devices. Change-Id: I0c25c3e5bec651b27158a84cc91289639a04ceb6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-21mb/*/{x201,packardbell}: Remove unused C-state generation functionsArthur Heymans
Those are copied from Lenovo X60 code, but are unused. NOTE: No ACPI C-state are generated on this platform but Linux has a separate driver for that. Change-Id: Ie9b49f5451d8cde9c36672cac1f0f14cb3f0095e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33140 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21sb/intel/ibexpeak/smihandler: Move finalizing to a common locationArthur Heymans
TODO: There is no reason to do this in SMM. Change-Id: I8bbb2f65bbe674bd1bc4ae8a4086bd1f5e9a79fa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33139 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-19{mb,sb}: Use get_acpi_table_revision(FADT)Elyes HAOUAS
Change-Id: Id3d7f021a52e08906ae0a3f794756e397601fe96 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33428 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-13 02:20:07 +0000