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2023-07-12mb/{google, intel}: Enable PCH Energy Reporting for MTL platformsSukumar Ghorai
This patch enables PCH to CPU energy report feature which can be used by Intel Telemetry Driver. BUG=b:269563588 TEST=Able to build and boot google/rex and perform below check to ensure the energy reporting is correct w/o this cl: # lspci -s 00:14.2 -vvv | grep "Region 0" Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K] # iotools mmio_read32 0x957f8068 #i.e., 104th offset 0xXXXX0000 w/ this cl: #lspci -s 00:14.2 -vvv | grep "Region 0" Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K] # iotools mmio_read32 0x957f8068 #i.e., 104th offset 0xXXXXfc004 Change-Id: I9bd4625ea311a05071878aaec68433a1ba018c0d Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76353 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-06-23soc/intel/meteorlake: Rename shared SRAM aliasesPratikkumar Prajapati
Rename shared SRAM aliases for IOE and PMC to make them more readable. pci device 13.3 is IOE shared sram, renamed to ioe_shared_sram. pci device 14.2 is PMC shared sram, renamed to pmc_shared_sram. Rename them in SOC code as well as mainboard to make sure the patch builds for the relevant boards. BUG=b:262501347 TEST=Able to build. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I02a8cacc075f396549703d7a008382e76258f865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75999 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21meteorlake: Rename `SOC_INTEL_METEORLAKE_U_P` as per latest EDSSubrata Banik
This patch renames config `SOC_INTEL_METEORLAKE_U_P` to `SOC_INTEL_METEORLAKE_U_H` as per Intel Meteor Lake Processor EDS version 1.3.1 (doc number: 640228). With new branding, the MTL-U/H-Processor Line offered in a 1-chip platform that includes the Compute, SOC, GT, and IOE tile on the same package. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I032be650bbfef0bf0ef86bb37417b1d854303501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75931 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-06-20mb/intel/mtlrvp: disable acpi timer for xtal shutdownSukumar Ghorai
acpi timer needs to be disabled for xtal shutdown, requirement for platform to enter deepest sleep state (s0i2.2). BUG=b:274744845 TEST=Able to boot and verify S0ix is working w/o this cl: > iotools mmio_read32 0xfe0018fc 0x0 > iotools mmio_read32 0xfe4018fc 0x0 w/ this cl: > iotools mmio_read32 0xfe0018fc 0x2 > iotools mmio_read32 0xfe4018fc 0x2 Change-Id: Ib87b7555217b6954fca98f95b86d03016cd9b783 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75898 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-17soc/intel/meteorlake: Update tcss_usb3 aliasEric Lai
TCSS and TBT use the same lane on schematic. Update the port start from 0 to match the Intel schematic. You can better follow the it without convert the port number. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-12mb/intel/mtlrvp: Add CPU power limit valuesSumeet Pawnikar
Add support of variant_devtree_update() function to override devtree settings for variant boards. Also, add CPU power limit values for mtlrvp baseboard. BRANCH=None BUG=None TEST=Built the changes Change-Id: I11bc17f25d4880562d016e29f81e37e068bb6757 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-04mb/intel/mtlrvp: Select SOC_INTEL_METEORLAKE_U_PSubrata Banik
Intel/MTLRVP is built with Intel Meteor Lake-U SoC, so select it. Currently, there is no functional difference, but in the future FSP UPD parameters can be overridden properly. BUG=b:276697173 TEST=Able to build and boot intel/mtlrvp. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8b1dec47ef9d12ac50317b86c4f0bc5fbe4e4dc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75607 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-03mainboard/intel/mtlrvp: Refactor the kconfig selectionsSridhar Siricilla
The patch orders MTL RVP board Kconfigs alphabetically. TEST=Build the code for mtlrvp Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ib8557aab2848a384fba5203e5f3d62407b2566ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/74838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-04-21mb/intel/mtlrvp: Enable RTD3 root port mutex for WWANCliff Huang
This adds RTD3 RPMX mutex to the root port. It is shared between RTD3 and WWAN. The purpose of using this mutex is to prevent OSPM from calling _ON and _OFF methods while WWAN kernel driver is calling _RST, which accesses the GPIO pins. BUG=NA TEST=boot to OS and check the generated SSDT table for the root port. The RPMX mutex should be generated under the root port. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I5b53765453bac0fc96e9651ab347069c7c8bf058 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73384 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-17Makefiles: Drop redundant VARIANT_DIR definitionsKyösti Mälkki
Change-Id: Ie75ce1eee3179a623da812a6b76c7ec457684177 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-11mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MBSubrata Banik
This patch updates the MTLRVP debug flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Increase to 7.5MB. RW_LEGACY: Introduce with 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 2MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot intel/mtlrvp with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie635e3cce1c3fd771e6a17e4b3c1bd700f4729bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MBSubrata Banik
This patch updates the MTLRVP flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Reduce to 7MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 3MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot intel/mtlrvp with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibd1ea7a3a2cd21928b8e33473c7bdddfad17c636 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11mb/intel/mtlrvp: Enable PCIe port 6 and RTD3 support for x1 slotCliff Huang
This change enables PCIe x1 slot. In addition, it turns off 3.3v and 12v power and assert PERST# when suspend and turn on the power and deassert the PERST# when resume for the x1 slot. NOTE: Kconfig flag and required GPIO pins are already configured. - /soc/intel/meteorlake/Kconfig select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 - gpio.c: /* GPP_A18: X1_PCIE_SLOT3_PWR_EN */ PAD_CFG_GPO(GPP_A18, 1, DEEP), /* GPP_A19: X1_DT_PCIE_RST_N */ /* SRCCLKREQ: GPP_C12: SRCCLKREQ3_GEN4_X1_DT_SLOT3_N */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), BUG=b:224325352 BRANCH=None TEST=Insert a SD card or NIC AIC on PCIe x1 slot and the AIC should be detected and enabled at boot. For S0ix, run 'suspend_stress_test -c 1'. The RP6 should not cause any suspend and resume issue. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Id2e92acf754569a22ea76a68c91aafce0075a742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73054 Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-06mb/intel/mtlrvp: Use `-` over `.` in chromeos-debug-fsp.fmdSubrata Banik
This patch renames debug FMD file (chromeos.debug-fsp.fmd) to chromeos-debug-fsp.fmd in order to match the file path name in `FMDFILE` config. TEST=Able to build intel/mtlrvp with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic8de07e4befa6b1ab8ab57d593c6939d87c48e9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-04mb/google/mtlrvp: Update MTLRVP Flash LayoutUsha P
This patch updates the MTLRVP flash layout to allow CSE Lite FW update and accommodate multiple ESx SoC stepping blobs. SI_BIOS: SI_EC: Removed RW_SECTION_A/B: Increased by ~1.9MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections Additionally, moved RW_LEGACY under extended BIOS region. For chromeos-debug-fsp.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.2MB. RW_LEGACY: Dropped RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections BUG=b:271407315 TEST=Able to enable CSE update on MTLRVP and have free space to add one more PUNIT FW to support different SoC stepping. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I8cfba861e6d3122b0795a5a8e589c67cebad9762 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73378 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-04-04mb/intel/mtlrvp: Add fmd for debug FSPUsha P
Debug FSP is ~920KiB larger than release FSP and we don't have sufficient space for MTL-P RVP flash layout. Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a room for it. BUG=b:271407315 TEST=Build intel/mtlrvp with CONFIG_BUILDING_WITH_DEBUG_FSP. Change-Id: Ief7dd39af018c4c1519ca80d1303085d8298cda6 Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74193 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-03-16mb/intel/mtlrvp: Add new MTL-P board variant for MCHP1727Harsha B R
This patch will add new board variant to enable MCHP1727 EC Card for MTL-RVP BUG=b:262800416 BRANCH=none TEST=check if you can observe MEC EC option as part of make menuconfig. Able to boot to ChromeOS with Microchip EC. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie0d3c37bcab5e4b90a131e17996c4b6dcbae7d5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-23mb/intel/mtlrvp: Move MX98357A codec out of soundwire nodeYong Zhi
MX98357A is not a soundwire codec, so move it out of drivers/intel/soundwire node. BUG=none TEST=Build and boot MTL-P RVP to Chrome OS. Verify I2S audio card enumeration and no max98357a entry under /sys/bus/soundwire/devices. Signed-off-by: Yong Zhi <yong.zhi@intel.com> Change-Id: I24fc7084ea18445c341eed012cfacde8de126fd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com>
2023-02-15mb/intel/mtlrvp: Enable mipi_camera for MTL-P RVPUsha P
Add support for MTL-P RVP mipi camera functionality BUG=None TEST=Build and boot MTL-P RVP to Chrome OS. Verify SSDT entries related to mipi camera and verify camera working. Scope (\_SB.PCI0.I2C1) { Device (CAM0) Scope (\_SB.PCI0.I2C0) { Device (CAM1) Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I698edd7155fc38477f3416900799e61d3295fd1a Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Harsha B R <harsha.b.r@intel.com>
2023-02-15mb/intel/mtlrvp: Enable Audio for MTL-P RVPUsha P
This patch adds FW_CONFIG and codec support for MTL-P RVP BUG=None TEST=Build and boot MTL-P RVP to Chrome OS. Verify audio codec listed under aplay -l and audio working with the connected audio card. localhost ~ # aplay -l **** List of PLAYBACK Hardware Devices **** card 0: sofrt5682 [sof-rt5682], device 0: Headset (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 1: Speakers (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 5: HDMI1 (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 6: HDMI2 (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 7: HDMI3 (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 card 0: sofrt5682 [sof-rt5682], device 8: HDMI4 (*) []   Subdevices: 1/1   Subdevice #0: subdevice #0 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Ib29ac3e4105e578e1555076d180b35a8265a99c8 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-15mb/intel/mtlrvp: Enable S0ixUsha P
This patch enables S0ix for MTL-P RVP platform BUG=None TEST=Able to enter low power idle S0 on MTL-P RVP Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Id84f21d81197e44d6dd0dd8888c80848aa3679e0 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71994 Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-02-10mb/intel/mtlrvp: Enable DPTF functionality for mtlrvp boardSumeet Pawnikar
Enable DPTF functionality for Meteor Lake based mtlrvp board BRANCH=None BUG=None TEST=Built and booted on mtlrvp board Change-Id: I8d3e1cd43cf67c3f2081be339589a6da358b668c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-08mb/intel/mtlrvp: Enable PCIE Advanced Error ReportingHarsha B R
This patch enables PCI Express Advanced Error Reporting Capability for WWAN, WLAN, and SSD root ports. On enabling PCIE_RP_AER, PCIE device will automatically report (if any error) about the error nature to the corresponding PCIe root port. BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Iab8619818e2219b41287b895513eb04b0464401e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-08mb/intel/mtlrvp: Add ACPI configuration for USB2/3 portsHarsha B R
This patch adds ACPI configuration for USB2/3 ports for mtlrvp as per schematics. This helps in generating corresponding ACPI code at runtime that includes port information. BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP. Connect USB device and check if corresponding enumeration of USB device (14.0) is observed on executing lspci. 00:14.0 USB controller: Intel Corporation Device 7e7d (rev 01) 00:14.1 USB controller: Intel Corporation Device 7e7e (rev 01) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie150247661322e3944be15dc70f66033266d8aac Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72787 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/intel/mtlrvp: Describe mainboard configuration for BB RetimerHarsha B R
This patch describes BB retimer for tcss_dma0 and tcss_dma1 with respect to GPP_B21 as per schematics. +--------------+------------+ | tbt_pcie_rp0 | tcss_dma0 | +--------------+------------+ | tbt_pcie_rp1 | tcss_dma0 | +--------------+------------+ | tbt_pcie_rp2 | tcss_dma1 | +--------------+------------+ | tbt_pcie_rp3 | tcss_dma1 | +--------------+------------+ BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration of tbt_pcie_rp as part of lspci. 00:07.0 PCI bridge: Intel Corporation Device 7ec4 00:07.1 PCI bridge: Intel Corporation Device 7ec5 00:07.2 PCI bridge: Intel Corporation Device 7ec6 00:07.3 PCI bridge: Intel Corporation Device 7ec7 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie1a0026b064aa4f7fcd27e75c0b0d052ec620dcc Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72786 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/intel/mtlrvp: Describe TCSS USB portsHarsha B R
This patch describes the TCSS USB ports for mtlrvp as per schematics. This patch describes TCSS ports for UPC_TYPE_C_USB2_SS_SWITCH as below, tcss_usb3_port1: USB3 Type-C Port C0 tcss_usb3_port2: USB3 Type-C Port C1 tcss_usb3_port3: USB3 Type-C Port C2 tcss_usb3_port4: USB3 Type-C Port C3 BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration of xhci (0d.0) as part of lspci. Also verify the enumeration of Type-C ports as part of cbmem -c. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72785 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/intel/mtlrvp: Enable WWAN ACPIHarsha B R
This patch enables FM350GL 5G WWAN support for mtlrvp. BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module 00:1c.6 is enumerated as part of lspci and cbmem -c in AP console. Also verify generation of PXSX Device as part of SSDT. Able to connect WiFi and access internet. cbmem -c: \_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3) \_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL) SSDT: Scope (\_SB.PCI0.RP07) { Device (PXSX) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I870cc0782fb989f1bdbe369a4a12630a62729d8e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72779 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-07mb/intel/mtlrvp: Enable GSPI interfaceHarsha B R
This patch enables GSPI [1] interface for mtlrvp based on mtlrvp schematics. BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to ChromeOS. (Base patch for CB:71223) SPI[0].Mode = 0 SPI[0].DefaultCsOutput = 0 SPI[0].CsMode = 0 SPI[0].CsState = 0 SPI[1].Mode = 1 SPI[1].DefaultCsOutput = 0 SPI[1].CsMode = 0 SPI[1].CsState = 0 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-07mb/intel/mtlrvp: Enable PCIe port 8 for WLANHarsha B R
This patch enables PCIe port for WLAN as per mtlrvp schematics BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Ensure that WLAN module gets is enumerated as part of lspci in AP console. ae:00.0 Wireless controller [0d40]: Intel Corporation XMM7360 LTE Advanced Modem (rev 01) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ief3c0eff40ced57d29ce343e569b6b392c27ad74 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72778 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHESHarsha B R
This patch enables EC_GOOGLE_CHROMEEC_SWITCHES for MTL_CHROME_EC which helps in mode switch using dut-control power_state:rec. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP to ChromeOS. Check if chroot command dut-control power_state:rec puts the DUT to recovery mode. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I5de0cd6c9a50bd85238205e09976a8bd8dd7142f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-07mb/intel/mtlrvp: Enable PCIe port 7 for WWANHarsha B R
This patch enables PCIe port for WWAN as per mtlrvp schematics BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module gets enumerated with cbmem -c. \_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3) \_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72777 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07mb/intel/mtlrvp: Enable ACPI support for Type-C portsHarsha B R
This patch adds ACPI support for Type-C ports. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP. Verify SSDT for the corresponding entry, \_SB.PCI0.PMC.MUX.CON0 under Device (CON0) \_SB.PCI0.PMC.MUX.CON1 under Device (CON1) \_SB.PCI0.PMC.MUX.CON2 under Device (CON2) \_SB.PCI0.PMC.MUX.CON3 under Device (CON3) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72789 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-05mb/intel/mtlrvp: Add chip configuration for I2C devicesHarsha B R
This patch adds below chip configuration for I2C devices for mtlrvp. +-----------+--------------------+-------------+ | INTERFACE | PCI Number (B:D:F) | DEVICE | +-----------+--------------------+-------------+ | I2C0 | 0:0x15:0 | CAM1 | +-----------+--------------------+-------------+ | I2C1 | 0:0x15:1 | CAM0 | +-----------+--------------------+-------------+ | I2C2 | 0:0x15:2 | NC | +-----------+--------------------+-------------+ | I2C3 | 0:0x15:3 | HID | +-----------+--------------------+-------------+ | I2C4 | 0:0x15:4 | NC | +-----------+--------------------+-------------+ | I2C5 | 0:0x15:5 | NC | +-----------+--------------------+-------------+ BUG=b:224325352 BRANCH=None TEST=Able to boot mtlrvp (LP5/DDR5) to ChromeOS. Also verify serial bus enumeration through lspci. 00:15.0 Serial bus controller: Intel Corporation Device 7e78 (rev 01) 00:15.1 Serial bus controller: Intel Corporation Device 7e79 (rev 01) 00:15.3 Serial bus controller: Intel Corporation Device 7e7b (rev 01) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ia5964472be902041f961187c0072a89055badd4f Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-05mb/intel/mtlrvp: Override display configurationHarsha B R
This patch enables display configuration for mtlrvp. The change follows mtlrvp schematics. BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump. Also verify display over eDP and HDMI. DdiPortAConfig : 0x1 DdiPortBConfig : 0x0 DdiPortAHpd : 0x0 DdiPortBHpd : 0x1 DdiPortCHpd : 0x0 DdiPort1Hpd : 0x0 DdiPort2Hpd : 0x0 DdiPort3Hpd : 0x0 DdiPort4Hpd : 0x0 DdiPortADdc : 0x0 DdiPortBDdc : 0x1 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I05bd7427d6a339ee200731a8dd448e85efc694e0 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-05mb/intel/mtlrvp: Remove GPP_A12 for chrome platformHarsha B R
This patch removes the configuration of GPP_A12 for mtlrvp. Garfield Peak (WLAN) doesn't use GPP_A12 for WAKE_N. Configuring GPP_A12 pin prevents system entering G3 (reboots) on issuing shutdown -h now. Hence configuring GPP_A12 as PAD_NC. BUG=b:224325352 BRANCH=None TEST=On issuing 'shutdown -h now' system enters G3 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I5e46b8afd3e0055440fd3c3db4aa5a9f1d4aa556 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com>
2023-02-04mb/intel/mtlrvp: Enable CNVi BT Core and WifiHarsha B R
This patch enables CNVi_BT Core and Wifi for mtlrvp based on mtlrvp schematics. 1. Enable CNVi BT Core in device tree 2. Enable CNVi Wifi (pci 14.3) device in device tree BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to ChromeOS. CNVi Mode = 1 Wi-Fi Core = 1 BT Core = 1 BT Audio Offload = 0 BT Interface = 1 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I22575bf31b540f9dc1149a2766268285001b72f4 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-01mb/intel/mtlrvp: Modify the print messageHarsha B R
This patch updates the print message to start with uppercase, 'board' to 'Board'. BUG=b:224325352 BRANCH=None TEST=Able to observe proper print message when invalid board id is configured. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie82df940cbd1eba9c5d485b48648c2bc8f234aae Reviewed-on: https://review.coreboot.org/c/coreboot/+/72638 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-30mb/intel/mtlrvp: Add romstage and configure LP5 memory partsAshish Kumar Mishra
This patch adds initial romstage code and spd data for LP5 memory parts for MTL-RVP. This also configures memory based on the board id. Memory - x32 LPDDR5 Vendor/Model - Micron/MT62F2G32D8DR-031 WT:B Board ID - 0b0000 - Empty spd hex file 0b0001 - DDR5 (Empty spd hex file) 0b0010 - LPDDR5 (MT62F2G32D8DR-031 WT:B) BUG=b:224325352 TEST=Able to boot intel/mtlrvp (LP5 SKU) to ChromeOS Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Change-Id: I15b352eb246aed23da273e56490c7094eae9d176 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-11mb/intel/mtlrvp: Configure USB devices for MTL-RVPHarsha B R
This patch adds OC configuration of USB devices for MTL-RVP as per MTL-RVP design specification, USB 2.0 usb2_ports0 -> OC0 usb2_ports1 -> OC0 usb2_ports2 -> OC0 usb2_ports3 -> OC0 usb2_ports4 -> OC0 usb2_ports5 -> OC0 usb2_ports6 -> OC_SKIP usb2_ports7 -> OC_SKIP usb2_ports8 -> OC_SKIP usb2_ports9 -> OC_SKIP USB 3.2 Gen 2x1 usb3_ports0 -> OC0 usb3_ports1 -> OC0 TCPx tcss_ports0 -> OC0 tcss_ports1 -> OC0 tcss_ports2 -> OC0 tcss_ports3 -> OC0 BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to chromeOS (on top of CB: 66190). Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: If1a0c31b7bf0f3fc06f039ad76b0cdd41f7cdd90 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-10mb/intel/mtlrvp: Add romstage and configure DDR5 memory partsJamie Ryu
This patch adds initial romstage code and spd data for DDR5 memory parts for MTL-RVP. This also configures memory based on the board id. Memory - x32 DDR5 SBS SODIMM 1DPC Vendor/Model - SK-Hynix/HMCG66MEBSA092N BUG=b:224325352 TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-04mb/intel/mtlrvp: Enable CSE Lite SKU for MTL-RVPHarsha B R
This patch will enable Kconfig SOC_INTEL_CSE_LITE_SKU option required to enable CSE-Lite SKU for MTL-RVP. On enabling the respective Kconfig option, CSE reboots the system into CSE_RW FW region on cold reboot. BUG=b:224325352 TEST=Able to boot intel/mtlrvp to ChromeOS and also able to observe CSE boot to RW FW region as part of coreboot console log, localhost ~ # cbmem -c | grep cse [DEBUG] cse_lite: Number of partitions = 3 [DEBUG] cse_lite: Current partition = RW [DEBUG] cse_lite: Next partition = RW Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I325405cc304d245871396317c11ac7a5b062a5bd Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71638 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-29mb/intel/mtlrvp: Add configuration for UART devicesHarsha B R
This patch adds below configuration for MTL-RVP UART devices, Interface -> UART0 PCI -> 0:0x1e:0 Device -> AP UART BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp ito chromeOS using subsequent patches in the train. UART logs appear on AP console. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I4702d603aa49357f4db0d18d646e536d9d81787e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70873 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-29mb/intel/mtlrvp: Configure GPIO Tier-1 GPEs for MTL-RVPHarsha B R
Configure GPIO Tier-1 GPE's that defines the route for GPE events for MTL-RVP. Configure GPE route as below, PMC_GPE0_DW0 -> GPP_B PMC_GPE0_DW1 -> GPP_D PMC_GPE0_DW2 -> GPP_E BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to ChromeOS using subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ieab95b72ade75734b0788a32566649d90acbc48a Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70872 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-27mb/intel/mtlrvp: Configure devicetree and GPIOs for MTL-RVPHarsha B R
Add devicetree and GPIO configuration for MTL-RVP Changes include, 1. Add initial devicetree to support MTL-RVP board & variant 2. Add initial setup for ramstage gpio config BRANCH=none BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp to chromeOS using subsequent patches in the train. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I3173c3f32b36d24467431df3652badd70efeab93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-27mb/intel/mtlrvp: Add bootblock and early gpio for MTL-RVPHarsha B R
This patch adds initial bootblock code. This also configures required GPIOs for early board initialization. 1. Add bootblock file for MTL-RVP 2. Add early gpio config for MTL-P variant in gpio.c BRANCH=none BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform to ChromeOS with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I9c0893e52036147c5f6bbfafc6d818e9d3460bed Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-21mb/intel/mtlrvp: Enable ChromeOS build for mtlrvpHarsha B R
This patch enables building ChromeOS for mtlrvp. Patch includes, 1. Add cros_gpios for mtlrvp 2. Add chrome OS configuration in Kconfig 3. Add Chromeos.c BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train (CB: 69886) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ia428941bd8269714c3edca6c7b0c2a3fbf08bd75 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70724 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20mb/intel/mtlrvp: Add files required for ramstage and SMMHarsha B R
This patch adds files required for ramstage and SMM. 1. Add file required for ramstage (mainboard.c) 2. Add smihandler.c for SMM BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I377c4ff954a900c7b5193d7cab5554c6c02573ee Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70723 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20mb/intel/mtlrvp: Enable EC for mtlrvpJamie Ryu
This patch will initialize EC for mtlrvp which includes, 1. Add configuration (& choice) for CHROME_EC and INTEL_EC (WINDOWS_EC) 2. Add respective ACPI configuration 3. Add ec.c required for ramstage 4. Program EC ranges as part of devicetree.cb 5. Enable VBOOT in Kconfig BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with CHROME_EC using subsequent patches in the train Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66101 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09mb/intel/mtlrvp: Add MTL-P RVP board idsJamie Ryu
This adds MTL-P board id definition. Change include, 1. Add board_id.c implementation 2. Add board_id.h implementation 3. Add board_id config in variants.h 4. Makefile changes BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I90b0543d5db208f696d2c2c2dc3d2581514a845b Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66102 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-09mb/intel/mtlrvp: Add initial code for mtlrvp_p_ext_ec variant boardHarsha B R
This patch adds the initial code for mtlrvp_p_ext_ec variant board which includes 1. support for 2 mainboards (Chrome EC and Windows EC) by adding overridetree.cb to corresponding directory 2. Move devicetree to baseboard/mtlrvp_p 3. Update mainboard name in Kconfig and Kconfig.name 4. Add config option to select corresponding overridetree.cb Subsequent patches include patch train starting from (CB - 66102) BUG=b:260654043 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I83948aa5e9fcaadee4745e313360773c48142f89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com>
2022-11-27mb/intel/mtlrvp: Create baseboard structure for mtlrvpHarsha B R
This patch will create the baseboard structure for mtlrvp. Changes include, 1. Adding Baseboard config for mtlrvp in Kconfig 2. Move gpio.h to corresponding baseboard directory 3. Append header reference to CPPFLAGS_common in Makefile.inc BUG=none TEST=FW_NAME=mtlrvp_p emerge-rex coreboot chromeos-bootimage Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I82acb6879fecb242014258f2c358804d5abbbd48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69971 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-08mb/intel/mtlrvp: Enable ACPI and add ACPI tableJamie Ryu
This enables ACPI configuration and add ACPI table. BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I8264197fd0acdd7e19b9a36fb22822447b013202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66100 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-07mb/intel/mtlrvp: Add MTL reference mainboard for MTLRVP-PJamie Ryu
This adds an initial mainboard code for mtlrvp, Intel Meteorlake reference platform. BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I097db4de9734ff81283cf470aabf3eb23b63aab8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66097 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-19mb/intel/mtlrvp: Add board_info.txtTim Wawrzynczak
Builds are failing on upstream master branch because there is no board_info.txt for the Intel Meteor Lake RVP mainboard; this patch adds a basic one so the tree will build. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3356ad65132dc4aaebd5e7d959a2bdb9ab1316b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67711 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-09-19mb/intel/mtlrvp: Add flashmap descriptorJamie Ryu
This adds 32MB flashmap descriptor as below: Descriptor Region: 0x0 - 0x3fff (~16KB) Intel EC Region: 0x4000 - 0x83fff (~512KB) ME Region: 0x84000 - 0x8fffff (~8.5MB) BIOS Region: 0x900000 - 0x01ffffff (~23MB) BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ifb572efe56eb7400b8328ba797892738f5927158 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66098 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-13 22:03:11 +0000