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path: root/src/mainboard/intel/cedarisland_crb
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2021-01-27ACPI: Add top-level ASLKyösti Mälkki
Objects that are created with acpigen need to be declared with External () for the generation of dsdt.asl to pass iasl without errors. There are some objects that are common to all platforms, and some that should be declared only conditionally. Having a top-level ASL helps to achieve this. Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21soc/intel,mb/*: get rid of legacy pad macrosMichael Niewöhner
Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-03soc/intel/xeon_sp: Use common ASL code for xeon_spMarc Jones
Move and use the common xeon_sp/cpx/acpi asl for skx/. There were only minor whitespace differences between the directories. Update the mainboards to build the moved files. TiogaPass coreboot.rom checked with BUILD_TIMELESS. Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/intel: Drop unneeded empty linesElyes HAOUAS
Change-Id: I3fdc521d30155c4275c336afe03244311f584e71 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44617 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/intel/cedarisland: Remove duplicated codeMaxim Polyakov
Some UPD options are already set in `xeon_sp/cpx/romstage.c`. Remove them from the board configuration to avoid duplicating this code. Change-Id: Ic79245103c33427e06c7ea881be778e3d219c45f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43924 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03mb/intel/cedarisland: Use FSP_M_CONFIG structure to set UPDMaxim Polyakov
According to src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h, use FSP_M_CONFIG structure fields to configure UPD options for FSP-M in romstage instead of raw offsets. Change-Id: Idb25d8954b09805b496ab97b341a8ef1ac38bb6a Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26mb/intel/cedarisland/Makefile: Add missing ramstage.cMaxim Polyakov
Fixes a bug in Makefile.inc, which did not allow building ROM image with ramstage.c from motherboard configuration. Change-Id: I70d8a2e1f53e2fa56d514361116a55f175407753 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43457 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25mb/intel/cedarisland: undo set trig and bufdis for NF padsMaxim Polyakov
According to the documentation [1], RX Level/Edge Configuration (trig) and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable in native mode and BIOS does not need to configure them. Therefore, there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG macros. Use PAD_CFG_NF instead and set this fields to 0. [1] Intel document #549921 [2] Intel document #336067-007US This is part of the patch set "src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ": CB:43455 - cedarisland: undo set trig and bufdis for NF pads CB:43454 - tiogapass: undo set trig and bufdis for NF pads CB:43561 - h110m: undo set trig and bufdis for NF pads CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG Change-Id: Ie3ee2eadc08826d49e8517c83ab6831398e3aa93 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43455 Reviewed-by: Michael Niewöhner Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01mb/intel/cedarisland_crb: Enable P2SB deviceAndrey Petrov
Enable P2SB in static device tree so that hide/unhide trick works. Change-Id: I7dc20b001605b715155d333a07580e21a5f24136 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-MAndrey Petrov
These parameters were found to work fine for 2-socket configuration, for FSP based on tag 16.D.21. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-30mb/cedarisland_crb: rework GPIOs configuration using macrosMaxim Polyakov
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility: ./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. [1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921 Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40736 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-30mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-MMaxim Polyakov
We should be sure that after romstage the pads will be configured according to the config from gpio.h only. This patch sets the GPIO configuration from gpio.h using the soc/intel/common/gpio.c driver again in ramstage. [1] https://review.coreboot.org/c/coreboot/+/40730 Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-30mb/intel/cedarisland_crb: use common driver to configure GPIOMaxim Polyakov
According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with vendors firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-04-24mb/intel/cedarisland_crb: Add dummy mainboard_memory_init_params()Andrey Petrov
Add a dummy implementation (currently FSP defaults are meant for CRB). It is needed only to prevent build breakage. Change-Id: I67b1a693886a29bdaf23f1f3f249da52ba65451a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-03-26mb/intel/cedarisland_crb: Add Cedar Island CRBAndrey Petrov
Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: Ie2f944964e938d8026a6d5d8a22a8449199d08aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/39714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 20:17:40 +0000