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Side effect was observed that after override BayHub EMMC
driving strength to the max, EMMC CLK will be reduced to
51.x Mhz from 200 Mhz.
This will cause OS installation fail on Samsung EMMC sku.
BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I848ab0cae474b15fbc4264c8ade63d5c6b4e489d
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This file contains two instances of "dptf_enable" = "1". This change
removes the 2nd instance (it doesn't have an explicit comment like the
1st instance).
The dptf devices still seem to be present even with this change, as
expected.
Change-Id: I890006644be9176ebaf555cc121c816e12f2b596
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The spec of the sx9310 says the I2C interface can handle standard
(100kb/s) and fast mode (400kb/s). The current setting is using fast
plus (1000kb/s) so this change is reducing the speed to fast mode.
I've been using the sensors with this change for a few weeks now, though
I also don't recall seeing an issue prior to this change.
Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This reverts commit 1fdb76945a9d06bbff37dee9da69e13a86c933f4.
Camera power is now handled by ACPI rules - no need to force the GPIOs
on by default.
BUG=b:80106316,b:111141128
Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28072
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ping-chung Chen <ping-chung.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This defines new GPIO pin for controlling the display panel CABC
function. The default value is high (enabled).
BUG=b:112154569
Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28070
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This updates the DPTF sensor names to reflect the sensor locations on
the board.
BUG=b:75454415
TEST=verified new strings show up in
/sys/devices/LNXSYSTM:00/LNXSYBUS:00/INT3400:00/*/description
Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28069
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia38c6f8d978065090564d449cae11d54ddb96421
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch updates Power Limit (PL) for AML.
- PL1 as 5W TDP as POR
- PL2 as 18W TDP as POR
BUG=None
BRANCH=None
TEST=Build coreboot for Nocturne board and check default PL1/PL2 TDP.
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_0_power
5000000 (5W TDP)
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_1_power
18000000 (18W TDP)
Change-Id: Icb02a8a7c5fcd5e6aee45f14eba540a6b3ed3d67
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/27427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add TSR2 DART/DTRT package
BUG=b:110451144
BRANCH=nami
TEST=emerge-nami coreboot chromeos-bootimage
Test image with dptf.dv
Change-Id: I3328e17328415f5ebdcf84263e5456e11e55f769
Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This change updates GPIO configuration for bobba boards with id >= 1
This follows the same model as fleex:
a. Dynamically update touchscreen power enable GPIO in devicetree.
b. Provide default and bid0 tables for GPIO configuration in ramstage.
c. Configure WLAN enable GPIO differently in bootblock based on
boardid.
BUG=b:112354568
TEST=Built firmware for bobba
Change-Id: Id4ee4a1815e16ddfe60ed268688a8aaf4fb75579
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/28071
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I189c981f3334836ab24bbc74491e9b58a2d403a4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/27921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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All broadwell board set HAVE_IFD_BIN to default n, overloading the option in
soc, therefore just use the defaults in sb/intel/common/firmware.
Change-Id: I250dbbc9d61ecedc1a1eb48751ad966732604349
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28011
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is no need set the default HAVE_IFD_BIN explicitly to n.
Change-Id: I4a5fe45e7f8f6dd018937861b0fb92a8da49904e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28008
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is no need to redefine option present in
southbridge/intel/common/firmware/Kconfig.
Change-Id: I9999440031b07006e2df11e00dfb9f3dbe04f832
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3108193c0e0b644cecb74ae0c7a7b54e24a75b58
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I80dd65484fd52e9048635091fb20a123e959e999
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27869
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=none
BRANCH=master
TEST=emerge-octopus coreboot
Change-Id: Ic61a69e19e97520da0702dfe6cb7496563fc34f4
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Remove icc_max overrides to allow SoC code to set proper
icc_max based on CPU SKU.
BUG=b:78122599
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash to
nocturne, boot to kernel and verify device doesn't hang after
a few minutes.
Change-Id: I37c44e2428b802d754f2b12b8a57601d257e6582
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27996
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.
BUG=b:110890675
BRANCH=None
TEST=emerge-nocturne coreboot chromeos-bootimage & test with AML-Y
and KBL-Y skus.
Change-Id: Idfdc0c2434fdef56a7c25df05e640837a5096973
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27997
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.
BUG=b:110890675
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage & test with AML-Y
and KBL-Y skus.
Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27765
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow thermal table (b:112274477 comment#1) for first tunning.
BUG=b:112274477
TEST=Match the result from DPTF UI.
Change-Id: I63b2e50a4f6fc5453e6564e277600498ac0e6244
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Enable the GEO SAR feature for Octopus. Program wifi_sar VPD key.
coreboot reads the VPD and creates the ACPI table as per the WGDS spec.
BUG=b:112288077
TEST=Program VPD key, extract acpi table ssdt and valiate WGDS entry.
Change-Id: I40a6fd9e0ec8b440996bf3389322fd89bcca15a4
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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PERST signal is asserted/deasserted by ACPI routines during
suspend/resume. Configuring IOStandby for WLAN_PE_RST can result in
failure to resume from suspend state with wake-over-WLAN. This change
removes the IOStandby configuration for WLAN_PE_RST.
BUG=b:112371978
Change-Id: Ic7c0b2aa144233f8bbb4e5169d96347a1290abe1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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When CNVi is being used, external wake using GPIO_119 is not
required. This change configures GPIO_119 as PAD_NC if CNVi is taken
out of reset.
BUG=b:112371978
Change-Id: Ifee90f428ed43c4d7c612c170476aff43b4a33ce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change uses drivers/intel/wifi chip for CNVi device to ensure
that:
1. Correct device name shows up in ACPI node
2. It is possible to pass any parameters from devicetree to wifi
driver for SSDT generation.
BUG=b:112371978
Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change checks to see if CNVi module is out of reset:
1. If yes, then PCIe device for WiFi is disabled.
2. If no, then CNVi device is disabled.
BUG=b:112371978
Change-Id: I6e6cf2e646c897df017913056db87ac0cffa1a8e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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I2C2 is unused on all octopus variants. This change disables it in
devicetree.
BUG=b:112458032
Change-Id: I55abef864c06a448011f9570d3e6c0aa8bfdc5bc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28016
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change updates GPIO configuration for fleex boards with id >= 1
This follows the same model as phaser:
a. Dynamically update touchscreen power enable GPIO in devicetree.
b. Provide default and bid0 tables for GPIO configuration in ramstage.
c. Configure WLAN enable GPIO differently in bootblock based on
boardid.
d. Disable unused I2C devices in devicetree.
BUG=b:112458032
TEST=No errors observed on boot-up on fleex.
Change-Id: Ib4c449168b08e2393e2395d6b49469be5599c2ce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/23759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Allow for shared dram configuration by introducing a new table
that collapses the common settings after removing the part
numbers. When employing this scheme the part number comes
from CBI.
BUG=b:112203105
TEST=Placed part number in cbi. Faked out memory sku id. And enabled
DRAM part num always in cbi. Everything checked out.
Change-Id: I5229695ce3eb686421b89ac55d8df4b9fcec705c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Rotor is dead, long live [PROJECT NAME REDACTED]!
Change-Id: Ia9308944257255e077a44c1df262c7f49c69890c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27964
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add 3 new Kconfig options:
DRAM_PART_NUM_IN_CBI
DRAM_PART_NUM_ALWAYS_IN_CBI
DRAM_PART_IN_CBI_BOARD_ID_MIN
These control whether to 1. attempt to use CBI at all 2. always use cbi
and 3. conditionally use cbi based on board id. The intent is that the
MIN variant would be used for the tranisition period then cut over to
ALWAYS after full transition. Since multiple OEMs have different
schedules these options are there to bridge the gap. yorp. bip, and
octopus build targets would never flip DRAM_PART_NUM_IN_CBI, but in case
someone does the MIN values are 255 to always take the old path.
BUG=b:112203105
TEST=Set correct part number on phaser during testing.
Change-Id: If9a0102806d78e89330b42aa6947d503a8a2deac
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Ief6a04ccb63658b5fb03cd1d298bf00948cf7410
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Careena EVT SanDisk EMMC sku has high fail rate of 0x5B reboot failure.
It'll need to increase 1.8V EMMC CLK/CMD, Data driving strength for
this issue.
CLK[6:4]
CMD,DATA[3:1]
original register value: 0x6B
enhanced: 0x7F
BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27816
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Micron material that was broken has long since been fixed that
required this option. glkrvp had these stale entries and were
subsequently copied to octopus. Remove the need for this option.
BUG=b:35581751
Change-Id: Id73584367c2ad0e4958b5ea0f04a28e5fc82d085
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27959
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Skylake SoC code now sets the icc_max based on the CPU SKU, so we
should not hard-code it in the device tree.
BUG=b:110890675
BRANCH=None
TEST=boots on atlas
Change-Id: I7eb3499b7bea9ab2c49e1f299e2dbb688c8d1c33
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
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This configures the ACPI FADT perferred power management profile to
PM_MOBILE instead of PM_DESKTOP.
I'm not sure what impact this actually has. I just noticed the other
boards have it set.
BUG=b:110971913
TEST=Made sure SYSTEM_TYPE_LAPTOP shows up in coreboot.config
Change-Id: Iea1b8359b80d167e69745358f543f025713294ba
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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If GPP_E22(CABC_EN) remained floating GPI(SoC default) at V3.3_DX_EDP on,
it may cause damage on the GPIO pad.
To prevent, we would set this pad to GPO on romstage before EDP power on.
Since we need to cover all systems in market, I put it into romstage
instead of early_gpio_table.
BUG=b:111860510
BRANCH=poppy
TEST=Verified CABC_EN is set to GPO high 5ms before EDP power on
Change-Id: I34e2fe86329a88eb05e0ea3c6beac6a64754b41e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds variant callback to get GPIO configuration table in
romstage and configures these GPIOs before memory training is
performed.
BUG=b:111860510
BRANCH=poppy
Change-Id: I1eb51356fb3f4c0f4ff29b22dbcde6dbece303ad
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change provides implementation of smbios_mainboard_sku() to add
proper "skuX" string to SMBIOS table 1.
BUG=b:112163362
TEST=Verified "dmidecode -t 1" reports skuX correctly.
Change-Id: I7e42d2c80d791ea7170d066d2eeaa0c6811eb9c9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add default PSPP AGESA setting for Kahlee/Grunt mainboards.
BUG=b:112020107
TEST= build test
Change-Id: I8a8605402379de88a04f3a16553c308513fa1531
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Now that an updated bootloader with important fixes is available at coreboot
repository, all stoneyridge boards should use it. Move the selection of
SOC_AMD_PSP_SELECTABLE_SMU_FW from mb/google/kahlee to soc/amd/stoneyridge.
BUG=b:111428800
TEST=Build and boot grunt.
Change-Id: Idf8e348efbc85569aa1163125f412c5242c46eb4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27844
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update power limit1 value from 8W to 10W. There is an error
in the energy calculation for current VR solution on GLK.
Experiments show that when power limit1 set to 10W, gained
performance improvement with SoC TDP reaches max (6W) power.
BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: Ic320d442e7401e4be2e8e16d691db4c803f0fdc1
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds ACPI properties for WDT8752A device.
BUG=b:111402335, b:111102092
BRANCH=master
TEST=Verify touchscreen on fleex works with this change
Change-Id: Id186d5b87343007ae7e631d5d27464ee27e5b27d
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use the default value for Iccmax which is specified in vr_config.c.
The AcLoadline and DcLoadline keep the poppy value. Besides, the
USB 2.0 ports located on the mainboard are set to USB2_PORT_SHORT
and the others on the daughterboard are set to USB2_PORT_LONG.
Those setting need to be fine tuned later.
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: Icabfac04c94b3d480872c243d811509e274ef122
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The gpio setting is based on the proto board schematics
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: I20fc081d372b8686f6128a7e85276f9c6798b199
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Add memory configuration based on the proto board schematics
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: I45efdc7893b5bcbca0de6e932e1452cc1a2ff028
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Rammus uses DA7219 Headset, Maxim MAX98927 Smart Amps and 4 channel dmic
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: If21a3870ee4b000a776d2f3e025fb43ef2fe48c7
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Move the build board directory from poppy to rammus.
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: I3a9fc2bbfe7261661f0c5c073baff0ff1434d09f
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Kahlee based boards don't use SATA, so disable SATA on all boards to save
power.
BUG=b:112139043
TEST=Build and boot grunt, checked the absence of SATA PCI.
Change-Id: I6a12c03a5a95b1c8b40609a3fe656df92548b80b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Since only a handful of boards have descriptor blobs in the tree, it makes no
sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard.
This patch flips the default value of said variable, rendering all current
overrides unnecessary. The few boards which have an IFD in the blobs repo use
`select HAVE_IFD_BIN` to enable adding the IFD by default.
Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed
alongside the latter, and has been added to the boards with a ME blob as
`select HAVE_ME_BIN`.
Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well.
Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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These boards require polling vs interrupts, so remove the IRQ definition to
prevent it being added to the SSDT device entry.
Test: Boot Linux on various auron and cyan variants, verify no error for
'TPM interrupt not working' present in kernel boot log.
Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch applies correct AC/DC loadline settings for Atlas from
VRTT report.
BUG=b:111419622
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage and use DbC to check
the AC/DC loadline settgins.
Change-Id: I6e85b885a6d3a1db9a980d12f3cfc036a771422a
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27788
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch makes sure we deassert the USB hub reset pin so the hub will
work with the next board revision that drops the external pull-up.
(Actual USB support comes in a later patch.)
Change-Id: I1efdc3594cfa3229891d42d445a21c1739170b79
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27790
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds the required callbacks to read all strapping IDs on
Cheza.
Change-Id: I6437bbd03bdd00dfeedcafebabeb00b13588d052
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Tuning of fan speed for different temperature values. Earlier while
running few benchmarks, fan was always getting on and starting at
higher speed. With this change fan will start with lower speed and
slowly speed gets increased if temperature continue going high.
Thermal team provided these data after fine tuning of fan speed.
BUG=None.
TEST=Verified on Nami running with different benchmarks and observed
fan speed.
Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27683
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There is a potential IMVP8 issue for KBL that affects Intersil VRs
Nami is using one of the affected parts. The fix is to use an updated
microcode and also send a mailbox box command from FSP.
BUG=b:112081534
BRANCH=None
TEST=Build and boot Nami
Verify that suspend/resume and consecutive reboots are working
Change-Id: I6ec18a4c3fae6a66cf8a95685d91a8ba51e2697c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/27780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Adapted from chromium commits 831a372 and cc96c27
[Banon: board 2nd source DDR memory]
Add support for hynix/H9CCNNN8GTALAR-NUD and Nanya/NT6CL256T32CM-H1
Original-Change-Id: Ifd161ba5ade44e71c88655f760ca66668b5c5178
Original-Change-Id: I5cba13701ed8e037e21d34ed55162ee56291a842
Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Tested-by: TH Lin <t.h_lin@quanta.corp-partner.google.com>
Original-Reviewed-by: Vincent Wang <vwang@chromium.org>
Original-Reviewed-by: YH Lin <yueherngl@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I2166d1025ede33148c7ab623ba59190a342c4736
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Adapted from chromium commits 2319742 and 3b59fb2
[Edgar: Add Micron MT52L256M32D1PF-107 SPD data]
[Edgar: Add Hynix H9CCNNN8GTALAR-NUD and Nanya NT6CL256T32CM-H1 SPD data]
Supported 2nd source Hynix, Micron, and Nanya memory.
TEST=Built and used mosys command by "mosys -k memory spd print all"
Original-Change-Id: Iec9160b74d2812620d2d28f841d503e2d63c8579
Original-Change-Id: I610f01a0198f835a2038511ff78bf0cfba7812a0
Original-Signed-off-by: Hank2_Lin <Hank2_Lin@pegatroncorp.com>
Original-Reviewed-by: Vincent Wang <vwang@chromium.org>
Original-Reviewed-by: YH Lin <yueherngl@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: If2379d6e58425616f49d77b0cdea1cd90f9a8bfa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Adapted from chromium commit adcb858
[cyan: Configure WLAN_CLKREQ as GPIO and always assert low]
This is a workaround for issue b/35648315 as proposed by Intel to
ensure that WLAN_CLKREQ always stays low.
BUG=b:35648315
Original-Change-Id: I178b3e4fbf74cf08eadfa8bd31b80b018f330e77
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1055652
Original-Reviewed-by: Rajat Jain <rajatja@chromium.org>
Original-Tested-by: Rajat Jain <rajatja@chromium.org>
Change-Id: Ie3458b3fbd1ecadf6b99b9804fb98440cf8d6938
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Adapted from chromium commit cf18ab6
[Strago: mask Audio IRQ on boot]
Do not start with audio interrupt unmasked; this causes interrupt storms
on newer kernels that no longer mask all interrupts when initializing
Cherryview pincontrol driver.
TEST=Boot various cyan boards with kernels 3.18 and 4.14;
verify everything works.
Original-Change-Id: Id621682d3b59fea3ac54fb0ab92c8df9c78a6d43
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894688
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Icb55c885ea661c41168d3bd24109d2cdbb225546
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Adapted from chromium commit 3750e09
[Strago: mark GpioInt() resources as PullDefault]
coreboot considers GPIO resources first-class citizens and initializes
all pads according to their intended use, with necessary pull settings
applied. Therefore let's use PullDefault as pull qualifier in AML,
letting the kernel know that it should not attempt to alter pull settings
when using GPIOs.
TEST=Built and booted on celes, cyan, and egdar; built for other cyan devices.
Original-Change-Id: Iff58a324e73a7eeac9b38df05a095fcfe7acd31b
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/898259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I0c69e77c58b8ceca71bc0c99e16d10c3e539f783
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27760
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adapted from chromium commit 126d352
[Strago: switch Touchpad and Touchscreen interrupts to be level-triggered]
The Elan and other touch controllers found in this device work much
more reliably if used with level-triggered interrupts rather than
edge-triggered.
TEST=Boot several cyan boards, verify that touchpad and touchscreen
work.
Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894689
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Adapted from chromium commit ee7a150
[Strago: do not hardcode virtual interrupt numbers]
Instead of hardcoding virtual interrupt numbers that may change as
the kernel changes, use GpioInt() resources to describe keyboard,
touchpad, and touchscreen interrupt lines.
TEST=Build and boot several cyan variant boards, verify keyboard,
touchpad and touchscreen work with newer kernels (4.14+).
Original-Change-Id: I98d5726f5b8094d639fb40dfca128364f63bb30b
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894687
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Iecfb45be433249d274532eb746588483fedb3f52
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Since this works on Yorp and Bip, we should enable EC SW sync for all
known boards so that it doesn't get forgotten.
BUG=None
TEST=None
Change-Id: Ifee8e0b6620dc7554160a10a8e4663db25b6413d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27755
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code]
and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing
TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver
(drivers/pc80/tpm) must be added to devicetree in order to ensure the
new acpigen code is used to replace it.
Test: boot various google/samsung boards, verify SSDT created with
LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux
Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27786
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds a function to overwrite AC/DC loadlines for differnt
projects.
BUG=b:111761175
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage and use DCI to dump
AC/DC loadline settings. Tested on Vayne and Akali.
Change-Id: Id0068c5334c257b9f4c32b6088becbfe8391a864
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Add lpddr4 skus for new memory sources K4F6E3S4HM-MGCJ and MT53E512M32D2NP-046.
BUG=b:111964159
BRANCH=master
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: Id39a332998b28262e5aa45822078f3c4087f163f
Signed-off-by: nickchen <nickchen@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27747
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This never got enabled for fleex; we should enable this to make it
easier to have updated EC firmware.
With this commit, here's the relevant console messages:
sync_one_ec: devidx=0 select_rw=4
update_ec: Updating RW(active)...
Trying to locate 'ecrw' in CBFS
update_ec: image len = 137580
EFS: EC is verifying updated image...
send_packet: CrosEC result code 1
EFS: EC doesn't support EFS_VERIFY command
vboot_hash_image: No valid hash (status=0 size=0). Compute one...
print_hash: RW(active) hash: 35ba735cf97dd990f6f7f0895264382aa20beb4e7ba57270b0a7b24686e26afd
Trying to locate 'ecrw.hash' in CBFS
sync_one_ec: jumping to EC-RW
send_packet: CrosEC result code 12
EC returned from reboot after 27753us
BUG=b:112038021
TEST=Successful boot after EC update via sync
Change-Id: I2dc97c8e2b07f3bdef0d723789cc12c23b32c135
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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The careena board requires a different setting within VBIOS in order to
pass the eDP eye diagram test. Update all kahlee boards to use the new vBIOS.
CQ-DEPEND=CL:1153080
BUG=b:111673328
TEST=Verify, via SOME unspecified method, that the new vBIOS is built into
the Grunt/Careena ROM files.
Change-Id: I268cd3dbce6ba1f7bd781d768f470463846a4e10
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27643
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ibb13627bcd2ad023f7686b5ae0bd7331e09cf5b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: If4d6c80e95469341f0c978f302f04508f50280bd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: Ie95d9c04375e0125bae9bc01ae5caef423faf33e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
The careena board needs different video settings to pass eye diagram test,
which does not affect negatively the grunt board. In preparation for new
VBIOS, AGESA environment needs eDP high vdiff enabled.
BUG=b:111673328
TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and
boot grunt. Add new code to grunt, build and boot, verify eDP changed.
Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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- add Nanya NT6CL256T32CM-H1 to memory strapping table
BUG=b:111906760
BRANCH=none
TEST=none
Change-Id: I1432b9ab84f01a7fee1bc562aa40c714ddbf639e
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Caveh Jalali <caveh@google.com>
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This change primarily moves the PowerResource up to a more common scope so
that the _PRx references are simpler. The ^ scope modifier isn't well
supported everywhere amongst OSes and drivers. Windows 10 will BSOD
early during boot with ACPI_BIOS_ERROR (code 0x6, which means it could
not find the object referenced by a _PRx) with the way things are currently
laid out).
I've also not seen a firmware outside of coreboot that tries to reference
count _ON and _OFF. Isn't it up to the OS to deference count, and whatever
it tells ACPI is what should happen (i.e., on means on and off means off)?
Some of the _UIDs are also duplicated. This change makes them unique.
A few cosmetic changes are made so that diffing cam0.asl against
cam1.asl has fewer extraneous differences.
Change-Id: I9c9f6c712b075450539d5b84ac5bb221b3cbb57e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
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Adapted from chromium commit 7633daa
[caroline: Change debounce time for jack insertion and ejection]
We are using max debounce time. During this time line, MICBIAS will be
zero because of jack chasis. At the moment we got 0 button (PLAY/PAUSE)
We need to reduce this time to below 100ms for caroline device.
BUG=b:79559096
TEST=see there is no more irq before jack insertion/ejection irq
complete
Original-Change-Id: Ib6abdb4ff041823ca89f74cf59e2bfa644bb0d6a
Original-Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1143109
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wonjoon Lee <woojoo.lee@samsung.com>
Change-Id: I8f605989d6ffc8a75127ed6722e7a37db95029ed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27659
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On kukui board, the eMMC is routed to EC for boot ROM emulation when
loading bootblock, and should be set back to real eMMC as early as
possible after bootblock is loaded.
BUG=b:80501386
TEST=make; boots and verified BOOTBLOCK_EN_L GPIO is enabled.
BRANCH=None
Change-Id: Ifefb2e26ed048c38595907cc0875757410129828
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/27601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable power to FPMCU by default on power-on and deassert
the PCH_FPMCU_RST_ODL reset line.
BUG=b:111880258
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel
prompt, wait a few seconds, press power button to wake, then execute
"cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes
up empty.
Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27658
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable nocturne to wake from lid attach/detach events.
BUG=b:111803637
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", verify EC has
commit a5abbbb4eb9b15a72624dddbfd727d0b324c3f36, and verify nocturne
wakes from suspend on a lid attach/detach event.
Change-Id: I22b957d741426ca8b49d1819cf39c940f55198eb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27649
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some fields were only required during early stages of IPU3.
Remove some fields that aren't used for the current version of IPU3.
BUG:None
TEST=Launch camera app and check if it works properly.
Change-Id: I72bcba13cc353a1b16fedeb7543fbbac432fbf5d
Signed-off-by: Alan Chiang <alanx.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/27617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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terminations
For unused pins, configure them as GPIO input and use the default
termination. For the pins where board has an external termination,
remove SOC's internal termintation.
BUG=b:110654510
TEST=On Bip, flashed image and verified that it boots to OS. Also
executed a few suspend resume cycles.
Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/27634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Currently, default GPP_D21(LTE3_BODY_SAR) output level is low, it means
LTE tx power is backoff mode as default.
We would set GPP_D21 to high to change LTE tx power to normal mode as
default.
BUG=None
BRANCH=poppy
TEST=Verified default LTE tx power mode is normal mode as default
Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27661
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the new setting for fan performance state.
BUG=b:111860513, b:11865138
TEST=Fan do not run below trip point
Change-Id: I894460b8b418217e2477608094c37018437cbb78
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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All of the other SPDs are padded with spaces to make them use the full
size of the serial number field. The hynix-H5AN8G6NCJR-VKC SPD was not,
and that seems to be causing problems with some tools.
BUG=b:111903749
TEST=Mosys correctly identifies memory on board using that SPD.
Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
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A variant might talk to the EC to get board id in order to identify the
right GPIO configuration. Thus it is important to ensure that the LPC IO
windows are configured before this. This change moves the call to
perform EC init before configuring bootblock GPIOs.
BUG=b:111933657
TEST=Verified that reading board id does not fail on phaser.
Change-Id: Ic23c6fd7597a314e0b6421be39ccc0b1dfb46567
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27671
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix Micron MT40A512M16LY-075:E DRAM SPD CRC error in AGESA MemSPDChecking:
ERROR Event: 04011200 Data: 0, 0, 0, 0
BUG=b:111901461
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I85c82fd9294f9146fc23e649436cbcc337c4c961
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27657
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch sets SPI flash related configs and inits SPI bus 1 to
support SPI NOR flash.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I1a18a456f41a7c7daec954e961c9fbee3650493d
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add audio codec definitions in devicetree, which were accidentally
dropped when upstreaming
Test: build/boot Caroline with GalliumOS 3.0a2, verify working audio.
Change-Id: I707b93c83f773cde2108b75ec550a15e5566d974
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27626
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove duplicate FMCN package for I2C2, since already generated by
the devicetree-linked generic i2c driver. This fixes an ACPI parsing
error which resulted in the touchpad and touchscreen being non-functional.
Test: build/boot Caroline with GalliumOS 3.0a2, verify touchpad and
touchscreen functioning properly, no ACPI errors in dmesg.
Change-Id: I68315daf087aef0fc51411605b054e6322d5d7f8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This change provides override GPIO table for variant phaser depending
upon the board id. Additionally, early_gpio_table is also provided for
phaser since EN_PP3300_WLAN needs to be handled differently based on
board id.
BUG=b:111743717
TEST=Verified that GPIO configuration for the override GPIOs is
different than before with this change.
Change-Id: I4d2e829e1b886299442c17cecc069854b742b43c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change updates mainboard_init to call
gpio_configure_pads_with_override instead of gpio_configure_pads to
allow variants to provide overrides for the GPIO config table provided
by the baseboard.
BUG=b:111743717
TEST=Verified on phaser that GPIO config with and without this change
is the same.
Change-Id: I494a950100e5ec82504d652ff6e8a75746456d1f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The next build for phaser swapped the gpio for the touchscreen
enable. In order to support previous builds the devicetree needs
to be updated at runtime based on board revision id.
BUG=b:111808427,b:111743717
TEST=built
Change-Id: I45ef05ea0b991d04d5bf410cd7a175913bf0bf5d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27638
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The variants of the octopus family have their own schedule and needs
for modifying settings based on the phase of the build schedule while
also needing to maintain support for previous builds. Therefore, utilize
the SoC callback, mainboard_devtree_update(), but just callback into
the newly introduced variant_update_devtree(). The indirection allows
for the ability to move the call around earlier than the
mainboard_devtree_update() if needed while maintaining consistency in
the naming of the variant API.
BUG=b:111808427,b:111743717
TEST=built
Change-Id: If1c2f60cabe65b5f1c6a04dd60e056e50c4993df
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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The variant_board_id() API was never used on octopus because all
boards in the octopus family used the EC to get board id, i.e. they
all use EC_GOOGLE_CHROMEEC_BOARDID. Therefore, remove the code
and declarations so as not to cause confusion.
BUG=b:111808427,b:111743717
TEST=built
Change-Id: I4f9a24b46dd4262120075d3d42daf22015a3dd50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.
A fully functional bootblock (that can boot into verstage or romstage)
is about 38000 bytes. If self decompression (CONFIG_COMPRESS_BOOTBLOCK)
is enabled, only 25088 (66%) bytes are needed.
Inspired from crosreview.com/1070018.
BUG=b:80501386
TEST=manually flashed into kukui and boots into romstage.
Change-Id: I7a739866a4ea3bcafe2ff7b9e88d5ed00f3f3e40
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/27599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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These values are Intel recommended.
IccMax = 28A
DC and AC LL = 4mOhms
Pl2 = 18w
BUG=b:79666828
BRANCH=none
TEST=Enabled p-states with patch
Change-Id:I82d1516998cc26b789faa5d4e897feb06dc06020 and then
"emerge-nocturne depthcharge coreboot chromeos-bootimage", flash spi
image onto nocturne, boot to kernel and verify device stays alive and
responsive for several minutes without locking up.
Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27175
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables p-states for nocturne which was disabled by commit
de31587a (mb/google/poppy/variants/nocturne: disable p-states). p-states
feature was disabled as a temporary work-around as system was getting
hung while booting up. Now with IMVP7 firmwware turning and hardware
rework the issue is not seen, so its safe to enable p-states.
BUG=b:79666828
BRANCH=none
TEST=cherry picked Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d
patch and then "emerge-nocturne depthcharge coreboot chromeos-bootimage"
, flash spi image onto nocturne, boot to kernel and verify device stays
alive and responsive for several minutes without locking up.
Change-Id: I82d1516998cc26b789faa5d4e897feb06dc06020
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27257
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For unused pins in octopus baseboard, configure them as GPIO input
and use the default termination. For the pins where board has an
external termination, remove SOC's internal termintation.
BUG=b:110654510
Change-Id: I67ec62913b0ef47105289838218f5d74c004223c
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/27183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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As per the ACPI specification, there are two types of power button
devices:
1. Fixed hardware power button
2. Generic hardware power button
Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
is not set in FADT by the BIOS. This device has its programming model
in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
power button device by default if the power button FADT flag is not
set.
On the other hand, generic hardware power button can be used by
platforms if fixed register space cannot be used for the power button
device. In order to support this, power button device object with HID
PNP0C0C is expected to be added to ACPI tables. Additionally,
POWER_BUTTON flag should be set to indicate the presence of control
method for power button.
Chrome EC mainboards implemented the generic hardware power button in
a broken manner i.e. power button object with HID PNP0C0C is added to
ACPI however none of the boards set POWER_BUTTON flag in FADT. This
results in Linux kernel adding both fixed hardware power button as
well as generic hardware power button to the list of devices present
on the system. Though this is mostly harmless, it is logically
incorrect and can confuse any userspace utilities scanning the ACPI
devices.
This change gets rid of the generic hardware power button from all
google mainboards and relies completely on the fixed hardware power
button.
BUG=b:110913245
TEST=Verified that fixed hardware power button still works correctly
on nautilus.
Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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