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2022-05-16google/cyan: Clean up write_protect_state()Kyösti Mälkki
The commentary was wrong, write_protect_state() is only called in ramstage at the moment, and only if MRC_SETTINGS_PROTECT is selected. Implementation of get_gpio() eventually does the MMIO read, so BOARD_GOOGLE_CYAN was not a special case. Change-Id: I96ca871110bcf2fc1485bd042ed137d51b822a20 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16mb/google/brya: Consistently put void before __weak attributeTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic59cccdf0fb88fc71a440170ee40b73dd8736a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16mb/google/nissa/var/nivviks: Disable PCIe WLAN pinsReka Norman
Nivviks uses CNVi WLAN, so disable the PCIe-related GPIOs. BUG=b:218929856 TEST=Boot to OS on nivviks and check that WLAN still works. Change-Id: I68f12490b0f09658e1307828b0e4488504f50e61 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/nissa/var/nivviks: Add support for NVMe and UFSReka Norman
Enable either eMMC, NVMe or UFS based on fw_config. NVMe and UFS are only supported on nirwen, an additional nissa variant based on nivviks and sharing the nivviks coreboot target. BUG=b:218929856 TEST=Boot to OS on nivviks to check that eMMC still works. NVMe and UFS will be tested once nirwen boards are available. Change-Id: Ibdb122ef35920c962d7bd9f3f238a5d548112282 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/nissa/var/nivviks: Update GPIOs to support nirwenReka Norman
Nirwen is an additional nissa reference board which is almost identical to nivviks, so is reusing the nivviks coreboot variant. However, there are two GPIO changes, so update the GPIO tables to handle these based on board_id. nivviks: GPP_D6 -> WWAN_EN GPP_E13 -> NC nirwen: GPP_D6 -> SSD_CLKREQ_ODL GPP_E13 -> WWAN_EN BUG=b:218929856 TEST=Boot to OS on nivviks Change-Id: I494ed127714069a8f36d16d11ca4e8a1f3d37827 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/nissa/var/nivviks: Disable pen garage based on fw_configReka Norman
BUG=b:218929856 TEST=Boot to OS on nivviks. Set fw_config in CBI and check that pen garage is enabled/disabled as expected. Change-Id: I2c3f5403e0f11443ad3647b8c4ae624f0b88a111 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/nissa/var/nivviks: Disable MIPI WFC based on fw_configReka Norman
BUG=b:218929856 TEST=Boot to OS on nivviks. Change fw_config in CBI and check that WFC is enabled/disabled as expected. Change-Id: Iac4bb358d904579376e0810f8c2644b3bde4f1e6 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16mb/google/brya: Remove Rcomp resistors override for NissaUsha P
This patch sets the RComp resistor values to default values needed. BUG=b:231202733 TEST=Build and boot nivviks and nereid. Verify the Rcomp values are set to default values from debug FSP log. [SPEW ] Updating Rcomp Targets: [SPEW ] RcompTarget[RdOdt]: 48 [SPEW ] RcompTarget[WrDS]: 30 [SPEW ] RcompTarget[WrDSCmd]: 20 [SPEW ] RcompTarget[WrDSCtl]: 20 [SPEW ] RcompTarget[WrDSClk]: 20 Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I2c7a54c49e282446ece77ca406951782282a009a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16mb/google/brya/var/crota: Enable DRIVERS_GENESYSLOGIC_GL9750Terry Chen
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Crota. BUG=b:231686917 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ie10167e48256a61801b2623ae4500db5e67e73cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/64255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-16mb/google/crota: Change ELAN touchscreen i2c address and HIDTerry Chen
Change ELAN touchscreen i2c address to 0x16 and change HID to ELAN900C BUG=b:231684121 TEST=local build and tested with ELAN touch screen Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ide005a0681e236c3102090c1c36ab81926849000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-16mb/google/nissa/var/nivviks: Disable SD card based on fw_configReka Norman
BUG=b:218929856 TEST=Boot to OS on nivviks. Change fw_config in CBI and check that SD card is enabled/disabled as expected. Change-Id: Idcf38343bb290b1eff6a2e440f868b03acba3288 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-16drivers/i2c/tpm: Work around missing firmware_version in Ti50 < 0.0.15Reka Norman
Ti50 firmware versions below 0.0.15 don't support the firmware_version register and trying to access it causes I2C errors. Some nissa boards are still using Ti50 0.0.12, so add a workaround Kconfig to skip reading the firmware version and select it for nissa. The firmware version is only read to print it to the console, so it's fine to skip this. This workaround will be removed once all ODM stocks are updated to 0.0.15 or higher. A similar workaround Kconfig was added in CB:63011 then removed in CB:63158 which added support for separate handling of Cr50 and Ti50. But we actually still need this workaround until all Ti50 stocks are upgraded to 0.0.15 or higher. BUG=b:224650720 TEST=Boot to OS on nereid with Ti50 0.0.14 Change-Id: Ia30d44ac231c42eba3ffb1cb1e6d83bb6593f926 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-05-16mb/google/nissa/var/nivviks: Use interrupt with lock for pen detect GPIOEric Lai
With GPIO_DRIVER_LOCK kernel driver can't change to IRQ. Thus, we need to set it as INT in coreboot to make the IRQ work. BUG=b:223476974 TEST=evtest work as expected. Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 0 Properties: Testing ... (interrupt to exit) Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: -------------- SYN_REPORT ------------ Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I5f9fdfb2622b4b955da216119e74c6f7d5795d36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-05-16mb/{google,ocp}: Remove unused <bootstate.h>Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id4550842a31f89e7eb6c1543512794eeb5e24937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16mb/google/stout: Use pci_update_config32()Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie1d2965b384e5653958f7f8503c62b8a16fa7bc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-14mb/google/eldrid: Fix use of floatArthur Heymans
Floats are not allowed in coreboot. As the compiler rounded down the value, do so in the code too as this is a known good value. Change-Id: I4e180d4cb8e0e1aa68186bfc1daffdc5c339dc64 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-13mb/google/brya/variants/osiris: Init devicetree for osirisDavid Wu
Init basic override devicetree based on schematics BUG=b:224423318 TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie69957b39b5c299846c64f67fb29207cf858e50e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64199 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13mb/google/brya/variants/osiris: Configure GPIOs according to schematicsDavid Wu
Update initial gpio configuration for osiris BUG=b:224423318 TEST=FW_NAME=osiris emerge-brya coreboot Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I014bd7ebf94bf687362f7ee734cadfa83f3bde2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-05-13mb/google/glados: Fix unused variableArthur Heymans
Commit f89cb241eec introduced a regression where the RcompTarget was not updated according to the SPD. Change-Id: I07715224b11937604b107e370d957745b245ddd9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64239 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12mb/google/skyrim: allow MKBP devices and disable TBMC deviceIan Feng
Enable MKBP (Matrix Keyboard Protocol) interface for all skyrim family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:230682161 TEST=manual test on Skyrim: Volume Up/Down and Power buttons, Tablet Mode switch Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I79ee2fdbb325491c9e3df5b9cff0c0c1181a7001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-05-12mb/google/deltaur: Remove mainboard from treeTim Wawrzynczak
This board never made it to production, and development on it has long since stopped; it is a maintenance burden, therefore drop it from the tree. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ieb12a95ff56c3437cb88df8ef3f6ae115ad53446 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-12mb/google/corsola: Enable TPM_GOOGLE_TI50Yu-Ping Wu
Replace TPM_GOOGLE_CR50 with TPM_GOOGLE_TI50. BUG=b:232066387 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I0cc787b3104bc47f6f856497bbc0870e0519dc28 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64252 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12mb/google/skyrim/var/skyrim: Add USB WWAN configurationKarthikeyan Ramasubramanian
Add Fibcom FM101-GL USB WWAN configuration with the required power sequence as suggested in Fibocom FM101-GL Hardware Guide V1.0. BUG=b:227761300 TEST=Build and boot to OS in Skyrim. Ensure that the WWAN module is enumerated in the output of lsusb. localhost ~ # lsusb Bus 004 Device 003: ID 2cb7:01a2 Fibocom Wireless Inc. Fibocom FM101-GL Module Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I39f8e7204e31d9a4d093aacd838a18e6d2f44970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64004 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12mb/google/skyrim/var/skyrim: Add VL822 USB hubKarthikeyan Ramasubramanian
In Skyrim, USB-A port and WWAN modules are connected to the SoC USB ports through an external hub. Update the USB configuration in the devicetree accordingly. Enable the ACPI driver for external USB hub. BUG=b:227761300 TEST=Build and boot to OS in Skyrim. Ensure that the hub and USB-A ports are enumerated correctly in the output of lusub command. Change-Id: Ibf6a3da8add7361fc50adcf7c62e46df234685dc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63586 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12mb/google/brask/variants/moli: Set GPP_E14 as the default value.Raihow Shi
We found HDMI-DDIA didn't get hot plug detection,so set GPP_E14 as the default value to let HDMI-DDIA get hot plug detection. BUG=b:231769129 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I1b5cc1465fec519be4bbe5e027be0dc25815f4fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/64138 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-12mb/google/nissa/var/craask: Add supported touchpadTyler Wang
Add related settings for synaptics touchpad. BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3b3bb5cec56901dadaaa1c5699781df45c237257 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-12mb/google/brya/var/agah: Enable PCIe RP 3 for LANTony Huang
Using CLKREQ 4 and CLKSRC 4 BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: Ie0e362013551036a03ef69a98c6f1793e0e75c41 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-11mb/google/brya/var/crota: enable wifi sarScott Chao
BUG=b:216594621 BRANCH=brya TEST=build pass and SAR table be changed according to tablet/ desktop mode Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I62265e8931da48d20cf41e0c91ccb1a5b4bc1167 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-11mb/google/brya/var/kinox: Disable thunderbolt interfaceDtrain Hsu
Disable all of the TBT devices in devicetree since kinox doesn't support thunderbolt. The change also need to disable TBT in fitimage (chrome-internal:4731094). BUG=b:231654363 TEST=Build and run on DUT. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I944680dd1f41ac6f375015a3a138eb00c41b58a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-11mb/google/brask/variants/moli: correct tcss_usb3 portCasper Chang
Correct tcss_usb3_port to meet Moli's schematic design. BUG=b:220814038 TEST=emerge-brask coreboot Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ib8faa4a353d8d617fce7aa70922bf027e6e11b38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-06mb/google/brask/variants/moli: enable BT offloadCasper Chang
Enable BT offload of NAU88L25B on Moli with fw_config NAU88L25B_I2S. BUG=b:220814038 TEST=emerge-brask coreboot, Check BT offload enabled in CPU log and audio works. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I72d91d2dafffa7d9604b7dd3d697cb3b2b04b152 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-06mb/google/brya/var/crota: Fix codec reset pin in overridetreeTerry Chen
Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the reset pin to be deasserted in ramstage for proper power sequencing. BUG=b:230074351 BRANCH=none TEST=build coreboot without error Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-06mb/google/brask/variants/moli: disable ASPM on pcie_rp 6Raihow Shi
Currently coreboot will hang on ASPM on pcie_rp 6, so disable ASPM to let it go into kernel. BUG=b:231400217 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: I79a80d97d168f40e58774e5652967d659daa323c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-06mb/google/brya/variants/crota: Enable Bluetooth offload supportTerry Chen
Enable CnviBtAudioOffload UPD from Intel Guideline BUG=b:230418589 TEST=emerge-byra coreboot and verified pass Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I7ac54156cc4a8d824ed1c549d66fc369698a352c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-05soc/intel/tigerlake: Add enum for `DdiPortXConfig`Angel Pons
Add an enum for `DdiPortXConfig` devicetree options. Note that setting these options to zero does not disable the corresponding DDI port, but instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is connected to it. Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2022-05-05mb/google/brya/var/vell: Remove unused i2c7 settingsGaggery Tsai
This patch removes unused i2c7 settings. Accroding to EVT schematic, i2c7 is reserved for AMP but resistors are unstuffing. BUG=b:229334701 TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend && checks EC log and ensures the DUT could enter s0ix. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: Ifc1e0085064a13149ebc7e70184d1f40462e0fff Reviewed-on: https://review.coreboot.org/c/coreboot/+/63892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-05mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SARTeddy Shih
To meet LTE's RF Specific Absorption Rate (SAR) certification, we add a Semtech Smart Proximity Sensor (P-Sensor) SX9324. P-Sensor connects EC of I2C 5 bus and GPIO D22, D23, as well as, SoC of GPIO E11, refer to mainboard schematic. BUG=b:213549229 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: If172d13aa62503547227adf91f049ea50b948888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63652 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-05mb/google/brya/var/agah: Add GPU power sequencingTim Wawrzynczak
This patch adds support for power sequencing of the Nvidia GN3050 for agah, which uses PCH GPIOs to control the 5 power rails required for the GPU. The GPU is power sequenced on during mainboard initialization, then it is enumerated on the PCI bus and its resources are assigned. This GPU will be used in a sort of "hybrid graphics" mode, therefore during finalization, since its PCI BARs are saved into ACPI memory and the GPU is not required upon initial boot, the GPU is power sequenced off. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-05-05mb/google/brya/var/crota: setting for codec reset pinTerry Chen
Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the reset pin to be deasserted in ramstage for proper power sequencing. BUG=b:230074351 BRANCH=none TEST=build coreboot without error Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-05mb/google/skyrim: Fix SD card power sequenceIan Feng
Fix power sequence according to datasheet:GL9750S-OIY04 rev1.24. BUG=b:229181624 TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller and SD Card are enumerated fine. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: Iea729d43d10a3f8353b4fe540146d00975f4d422 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-04mb/google/brya/var/taeko{4es}: Remove extraneous __weak attributesTim Wawrzynczak
Functions that are intended to override weak ones defined in the baseboard should not also be declared weak, otherwise how would the linker know which copy to keep. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia2ceee77d00a5baa915fd1f306d76e79aa609e65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-04mb/google/brya/var/crota: Enable webcam powerTerry Chen
Based on the schematic bernadino 14 adl-p 20220318.pdf to set GPP_D16 to enable webcam power BUG=b:230289857 BRANCH=none TEST=build and notice log kernel v5.10 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I01c73006d24b00be348655334232bea5eeb312e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-04mb/google/brya: Add EC mux device to brya0Prashant Malani
Add entries to the devicetree override for brya0 and enable the Kconfig to ensure the Chrome OS EC Mux driver is build tested. BUG=b:208883648 TEST=None BRANCH=None Change-Id: Icf841cd32587f6bd98b15747283b0d331f013532 Signed-off-by: Prashant Malani <pmalani@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-02mb/google/brya/var/kinox: Update power control settings for 15W SOCDtrain Hsu
Kinox keeps 65W barrel jack for Intel Pentium/Celeron SOC. Considering the dynamic loading of 65W adapter, it can up to 130% with 20ms. Update power settings to below for preventing blowing out the adapter. - Psys_Pmax 135W - PL2 39W - PL4 72.5W - Psys_PL2 65W - Psys_imax_ma 6750ma - bj_volts_mv 20000mv For Intel Core processor, Kinox will use 90W barrel jack. Modify default power settings as below. - Psys_Pmax 135W - PL2 55W - PL4 123W - Psys_PL2 90W - Psys_imax_ma 6750ma - bj_volts_mv 20000mv BUG=b:213417026, b:222599762 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I6df2a17969067f8242519f7fd4ffd08a682fe3e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hou-hsun Lee <hou-hsun.lee@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-05-02mb/google/brya/var/osiris: Enable EC keyboard backlightDavid Wu
Enable EC keyboard backlight for osiris. BUG=b:224423318 TEST=FW_NAME=osiris emerge-brya coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I501155531bff8c59641e88ea61aab623cb9a1868 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-04-29mb/google/brya/var/agah: Change Aux settings to TCSS port 2Tony Huang
Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2. Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port. BUG=b:210970640 BRANCH=NONE TEST=emerge-draco coreboot chromeos-bootimage Change-Id: I2d26777e850187aee0b676de13dff915474fed7b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-28mb/google/{octopus,reef}: add RO_VPD region to default FMAPMatt DeVillier
This allows for the option to persist the serial number and other device-specific information when switching from stock ChromeOS and upstream coreboot firmware images. Change-Id: I12711f678259390fe9e31b7ca728344cc2875b0e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-28mb/google/brya/var/crota: fix Goodix touchpadTerry Chen
- Fix Goodix hid and hid offset BUG=b:230415144 BRANCH=brya TEST=build and boot without error Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I5a5c1cdca0cec15d65fe62a3104652d2d347fd54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-28mb/google/brya: disable early EC sync for nereidPeter Marheine
The ITE EC used on Nereid can take a long time to update, and especially too long to erase. There is a 1 second timeout enforced on the EC erase command, but Nereid's IT81302 will typically take about 5 seconds to complete erase, and could take as long as 30. Since this affects any Nissa variant using an ITE EC and it's nice to make the entire Nissa project consistent, this change disables early sync for all Nissa boards. BUG=b:222987250 TEST=EC software sync is no longer attempted (and thus does not fail) on Nereid. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I55d36479e680c34a8bff65776e7e295e94291342 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2022-04-27mb/google/brya/var/banshee: Update the FIVR configurationsFrank Wu
This patch enables V1p05 and Vnn external bypass VRs for Banshee. BUG=b:207116793 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Idb56890db40f90f163d8dadf5bf7c7335469771a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63860 Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27mb/google/brya/var/vell: Enable TBT PCIe root port 3Gaggery Tsai
This patch enables TBT PCIe root port 3. BUG=b:230464233 TEST=emerge-brya coreboot chromeos-bootimage and $lspci -t and ensure 07.3 is in the list. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I118facd45f54c8ed2843a85c0aa61b6571077a5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-27mb/google/dedede/beadrix: Update DPTF settingTeddy Shih
Update DPTF Policy and temperature sensor values from thermal team. BRANCH=dedede BUG=b:204229229 TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot. Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I34c1298dc8412121f8688842bb8d69d7fafa46f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivan Chen <yulunchen@google.com> Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-27soc/intel/jasperlake: Revert CdClock settingSimon Yang
Revert CdClock setting and use default value 0xff. Previous problem was fixed by Jasperlake FSP in version 1.3.09.31, so we can use the original CdClock setting in baseboard. BUG=b:206557434 BRANCH=dedede TEST="Built and verified on magolor platform to confirm FSP solution works" Cq-Depend: chrome-internal:4662167 Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-27mb/google/octopus/Kconfig: Remove space saving optionsArthur Heymans
Commit 28e61f1634 "device: Use __pci_0_00_0_config in config_of_soc()" significantly reduced the size of the bootblock. This makes the space saving options, required to make to bootblock fit in the 32K SOC limit, unnecessary. TESTED: with configs/config.google_octopus_spi_flash_console the .text size is 0x29c8 bytes which is still well below the 0x8000 SOC limit. Change-Id: I208211d30cc2805113a16a02cdab957b8c584c92 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-27mb/google/corsola: Add RO_GSCVD area to FMAPYu-Ping Wu
This area is used for storing AP RO verification data. BUG=b:229670703 TEST=emerge-corsola coreboot TEST=cbfstool /build/corsola/firmware/kingler/coreboot.rom layout BRANCH=none Change-Id: Id0a3304920c80987319d8072b8e443c41c1f1c47 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2022-04-27mb/google/nissa/var/craask Add device settingsTyler Wang
Add the configuration in device tree: 1. Add speaker codec and speaker amp settings 2. Add Elan touchscreen settings 3. Add WFC and usb settings 4 Add Elan Touchpad settings 5. Add WiFi configuration 6. Add LTE settings BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iabf7f864082714ef1fecdee984fbebf1f3f0a672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-27mb/google/brya/var/craask: Add GPIO tableTyler Wang
Fill GPIO table for Craask. BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I3b85b4b7a68211013f5862d71c8e31ecec41c7b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-27mb/google/brya/var/craask: Generate SPD ID for supported memory partTyler Wang
Add supported memory parts in mem_parts_used.txt, and generate SPD id for this part. MT62F1G32D4DR-031 WT:B MT62F512M32D2DR-031 WT:B BUG=b:229938024 TEST=emerge-nissa coreboot Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I183b74e66786c378cc227ee1e53ea422986b672a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-04-27soc/intel/adl/chip.h: Rename max_dram_speed to include unitsScott Chao
The unit of dram speed is MT/s so append it on variable name. BUG=b:229549930 BRANCH=none TEST=build coreboot without error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I83c780440613050c0202f95d5f64991b61d9c280 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-27mb/google/brya/var/crota: update gpio configurationScott Chao
- enable CPU PCIe VGPIO for PEG60 - enable GPP_C3/ GPP_C4 native function - set unused GPIO to NC BUG=b:229584785 BRANCH=none TEST=build and boot into kernel v5.10 Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I5d4ef92623ce6b0a36e6df23b232b35b498ce964 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-27mb/google/brya/var/crota: enable boot from SSD/ eMMCScott Chao
- Fix eMMC reset/ enable GPIO pins. - Fix clk_req and clk_src BUG=b:229437061 BRANCH=none TEST=build and boot without error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: Id16e292ec7557d1780516a267bd752014d98e463 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-27mb/google/brya/var/crota: Limit dram speed to 4800 MT/sScott Chao
When using LPDDR5 on a Type-C PCB, the Intel ADL-P PDG (Rev. 2.0.1) page 121 recommends a maximum DRAM speed of 4800 MT/s. BUG=b:229549930 BRANCH=none TEST=build and pass memory training Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I38f0006d478702afb382d30338f20b46641964ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/63682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-27mb/google/brya/var/crota: modify DQ/ DQS tableScott Chao
BUG=b:229547171 BRANCH=none TEST=pass memory training with error Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: If6acf8cb9474f816374743fd1e800da46958993d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-27mb/google/brya/var/vell: Fix camera LED flicker problemShon Wang
Camera LED flicker 3 times or so as sensor is being probed during kernel boot. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot preventing camera LED flicker. Corrects that by explicitly sequencing the reset GPIO and power GPIO BUG=b:219644184 TEST=Build and boot on vell, observe whether camera LED flickers Change-Id: I846ec4cb5c4527f5664699b31d0d561d390d938c Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63441 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27mb/google/skyrim: Configure SD_AUX_RESET_L signalIan Feng
Set native function (SD_AUX_RESET_L), and drive it high. BUG=b:229181624 TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller and SD Card are enumerated fine. 02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01) Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-27mb/google/skyrim: Include smm handlerRaul E Rangel
We need to include the SMM handler to enable SCI events when ACPI is enabled. With this enabled we now see we have EC timeout problems while in SMI: [SPEW ] SMI# #1 [WARN ] SMIx88 => 0x800 [DEBUG] Chrome EC: Set SMI mask to 0x0000000000000000 [DEBUG] Chrome EC: UHEPI supported [ERROR] Timeout waiting for EC QUERY_EVENT! [DEBUG] Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected. [ERROR] EC returned error result code 1 [DEBUG] Chrome EC: Set SCI mask to 0x00000000186601fb We still need to debug that. I suspect we have problems reading from the ACPI IO decodes 0x62 or 0x66. BUG=none TEST=Verify SMI handler runs Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ida0fcd634e620274e124a8669836f3974e0a2bf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-04-27mb/google/skyrim: Fix eSPI configurationJon Murphy
* Use GPE 24 since it doesn't conflict with any existing GEVENTS. * Remove IRQ 12 mapping since it's not used. * Unmask IRQ1 in PM registers. * Use the new SMITYPE_ESPI_SCI_B SCI. BUG=b:227282870 TEST=Build and boot to OS in Skyrim. Signed-off-by: Jon Murphy <jpmurphy@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7e9816d67500365ed1d2ee39ef184a1f60321ca1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-25mb/google/zork: Correct PIRQ_MISC0 configurationRaul E Rangel
The current configuration is masking off IRQ 1 and IRQ 12 to the PIC. This for some reason causes problems when using level triggered interrupts. This change updates the PIRQ_MISC0 value to match what skyrim is doing. This will enable level interrupts to work correctly. BUG=b:218874489, b:160595155 TEST=Boot zork and verify keyboard still works. Boot with patch train and verify keyboard works as expected. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I46b1fd68915c6f7aa4c34cdba57d24425752bc38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-25mb/google/skyrim: Prepare for enabling PSP verstageKarthikeyan Ramasubramanian
Add various verstage init functions to prepare for enable PSP verstage. BUG=None TEST=Build Skyrim BIOS image with PSP verstage enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0d0dba05d4d083e2c6860078676e59cf8f487c87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-24mb/google/poppy: Convert 'If (LGreater(STA,0))' to 'If (STA > 0)'Elyes HAOUAS
Change-Id: I088e514271b785e59907b0271eb89727ae1e7c05 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24mb/google/brya: Create mithrax variantJohn Su
Create the mithrax variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:223091246 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_MITHRAX Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I7c2fa6a74cc8e37397dea7e67e8cfa6506a49bdb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-24tpm: Allow separate handling of Google Ti50 TPMJes Klinke
A new iteration of Google's TPM implementation will advertize a new DID:VID, but otherwise follow the same protocol as the earlier design. This change makes use of Kconfigs TPM_GOOGLE_CR50 and TPM_GOOGLE_TI50 to be able to take slightly different code paths, when e.g. evaluating whether TPM firmware is new enough to support certain features. Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986 Signed-off-by: Jes B. Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-24mainboard/google: Remove unused <boardid.h>Elyes Haouas
Found using: diff <(git grep -l '#include <boardid.h>' -- src/) <(git grep -l 'UNDEFINED_STRAPPING_ID\|BOARD_ID_UNKNOWN\|BOARD_ID_INIT\|board_id(\|ram_code(\|sku_id(' -- src/) |grep "<" Change-Id: I2611be41e8730a9b189b1b0aa3fe62be0757b371 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-22mb/google/brya/var/taniks: Configure Acoustic noise mitigationleo.chou
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:227165770 TEST=build FW and system power on. Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I262ef14032e0e412c63403dbb8c8fbc6a8b03dd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-22mb/google/brya/var/taniks: Add WiFi SAR table for taniksleo.chou
Add WiFi SAR table for taniks. BUG=b:226690925 TEST=build FW and checked SAR table can load by WiFi driver. Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I7b52f71b1fe49c02beaa48410495b81661b58fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/63684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-21mb/google/dewatt: Set SPI speed to 100Mhz on board version 3Rob Barnes
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=b:213403891 BRANCH=guybrush TEST=Build and boot to OS in Dewatt board version 3. Change-Id: If0318abf1fed9b1f4ba876f736fdbf92c1ea6933 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63747 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21mb/google/dedede/var/kracko: Add FW_CONFIG probe for EXT_VRRobert Chen
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on kracko. BUG=b:223687184 TEST=emerge-dedede coreboot Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: Ib12265591e679e6b9ed34299f1256db05147eaef Reviewed-on: https://review.coreboot.org/c/coreboot/+/63111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/dedede/var/drawcia: Add FW_CONFIG probe for EXT_VRRobert Chen
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on drawcia. BUG=b:223687184 TEST=emerge-dedede coreboot Change-Id: I683049e9d2b10fc9455ef782ce798f1c453073bc Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/dedede/var/lantis: Add FW_CONFIG probe for EXT_VRRobert Chen
Add FW_CONFIG probe for absent ANPEC APW8738BQBI IC on lantis. BUG=b:223687184 TEST=emerge-dedede coreboot Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Change-Id: I3d8eec1d2f962d42f3be225eef8498e8b722aace Reviewed-on: https://review.coreboot.org/c/coreboot/+/63112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/nipperkin: Fix WLAN to GEN2 speedRob Barnes
Fix WLAN PCIE speed to GEN2. Dynamic switching between speeds is causing the PSP to hang when resuming from S0ix suspend. The root cause is still under investigation. Just disabling PSPP fixes the hang but causes poor PLT performance. BUG=b:228830362 BRANCH=guybrush TEST=suspend_stress_test on AC and DC Change-Id: I988365e51aca0d6515c5605b3032521cf59d8d30 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63722 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21mb/google/brask/variants/moli: update overridetreeRaihow Shi
Add FW_CONFIG STORAGE and probe for UNKNOWN, NVME and eMMC. BUG=b:220039297 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2022-04-21mb/google/brya/var/taeko: Add WIFI SAR support for tarloJoey Peng
Taeko/Tarlo uses the WIFI_SAR_ID field in FW_CONFIG to pick which SAR table to load. BUG=b:226684990 TEST=emerge-brya coreboot Cq-Depend: chrome-internal:4676926, chrome-internal:4686953 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I9852553f5c91494db845d45a94e2566248538bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-21mb/google/brya/var/osiris: Generate SPD ID for supported partsDavid Wu
Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B (Micron) MT53E1G32D2NP-046 WT:B (Micron) H54G46CYRBX267 (Hynix) H54G56CYRBX247 (Hynix) K4U6E3S4AB-MGCL (Samsung) K4UBE3D4AB-MGCL (Samsung) BUG=None TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63706 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-21mb/google/brya: Create osiris variantDavid Wu
Create the osiris variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:229352299 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_OSIRIS Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I41e088a3415add86cba87c919af23494f816bb24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63650 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20mb/google/skyrim: Update SPI settings for skyrimChris.Wang
Update SPI setting as below: Normal speed:33mhz Fast speed:66mhz Alt speed:66mz TPM speed:33mhz BUG=b:225213679 TEST=boot skyrim and verify spi settings. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Icbe4b9f4794f7e883c3819258ede809c3c8922b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-20mb/google/brya/var/vell: increase RFI Spread Spectrum to 6%Robert Chen
Increase RFI Spread Spectrum to 6% for Vell as RF team request. The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard as default. BUG=b:228929196 TEST=emerge-brya coreboot and pass RF test as before Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-20mb/google/brya/var/brya0: configure gpio for headsetAmanda Huang
Configure GPP_R0, GPP_R1, GPP_R2 and GPP_R3 for headset function enable with ALC5682I+MAX98360. BUG=b:202671753 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Change-Id: I93070a8096d43557a50e5a545227f2906e299d8e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-04-20mb/google/brya/var/brya0: Swap TPM and touchscreen I2C busAmanda Huang
Based on the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:202671753 TEST=emerge-brya coreboot Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-20Revert "mb/google/guybrush/var/dewatt: Override SPI fast speed"Rob Barnes
This reverts commit d80d88c0fec96b2fff93db87d0c83f4c6754ae7a. Reason for revert: 100Mhz should only be enabled on DeWatt on board version >=3. Enabling it on board version 2 will cause failures. BUG=b:213403891 BRANCH=guybrush TEST=Build dewatt Change-Id: I0b6acd2cda2af35ff33e89e3b339731e35d72cb1 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63746 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-20ChromeEC boards: Drop `IGNORE_IASL_MISSING_DEPENDENCY`Angel Pons
This should no longer be needed because the ASL has been fixed. Change-Id: I4d1500217bef54fa3d2be397e5e2a155da3f965d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-20mb/google/brya/var/redrix: Add alias back to RP6 WWAN deviceTim Wawrzynczak
This alias name is required for the mainboard.c code to generate the appropriate power-off seqeuence for use during orderly S5 shutdown from the OS. It had been accidentally removed, but is required, so this patch adds it. BUG=b:227788351 TEST=compile Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I8936a01bd3a6b908033a8c58bd4e84b30d199e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-20mb/google/brya/var/anahera{4es}: Enable power saving for Smart CardWisley Chen
Configure the power saving pin for Smart Card. BUG=b:229356121 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-20mb/google/guybrush/var/dewatt: Override SPI fast speedKenneth Chan
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=b:213403891 TEST=Build and boot to OS in Dewatt board version 2. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63685 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-19mb/google/brya: Disable PCH USB2 phy power gating for felwinterSridhar Siricilla
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for felwinter board. Please refer Intel doc#723158 for more information. BUG=b:221461379, b:226020977 TEST=Verify the build for felwinter board Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-04-19mb/google/brask/variants/moli: update type-c setting in overridetreeRaihow Shi
Add conn1 for pch_espi and add type-c port2 for pmc_mux. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-19mb/google/brask/variants/moli: add delay time to rtd3-coldRaihow Shi
This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence, the reason is that the rise and fall times of each signal may differ by board, and so those board-specific delays must be taken into account when power sequencing. We checked power on sequence requires enable pin prior to reset pin, so added delay to meet the sequence. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:228907551 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/brask/variants/moli: remove i2c1 in overridetreeRaihow Shi
Remove i2c1 because brask devicetree is already has it. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-19mb/google/skyrim: Configure Pen Detect deviceIan Feng
Enable pen garage. Pen detect is active low. BUG=b:229168203 TEST:Build and boot to OS in skyrim. Evtest work as expected Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 1 Properties: Testing ... (interrupt to exit) Event: time 1649922170.578779, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649922170.578779, -------------- SYN_REPORT ------------ Event: time 1649922172.070740, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I3bb07af6aebdc355a73148d8be79b1014147f61d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-19mb/google/skyrim: Add Goodix touchscreenIan Feng
Add Goodix touchscreen according to the Programming Guide Rev.0.7 BUG=b:228907558 TEST=local build and tested with Goodix touch screen Change-Id: I35dd3ca76e9e0f17508bef46c90b53b4be5d0033 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63573 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-27 02:23:07 +0000