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2023-05-12mb/google/rex: Set WWAN_RF_DISABLE_ODL to NCTarun Tuli
This signal isn't functionally being used and is causing leakage during suspend. Set it to NC. BUG=b:279762779 TEST=builds. WWAN functional. Change-Id: I93f2b0a781e250678280b57e4ab1d80ef27ff460 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-12mb/google/brya: Fix typo in gma-mainboards filenameTarun Tuli
Small typo in brask/gma-mainboards-ads Should be brask/gma-mainboards.ads BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=Builds Change-Id: I9800870dcef13a3e16f6235137e79234a5e6bf83 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75052 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-11mb/google/brya: Create gothrax variantYunlong Jia
Create the gothrax variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.). BUG=279614675 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GOTHRAX Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I129e4a55e4b87091e425a45392024d04f3977c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-11mb/google/dedede/var/boxy: Disable EXT_VRKevin Yang
The boxy removed the APW8738BQBI-TRG and "disable_external_bypass_vr" should be set to "1" to disable BUG=b:271407334 TEST=emerge-dedede coreboot Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: Ic6667e93de41e84f67363ab7554fe755fe50684a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74889 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-11mb/google/dedede/var/boxy: Update devicetree and GPIO tableKevin Yang
Create overridetree and GPIO config based on latest schematic: 1. Update PCIe ports 2. Update USB ports 3. Remove unused I2Cs 4. Remove unused peripherals (SD card, eDP, speakers) 5. Add LAN 6. Thermal policy for updated temp sensors BUG=b:277529068 BRANCH=dedede TEST=build Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I5a155ebca50dbd5bdb046713ebabbee395361273 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74626 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-11mb/google/brya/variant/hades: Reduce PEXVDD shutoff delay for HadesTarun Tuli
For the sequenced controlled shutdown path, there's a 10ms delay after the PEXVDD rail is disabled to permit discharge needed on Agah/Proxima. This can be dropped to 3ms for Hades designs Proto0 and forward. Once Agah board is dropped, "if CONFIG" can be cleaned up/removed. BUG=b:271167335 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I8a0d62ec76caff861adce2d6c0ba2d4e4064affa Reviewed-on: https://review.coreboot.org/c/coreboot/+/75051 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-09mb/google/link: Apply symmetry for EC events definesKyösti Mälkki
All other boards use MAINBOARD_ prefix instead of board name. Change-Id: I97d9d28963c97e780156d75b39deac069028866a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-09mb/google,intel: Use common ChromeEC code for lid shutdownKyösti Mälkki
Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-05-09mb/google,intel: Use common ChromeEC code for SMI APMCKyösti Mälkki
Change-Id: If4b7c2b94e0fec84831740336ccdbea0922ffbfe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74513 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-05-09mb/google,intel,samsung: Use common poweroff()Kyösti Mälkki
Change-Id: I3881c152663a038833d8126d7f24f2a6688426d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74515 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-09mb/google/corsola: Enable HIMAX83102_J02 and ILI9882T panel for StarmieRuihai Zhou
The STA_HIMAX83102_J02 and STA_ILI9882T panel will be used for Starmie, enable these two panels config for it. BUG=b:272425116 BRANCH=corsola TEST=build starmie and check the cbfs include the panels Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I1dd696dd6a84d9606e4b9a2d4884dd70a6df9161 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74200 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08mb/google/myst: Add selective FP initJon Murphy
Add FW_CONFIG item for FP sensor init and conditionally init the GPIOs based on whether we're using a SPI or UART FP sensor. BUG=b:276939271 TEST=builds Change-Id: I9815bd17df1d15f73529beb15d08cde1ef90efad Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-08mb/google/myst: Add eMMC/NVMe config supportJon Murphy
Add FW_CONFIG item for eMMC/NVMe support and address the init of the lanes based on said config. BUG=b:278877257 TEST=builds Change-Id: Id6452f497cf78549b7d6126f1b55cd6d45b403c3 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74957 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Mark Hasemeyer <markhas@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-08mb/google/brya: Split gma-mainboards for different baseboardsTarun Tuli
Allow different gma-mainboards configs for different baseboards as they support varying display interfaces. Set Brya to eDP only and Brask to HDMI only. BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=Builds and SoL functions on both brya and brask varaints Change-Id: Iaf3f35b009d53e50723e4aa82c0f4932783f9bb9 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-08mb/google/rex/var/rex0: Correct _PLD values for USB C0Won Chung
Denote the correct value of ACPI _PLD for USB ports. The horizontal position of port C0 is incorrectly labelled. +----------------+ | | | Screen | | | +----------------+ C0 | | A0 | | C1 | | +----------------+ BUG=b:216490477 TEST=emerg-rex coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Id9ed435ca0af131e3bb4538701fc97d78146899f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74366 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08mb/google/nissa/var/uldren: Update eMMC DLL settingsDtrain Hsu
Update eMMC DLL settings based on Uldren board. BUG=b:280120229 TEST=executed 10 cycles of cold boot successfully Change-Id: I46e2f9df0e82e66fa3ae32aa87b4bcf30d5737ab Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-08mb/google/nissa/var/yavilla: Add G2touch touchscreen supportTony Huang
Update devicetree to support G7500 touchscreen. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot and check touchscreen function Change-Id: I3b63b1bb45275ad7eef8799dcff27f264739c258 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-08mb/google/volteer/Kconfig: Add variant model namesMatt DeVillier
Change-Id: Id5b0fa96ca8d86ddf20d808f5107a43ad2d0a1e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-06mb/google/jecht: Clean smihandlerKyösti Mälkki
Change-Id: I47ec05aa87e4e7c02b19817b2f703eca492008e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-06mb/google/rex/var/screebo: Add DDR DQ map configKun Liu
Add DDR DQ map config for screebo BUG=b:276814951,b:272218757 TEST=emerge-rex coreboot Change-Id: I993ae4024689b9cedbea247689a760bd83cd0d45 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74961 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-05mb/google/myst: Add variant makefileJon Murphy
Add variant makefile to support including the memory folder for Myst. BUG=b:273383819 TEST=Builds in chromium with blobs Change-Id: I03b0cd91dd66f357b15522da36f5118867b6b14c Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74964 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-05mb/google/fizz: Override SMBIOS product name based on OEM IDMatt DeVillier
Use the OEM ID from CBI to determine the correct OEM board name. ID mapping taken from ChromeEC source, branch firmware-fizz-10139.B. TEST=build/boot multiple fizz variants, check that board name reported correctly in SMBIOS tables. Change-Id: I06251974ac73570b911920ed566a175e8e733710 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-05mb/google/poppy/var/nami: Override SMBIOS product nameMatt DeVillier
Override SMBIOS product name with sub-variant name based on board SKU. TEST=build/boot multiple nami variants, verify SMBIOS product name reports correctly. Change-Id: I2125bfb6436469405378f9c983d7cfcb2f85f916 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-05vc/google: Decouple DSM_CALIB from CHROMEOSMatt DeVillier
DSM (Dynamic Speaker Management) uses calibration parameters stored in a VPD (Vital Product Data) FMAP region to configure the audio output via an ACPI _DSD table. This has no dependency on a ChromeOS, and can be used by Linux/Windows drivers if appropriately configured. Remove the dependency of DSM_CALIB (and the calibration file) on CHROMEOS and replace it with VPD, so that non-CHROMEOS builds can utilize this feature as well. Move files from underneath vc/google/chromeos to underscore the point. TEST=build/boot google/nightfury, dump ACPI, verify DSM calibraton parameters present in _DSD table. Change-Id: I643b3581bcc662befc9e30736dae806f94b055af Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-05Convert literal uses of CONFIG_MAINBOARD_{VENDOR,PART_NUMBER}Kyösti Mälkki
Only expand these strings in lib/identity.o. Change-Id: I8732bbeff8cf8a757bf32fdb615b1d0f97584585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-05mb/google/brya/var/marasov: Disable Tccold HandshakeFrank Chu
The patch disables Tccold Handshake to prevent possible display flicker issue for marasov board. Please refer to Intel doc#723158 for more information. BUG=b:279117758 BRANCH=firmware-brya-14505.B TEST=Boot to OS on marasov. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I286e88e5bec240d64e6c801648f6483ad2b0939c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74931 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-05mb/google/poppy/variant/nami - Move FPMCU IO setup back to ramstageTarun Tuli
variant_board_sku() is missing dependences in order to work correctly in romstage. Rather than more intrusive rework as its use is limited, move the FPMCU early GPIO init back to ramstage. We still meet sufficient power off time to fully power cycle the MCU. BUG=b:245954151 TEST=Confirmed FPMCU is still functional on Nami and FP tests all pass Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ia428ec5aec1a0438e91bc48903bda043046b740e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74695 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-05mb/google/octopus: Disable unused devices in devicetreeMatt DeVillier
The image processing unit/GMM and xDCI are not used on octopus boards; additionally, enabling xDCI can cause some problems with USB ports in both booting from the payload and in the OS. Change-Id: I1ee99b5c45881a4cf3624bf487bc9d83fb3d07a1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-04mb/google/puff: Add SOF chip driverMatt DeVillier
Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on wyvern variant, verify headphone output and microphone functional under Windows using coolstar's SOF drivers. Change-Id: I421c070eac321c2fc160b8f26868bcb1ec13001e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74815 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-04mb/google/volteer: Add SOF chip driverMatt DeVillier
Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on several volteer variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: I62a96149cec9eeb7b2da8a2337083969a1b0fce0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74816 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-04mb/google/brya: Add SOF chip driverMatt DeVillier
Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on banshee and osiris variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: I12614b85f9779cc40d83a9c868cc46b110f26af6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74817 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-04mb/google/dedede: Add SOF chip driverMatt DeVillier
Add all SOF chip drivers to baseboard and use FW_CONFIG to determine the correct option, to ensure the correct audio config is passed to the SOF OS drivers. TEST=build, boot Windows on several dedede variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: I9452b11af614d8727aa8dd448e37f7a06faa450d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74818 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-03mb/google/brya/var/omnigul: Adjust I2C3 and I2C5 Waveform meet to SPECJamie Chen
Tuning i2c frequency ,timing ,Waveform meet to SPEC i2c frequency : I2C0=>399.8khz / Setup Time:1765ns / Hold Time:82.35ns. I2C1=>390.4khz / Setup Time:1.788us / Hold Time:70.58ns. I2C3=>308.7khz / Setup Time:1.482us / Hold Time:0.4us. I2C5=>390.8khz / Setup Time:1.218us / Hold Time:0.405us. BUG=b:275061994 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot, EE check OK with test FW and TP function is normal. Change-Id: I5b77cd3fd3ff00804f1b8dd5828dc831a9732566 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74880 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-05-03Drop many cases of CONFIG_MAINBOARD_PART_NUMBERKyösti Mälkki
We have largely dropped from filling in mainboard_ops.name as unnecessary. A common place should be decided where or if this information is added in the console log. Change-Id: I917222922560c6273b4be91cd7d99ce2ff8e4231 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-03mb/google/hatch: Add SOF chip driverMatt DeVillier
Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on several hatch variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: Ie791fa873fc7bbab84644f5ea5743bdcdc124908 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-05-03mb/google/reef: Disable unused devices in devicetreesMatt DeVillier
The image processing unit (Iunit) and SoC UARTS are not used on any reef boards. Change-Id: Iacdf93b4952cbc63fc465f07d440463106527b8d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-03mb/google/reef: Disable Intel Trace Hub PCI deviceMatt DeVillier
It's not particularly useful to end users, and shows up as an unknown PCI device under Windows Device Manager. TEST=build reef, boot Windows, verify unknown PCI device no longer present in Device Manager. Change-Id: Ie8ec46e2e07b6635bfe9766812ce08b866c71d66 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-02mb/google/myst: Inject SPD binaries to APCBKarthikeyan Ramasubramanian
Add rules to inject the variant specific SPD binaries into APCB. BUG=b:273383819 TEST=Build Myst BIOS image. Currently no APCB is present. So no SPD is injected into APCB. Change-Id: Ic511cdc4fe0989c9abc0cd0531cc0cae40f8dc34 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74746 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-05-02mb/google/myst: Add initial memory configurationKarthikeyan Ramasubramanian
Generate the RAM Strap IDs based on the initial memory configuration. BUG=b:272746814 TEST=Build Myst BIOS image. Change-Id: I8a4fe9a41f101ac10391756f1b815220c8b98612 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-01mainboard/*: Drop USB power control bits in GNVSKyösti Mälkki
There is no platform-level implementation for USB port power management in various sleepstates. The mainboards changed here never evaluate the set GNVS variables S3U0, S3U1, S5U0 and S5U1 in ASL or in their SMI handlers. Change-Id: Ia1bc5969804a7346caac4ae93336efd9f0240c87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2023-05-01mb/google/volteer/Kconfig: Alphabetize variants, Kconfig selectionsMatt DeVillier
Change-Id: I634af65cd41e0d70e673d550ed8063abc6eea6d4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01mb/google/volteer: Add VBT data files for variantsMatt DeVillier
Add data.vbt files for all variants supported by current volteer recovery image. Several boards use the same VBT, so place the "common" VBT under the baseboard directory and set it as the default. For variants with a unique VBT, override the default and use the file in their respective variant directory. Select INTEL_GMA_HAVE_VBT for all variants which have a VBT file. TEST=build/boot various volteer variants Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74852 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-01mb/google/nissa/var/craask: avoid camera LED blinking during bootJimmy Su
Camera LED will blink several times as sensor is being probed during kernel boot. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:274634319 TEST=Build and boot on Craask. Verify & observe Camera LED blinking behavior. Change-Id: I78ed5efe1e2c071d817c1e0455271886e89e63c7 Signed-off-by: Jimmy Su <jimmy.su@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74728 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-29mb/google/poppy/variant/nami - Ensure power cycle of FPMCU on startupTarun Tuli
Add functionality to ensure that the FPMCU is power cycled long enough on boot to ensure proper reset. This solution relies solely on coreboot to sequence the power and reset signals appropriately (150ms on boot). -Confirmed power is off for 150ms on boot. -Confirmed RCC_CSR of FPMCU indicates power cycle occurred. -Confirmed reset is de-asserted approx 3ms after power application (target >2.5ms) BUG=b:245954151 TEST=Confirmed FPMCU is still functional on Nami and timings are as expected. Change-Id: I0a23bda96bc2ea90be81a2310605f75c55c0a839 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-29mb/google/poppy: Add support for variant SKU romstage GPIO configsTarun Tuli
Add functionality that allows a variant SKU to have a specific set of GPIO configs in romstage (modeled after the existing one in ramstage) BUG=b:245954151 TEST=builds Change-Id: I593a23951306908fadc00e6bc8d9d310f09c5e4b Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-29mb/google/rex/variants/screebo: Generate RAM IDsKapil Porwal
Generate RAM IDs for - MT62F512M32D2DR-031 WT:B (LP5) H9JCNNNBK3MLYR-N6E (LP5) MT62F1G32D2DS-026 WT:B(LP5x) H58G56BK7BX068 (LP5X) BUG=b:276814951 TEST=Run part_id_gen tool without any errors Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74802 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-28mb/google/rex/var/screebo: Add initial setup for gpio configKun Liu
add the initial gpio configuration for screebo initial variant BUG=b:276814951 TEST=emerge-rex coreboot Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Change-Id: Ib96e03f47bc1d6e5628ae459c3e1eb4dc18849c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74475 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-28mb/google/skyrim: Enable SPL fusing on MarkarthJohn Su
Because SPL fuse needs to be set before the FW lock. So enable Markarth project to send the fuse SPL (security patch level) command to the PSP. BUG=b:279499511 BRANCH=none TEST=FW_NAME="Markarth" emerge-skyrim coreboot chromeos-bootimage Then get "PSP: SPL Fusing Update Requested." in the firmware log. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I8fbbd89d11b1bdb2c95c761955c10bedb366fd70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74753 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27mb/google/skyrim/var/winterhold: Add support for K3KL6L60GM-MGCTRex Chou
Update Samsung 4G K3KL6L60GM-MGCT support BRANCH=None BUG=b:243337816 TEST=emerge-skyrim coreboot Change-Id: I89b9798c16635a32dff12f1c0b65737d3c16cd59 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-27mb/google/rex: Add USB4 ANX7452 Rev 2 to USB_DB FW_CONFIGSubrata Banik
This patch adds new USB_DB FW_CONFIG to enable support for USB4 ANX7452 Rev 2. BUG=b:279647370 TEST=Able to build and boot google/rex with Proto 2 SKU Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I878b591e5919d05d3c5fc2eefdeb492e95d4f7b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-27mb/google/skyrim/var/winterhold: adjust the eDP panel power sequenceChris Wang
Set edp_panel_t9_ms to 8ms which means it will delay 8ms between backlight off and vary backlight off. BUG=b:271704149 BRANCH=Skyrim TEST=Build; Verify the UPD was passed to system integrated table; Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74790 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-27soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_msChris Wang
Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to match the eDP sequence timing in milliseconds. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-27mb/google/nissa/var/yavilla: Add elan touchscreen supportTony Huang
Update devicetree to support ELAN I2C generic touchscreen. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I2779c2930d89ff42233f9b20bd8abdf6dc00c0e0 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74776 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-27mb/google/corsola: Report SKU and panel ID for unprovisioned devicesRuihai Zhou
The MIPI panels will be used on the detachable variant starmie, and there will be different MIPI panels used on starmie. In order to make the different panels functional on unprovisioned devices, it needs to pass the SKU ID and panel ID to the payload to load the matched device tree for kernel. From the schematic, the starmie variant will read the LCM ID from ADC channel 5. BRANCH=corsola BUG=b:275470328 TEST=boot starmie and see FW screen display Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I6339dc3c177fb8982f77fb3bd32dc00da735fce4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2023-04-27mb/google/brya/variants/hades: Correct and swap NV33 signalsTarun Tuli
The signals for the NV33 regulator were swapped (enable and power good). Switch these back to the way they should be: GPIO_NV33_PWR_EN GPP_E1 GPIO_NV33_PG GPP_E2 BUG=b:269371363 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ic2a53103e1feadd7ecebd4bed02dcc34410b8e3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-26mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq insteadEricKY Cheng
Because WD SSD drive isn't holding the clock low for some reason. So we change to read eMMC clkreq signal instead. BRANCH=none BUG=b:274377518 TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok. Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-26mb/google/skyrim: Disable unused SPI ROM typesMartin Roth
By default, coreboot includes support for all the different types of SPI ROMs. Excluding the unused ROM types shrinks ramstage by almost 4k. BUG=b:267735039 TEST=Build & Boot ROM BRANCH=Skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If6e402269d1f2cac8256d478eb36743441497bdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/72769 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-04-26mb/google/brya/var/taeko: remove rtd3 for emmcJoey Peng
Remove rtd3 for emmc device on taeko BUG=b:271003060 TEST= emerge-brya coreboot, flash to DUT and can boot to OS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I21191c9762a00ba137892e680d533f7dc3b53e86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-26mb/google/brya/var/taniks: remove rtd3 for emmcJoey Peng
Remove rtd3 for emmc device on taniks BUG=b:271003060 TEST=emerge-brya coreboot, flash to DUT and can boot to OS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I03168ecbf4611f05acd8c6c722b6a5037a8cc31d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-26mb/google/myst: Enable tis_plat_irq_statusJon Murphy
This will fix: > [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50! BUG=b:277297687 TEST=builds Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74286 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-26mb/google/myst: Configure WLANJon Murphy
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN. Mapping derived from myst schematic. BUG=b:275965982 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-26mb/google/myst: Enable PCIe devices in devicetreeJon Murphy
Ensure that DXIO descriptors are updated using info from AMD and Myst board schematics. BUG=b:275960920,b:276744321 TEST=builds Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74112 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-26mb/google/brya/var/omnigul: Disable Tccold HandshakeDtrain Hsu
The patch disables Tccold Handshake to prevent possible display flicker issue for Omnigul board. Please refer to Intel doc#723158 for more information. BUG=b:279539826 BRANCH=firmware-brya-14505.B TEST=Verify the build for Omnigul board Change-Id: I04e54df5afe09c12e1cf774445d57e13ffd8819e Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74737 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-25mb/google/nissa/var/yaviks: Update devicetree for UFC usb portTony Huang
USB port 6 connects to a USB front camera, it should always probe. Remove probe by rear camera fw_config. BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I554046718f6e0eb7197970f9a3808b3e1ea7f99c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-25mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIGTony Huang
Update devicetree -Enable USB2 port5 for WWAN -Update OVTI8856 setting -Update USB2/3 Type-A 0/1 port location Probe devicetree based on FW_CONFIG -pen garage -rear mipi cam -USB WWAN BUG=b:273791621, b:276369170 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-24mb/google/myst: Set system type to laptopJon Murphy
BUG=b:277294070 TEST=None Change-Id: I0aa4e0bcfb06e5e5cb7e9d52f2d82b5818925267 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74284 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-24mb/google/myst: Store XHCI PCI resourcesJon Murphy
Implement `smm_mainboard_pci_resource_store_init` to store the resources for XHCI devices. These stored resources are later used by the elog code to log XHCI wake events. BUG=b:277273428 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I608d51f438681ac529323c23cc707845a3d609d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74281 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-24mb/google/myst: Enable gfx_hdaJon Murphy
Enable gfx_hda to allow for audio over hdmi. BUG=b:277219546 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I58096f1408f66f968af1494e487cf2bfc43b9a0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74278 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-24mb/google/myst: Enable crypto in devicetreeJon Murphy
Add the crypto device to the devicetree. BUG=b:277214359 TEST=builds Change-Id: I5394c5f9df64642d8633af84cf662652bd1a5cb2 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74275 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-22soc/amd/mendocino: drop code for non-existing eMMC controllerFelix Held
Mendocino and Rembrandt don't have an eMMC controller and also don't have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC related code from Mendocino. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8ec49a7084bdd62e480baee75a280fde8b13d01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-22mb/google/octopus: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:268342532 BRANCH=firmware-octopus-11297.B TEST=Observe kernel ec panic handler run when ec panics Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I37e566e459f39f8bc2dafc3c3915260259730ca6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22mb/google/dedede/var/boxy: Generate SPD ID for supported memory partkevin3.yang
Add boxy supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K4U6E3S4AB-MGCL 2. Hynix H54G46CYRBX267 3. Micron MT53E512M32D1NP-046 WT:B BUG=b:278983561 TEST=Use part_id_gen to generate related settings Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I317f2b31774627706babdea10776af05ab692d1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-22mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviksTony Huang
Yavilla board memory id setting references to yaviks. This CL aligen it with yaviks. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) H9JCNNNBK3MLYR-N6E 0 (0000) H58G56AK6BX069 2 (0010) K3LKBKB0BM-MGCP 2 (0010) H58G56BK7BX068 3 (0011) MT62F1G32D2DS-026 WT:B 3 (0011) K3KL8L80CM-MGCT 3 (0011) H58G66BK7BX067 4 (0100) MT62F2G32D4DS-026 WT:B 4 (0100) K3KL9L90CM-MGCT 4 (0100) H58G66AK6BX070 5 (0101) BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=run part_id_gen to generate SPD id Change-Id: I4a5eb9e6e87a4adbc23f94f0eb92d5452c50e47c Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22mb/google/brya/variants/hades: Swap LAN and SD Card PCIE PortsTarun Tuli
To aid in layout, the PCI ports for LAN and SD card were swapped. SD Card is now on RP3 (clksrc 4) LAN is now on RP8 (clksrc 3) BUG=b:269371363 TEST=builds Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: If59849c13e4c42f00e3571c0385994ade5931adb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gatingFrank Chu
The patch disables PCH USB2 PHY power gating to prevent possible display flicker issue. Please refer Intel doc#723158 for more information. BUG=b:279117758 BRANCH=firmware-brya-14505.B TEST=Verify the build for marasov board Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74627 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-22mb/google/corsola: Rename common config from `STARMIE` to `STARYU`Ruihai Zhou
The STARYU is the mt8186 detachable reference design, and the STARMIE is a variant of STARYU. Let's rename the common config from STARMIE to STARYU, and we can select the STARYU config for the follow up mt8186 detachable variant. BRANCH=corsola BUG=b:275470328 TEST=./utils/abuild/abuild -t google/corsola -a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: If75e94e86420b0a216fe7a1a9dee9cb42bbd985c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74654 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-04-22mb/google/brya: Enable CSE FPT Info config for NissaSubrata Banik
Google Brya variants like Nissa family selects `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` to store CSE FPT information. BUG=b:273661726 TEST=Able to build and boot google/marasov. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I234b5d272077de9a6f0a9ba69fa015cda7ebd56c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74387 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-22mb/google/rex: Enable asynchronous End-Of-PostSubrata Banik
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 100ms on google/rex. TEST=Tests on google/rex with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-21mb/google/myst: Expose SKU and board ID to Chrome OSJon Murphy
Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to provide common routine for reading skudid and boardid from Chrome EC. BUG=b:277293398 TEST=builds Change-Id: I8e42ba23dada9771f335df34275e44e51d645596 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74283 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21mb/google/brya: Enable RTD3 root port mutex for WWANCliff Huang
This adds RTD3 RPMX mutex to the root port. It is shared between RTD3 and WWAN. BRANCH=firmware-brya-14505.B TEST=boot to OS and check the generated SSDT table for the root port. The RPMX mutex should be generated under the root port. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia87b5f9d8300d6263c84a586256424799d3a45b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73382 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-21mb/google/myst: Enable mp2 deviceJon Murphy
The mp2 PCI device is still present when no mp2 firmware is loaded. When this device isn't explicitly enabled in the mainboard's devicetree, the chipset devicetree default of the device being disabled is used. This results in coreboot's resource allocator not allocating resources to the device and since the bridge doesn't have enough MMIO space reserved, the Linux kernel can't assign resources to it. Enable the mp2 device in the mainboard's devicetree so that it gets its resources assigned by coreboot. BUG=b:277217097 TEST=builds Change-Id: I21885c51ff08846b456675090946f381843ef5e6 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74277 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21mb/google/myst: Enable audio co-processor in devicetreeJon Murphy
Enable the audio co-processor in the device tree. BUG=b:277214614 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I1e1749359804960bbd75d869385b9071e7f33be7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74276 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21mb/google/skyrim/var/markarth: Change to read the eMMC clkreq insteadJohn Su
Because WD SSD drive isn't holding the clock low for some reason. So we change to read eMMC clkreq signal instead. BRANCH=none BUG=b:278495684 TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74583 Reviewed-by: Chao Gui <chaogui@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-04-21mb/google/volteer/var/delbin: Add new memory supportFrank Chu
Add the new memory support: Samsung K4UBE3D4AB-MGCL BUG=b:274373361 BRANCH=firmware-volteer-13672.B TEST=FW_NAME=delbin emerge-volteer coreboot Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ie88c25b4b0f88ed299711f2b6b94006d5301554c Reviewed-on: https://review.coreboot.org/c/coreboot/+/74556 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-21mb/google/myst: Enable AP <-> GSC communicationJon Murphy
Configure GSC I2C and Interrupt GPIOs during the early initialization. Add devicetree configuration for GSC device and enable the required config items. BUG=b:275959717 TEST=builds Change-Id: I6e235356b252a7b68a42da128ffd3189a829f117 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74111 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21mb/google/brya/var/marasov: Add _DSD object for wifiFrank Chu
`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it makes sense to have a unified name across different device drivers. BUG=b:278310435 BRANCH=firmware-brya-14505.B TEST=Verified that the _DSD object is still present in the SSDT. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I5a69a47e67f6acaad5a5d1b67e437c5a41bebf3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74499 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-21mb/google/dedede: Create boxy variantkevin3.yang
Create the boxy variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:277529068 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_BOXY Change-ID: Ief22eb000421c23abf6de3f99eb860bdae1e7919 Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-20mb/google/myst: Add eSPI configurationJon Murphy
Add eSPI configuration for myst. Ensure the additional windows are used and remove unnecessary addresses from the range used on skyrim. BUG=b:275953893 TEST=builds Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74110 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19mb/google/myst: Add initial fch irq routingJon Murphy
Add initial fch irq routing table for Myst. BUG=b:275946702 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ic81c3cbfbb30a0beb3c4083624cf19abe6d1e694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74109 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19mb/google/skyrim: Fix eMMC reset GPIOJon Murphy
On Skyrim variants, the eMMC reset GPIO should be SSD_AUX_RST_L (GPIO6). Update the port_descriptors to link the correct reset GPIO. Data is from the skyrim variant schematics and go/skyrim-gpios. BUG=b:278759559 TEST=reboot: 5 iterations suspend_stress_test: 10 iterations Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74512 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-19mb/google/brya/var/crota: select SOC_INTEL_RAPTORLAKETerry Chen
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP as crota is using a converged firmware image. BUG=b:267249674 BRANCH=firmware-brya-14505.B TEST="FW_NAME=crota emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage" Cq-Depend: chromium:4430832 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I448c58f93fddc44904c1f5ef3f8939618eff536f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-19mb/google/kukui: Add sdram configs for RAM code 0x33 and 0x34Sheng-Liang Pan
Add sdram configs: - RAM code 0x33: sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB SPD for K4UBE3D4AB-MGCL 4GB - RAM code 0x34: sdram-lpddr4x-H9HCNNNFAMMLXR-NEE-8GB for H54G68CYRBX248 8GB BUG=b:278644249 BRANCH=kukui TEST=emerge-jacuzzi coreboot Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: If5b484b5324ba39dbb220f12bdb8344ecb5c4da5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73469 Reviewed-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-19mb/google/brya/var/constitution: Generate SPD ID for supported partsMorris Hsu
Add supported memory part in mem_parts_used.txt, then generate. K4UBE3D4AB-MGCL BUG=b:267539938 TEST=run part_id_gen to generate SPD id Change-Id: Iee41bb4511f2d77e5ddc2798f9d4db6137ed818d Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74497 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-18mb/google/brya/var/omnigul: Adjust I2Cs CLK to be around 400 kHzJamie Chen
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for audio, TPM, touchscreen, and touchpad. Tuning i2c frequency for omnigul I2C0 - Audio CLK : 293.7khz I2C1 - TPM CLK : 388.8khz I2C3 - Touch Screen CLK : 294.8khz I2C5 - Touch Pad CLK : 389.2khz BUG=b:275061994 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot, and measure i2c clock. Change-Id: I7c4fdf0e003318a69b870b487a60accefbc0ffed Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-17Makefiles: Drop redundant VARIANT_DIR definitionsKyösti Mälkki
Change-Id: Ie75ce1eee3179a623da812a6b76c7ec457684177 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-17mb/google/dedede/var/boten: Generate SPD ID for supported memory partkevin3.yang
Add boten supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K4U6E3S4AB-MGCL BUG=b:278138388 TEST=Use part_id_gen to generate related settings Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I5f910393847c6494f77c009cb11f50b31bebffb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-17mb/google/rex: Enable all DDI lanesAnil Kumar
This patch enables all DDI ports on Rex board to support display port tunneling and dual display on TBT dock. BUG=b:273901499 TEST=Boot google/rex and connect two displays over a TBT dock and check the display functionality. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I45ee5334fbb877bd58912c8d24920037f155dc42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74413 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-17mb/google/brya/variants/hades: Update GPIO configsTarun Tuli
Update GPIO configs based on latest schematics (revision aabe36) Move GPP_D4->GPP_A13 (BT_DISABLE_L) Swap GPP_E3<>GPP_E8 (WIFI_DISABLE_L and PG_PPVAR_GPU_NVVDD_X_OD) Move GPP_A13->GPP_A20 (GSC_PCH_INT_ODL) BUG=b:269371363 TEST=builds Change-Id: I958e45156515cf4ce236084ec823f9329d7a063d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-17mb/google/nissa/var/craask: Add GTCH7503 and split TS by SSFCTyler Wang
Add G2 touchscreen GTCH7503 for craaskino. Use SSFC to separate touchscreen settings. Bit 38-41 for TS_SOURCE: (1) TS_UNPROVISIONED --> 0 (2) TS_GTCH7503 --> 1 BUG=b:277979947 TEST=(1) emerge-nissa coreboot (2) Test on craaskino with G2 touchscreen (3) Test on craaskino with elan touchscreen Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I636f21be39f26a617653e134129a11479e801ea2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-16mb/google/rex: Create screebo variantSimon Zhou
Create the screebo variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:276814951 BRANCH=None TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_SCREEBO Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74391 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>