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Add ELAN touch support and update Goodix settings.
BUG=b:157265632
BRANCH=zork
TEST=emerge coreboot and check both touch screen are workable.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icfc2421061e8b3163d7d5108673351bc17df20ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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This change reorganizes the CNVi device entries in mainboard
devicetree/overridetree and SoC chipset tree to make it consistent
with how other SoC internal PCI devices are represented i.e. without a
chip driver around the SoC controller itself.
Before:
chip drivers/wifi/generic
register "wake" = "..."
device pci xx.y on end
end
After:
device pci xx.y on
chip drivers/wifi/generic
register "wake" = "..."
device generic 0 on end
end
end
Change-Id: I22660047a3afd5994400341de0ca461bbc0634e2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Terrador and Todor are fanless design, so disable DPTF active policy.
BUG=b:171019363,b:170699797
BRANCH=volteer
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I53a33b8706d7a7d4013a2a5627a620223fcffc3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46874
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIO D4 was used for camera reset for both front and rear cameras
(RCAM_RST_L/FCAM_RST_L) in RIPTO. For later volteer versions,
GPIO F15 is dedicated to the rear camera reset (RCAM_RST_L).
Before, BOARD_GOOGLE_VOLTEER flag was used for setting the right
RCAM_RST_L per volteer version. However, we don't support RIPTO
anymore. Also using flags for different volteer version support can
be error-prone. Removing RIPTO support.
BUG=b:171726823
BRANCH=none
TEST=Build and boot volteer proto2 or later version. Camera should
work without an issue.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I961fc17092887b4807c12c95f7139bb7e7b33e91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46826
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The camera privacy LED blinks during the boot and this gives a wrong
impression to the users that the camera is being used during the power
up. The blink happens when the camera module is probed and a series of
kernel patches and coreboot patches are being submitted to resolve the
issue.
The kernel patches are submitted to the chromium gerrit.
https://chromium-review.googlesource.com/2403386
https://chromium-review.googlesource.com/2403387
https://chromium-review.googlesource.com/2403385
https://chromium-review.googlesource.com/2403384
https://chromium-review.googlesource.com/2403383
https://chromium-review.googlesource.com/2403382
https://chromium-review.googlesource.com/2403381
https://chromium-review.googlesource.com/2403380
This is to separate the power resource for the VCM so that it can be
controlled by the driver and suppress the LED turn on.
BUG=b:169049942
BRANCH=none
TEST=Build and boot volteer board. Monitor camera privacy LED
and check if it blinks. It should not blink.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Id51c98e42c5f20e231d8096c9d2d98deebc7c968
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tomasz Figa <tfiga@google.com>
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LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.
If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:169645448
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3a04320b0e2441dce540a5afdc461f12de45c41b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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We all knew this was coming, 32 bits is never enough. Doing this early
so that it doesn't affect too much code yet. Take care of every usage of
fw_config throughout the codebase so the conversion is all done at once.
BUG=b:169668368
TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG
and verify the console print contained that bit.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices
can be hooked up together via devicetree aliases.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45878
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The current I2C5 bus frequency is 367 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring
the bus frequency closer to 400kHz.
BUG=b:153588771
TEST=Verified that I2C5 frequency is between 389-396kHz.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: If0803a74ba9071acf15486ce4038261c1681a92f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Flesh out the PCH configuration into a separate chip. Keep it within the
Broadwell SoC directory for now, to ease moving files around. The boards
were prepared beforehand and the devicetrees require next to no changes.
Tested on out-of-tree Acer Aspire E5-573, still boots.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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`chip` entries are only hooked up via device nodes to the tree. A `chip`
without a `device` below it does nothing. To allow variants to override
SATA tuning parameters, ensure a device exists under the PCH chip scope.
Without this change, some variants would not properly override the SATA
tuning parameters after extracting the PCH parts into a different chip.
TEST=Sanity-check static.c and verify overridetrees override properly.
Change-Id: I013dbe1403567b93c8ee0e66f76481f2a3f42796
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46769
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, all variants remain identical.
Change-Id: I0fa486b8a0fc8be974f37d0bb4eb77a254e8cd86
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46703
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:170604353
BRANCH=volteer
TEST=emerge-volteer coreboot, and boot into kernel.
Change-Id: If354aa158f3ad60193268f38278a44f9c99bf3db
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46770
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the ambassador variant of the puff reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:171561514
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_AMBASSADOR
Signed-off-by: Matt Ziegelbaum <ziegs@chromium.org>
Change-Id: Ib0e3a813a120a4a8e984f3a89dc3ba100d94da95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Remove code to turn on backlight during ACPI mode because backlight has
been properly enabled in ACPI.
BUG=b:158087989
BRANCH=Zork
TEST=tested backlight during reboot and suspend
Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I3bf06042aa19e4559127d611d401f0ba0516b3a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Generate acpi methods which enable and disable backlight during _INI,
_WAK, and _PTS.
BUG=b:158087989
BRANCH=Zork
TEST=check backlight during reboot and suspend
Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I2f3434dc92de1f697693ff69ca15bd76647b89a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46671
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add internal pull-down for GPP_D19 to improve DMIC noise issue on
nightfury.
BUG=b:171669255
BRANCH=firmware-hatch-12672.B
TEST=Built and checked GPP_D19 voltage after booting
Change-Id: Ie63f260be3d6a55f91908db59312b3b0a8af98f4
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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To support gpio reset SoC, we need to pass the reset gpio parameter to
BL31.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I2ae7684a61af76693605cc0bcf8d20c8992c7bff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46388
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The pins for SD and MMC must be configured properly
so we can access them in payloads.
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: Ie6bdffb987d5acf286645550f1c53f294f71c38a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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LTE module Fibocom L850-GL is lost after idle overnight,
with this workaround, host will not initiate U3 wakeup
at the same time with device, which will avoid the race condition.
If this option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR +
offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0.
BUG=b:171478764
BRANCH=octopus
TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash
the image to the device. Run following command to check if
bits[7:4] is set 0:
>iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Change-Id: I213fed2b56f216747b2727b69f97d46d8c0c872e
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46701
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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invoke LTE power off function to meet LTE power sequence while DUT is
in reboot state.
BUG=b:167565015
BRANCH=octopus
TEST=build and verify on the DUT with LTE
Change-Id: I825cefb524ddaf9a9cb6add31c2ee0eea484f978
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46022
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested with BUILD_TIMELESS=1, all variants remain identical.
Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure the I2C bus high and low time for all enabled I2C buses.
BUG=b:168783630
TEST=Measured the I2C bus frequency reduce to 387 KHz.
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I9f5b81815f86db7bdcea95a95b9c9b235b4a34b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46613
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The LCM ID is not really used on Jacuzzi followers and the reference
design expects ADC to return 0. However, there were hardware design
issues so the returned value became unexpected numbers.
- Juniper and Kappa returns 1.
- Burnet and Esche returns 1 on normal boot, and 0 on recovery boot.
- Cerise and Stern usually returns 0, and sometimes 1.
To fix that, we are changing LCM ID to fixed value for Jacuzzi followers.
BUG=b:170916885,b:171365301
BRANCH=kukui
TEST=1. emerge-jacuzzi coreboot
2. check burnet/esche skuid correctly
Change-Id: I3b43b9153315ec65e9168c4e84ea844dff14d446
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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1. Enable dptf feature and remove fan control part from overridetree.cb
2. Update tcc offset to 5
3. Follow thermal validation and update PL2 max_power to 51
BUG=b:167931578, b:170357248
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I99e429b90ed7de08385fe51ca742865b1266eef9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This reverts commit 214c719eed83967b8f0564feca65eebb3d83f5bc.
CB:45857 overrides the GPIO PM configuration if Cr50 does not support
long interrupt pulse width. More recent Cr50 Firmware versions support
long pulse width and hence the GPIO PM can take the default
configuration.
BUG=None
TEST=Build and boot Drawlat to OS. Ensured that 200 iterations of
suspend/resume sequence, warm and cold reboot cycles each are
successful.
Change-Id: I8e3be42cd82fd3ae919d23d6f19c84a90b9c737a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
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The dt option `speed_shift_enable` is obsolete now. Drop it.
Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Enable front camera power in ramstage.
BUG=b:169170677
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I8b5a9a8333ed518883aa3664a115a4ba2e8a0218
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
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Add goodix touch pad as below:
HWID : GXTP7288
CID : PNP0C50
I2C address : 0x2C
I2C speed : 400Khz
HID Descriptor Address : 0x20
BUG=b:171351666
BRANCH=octopus
TEST=build image and verify goodix touch pad working.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idb4f8d3aff09712dcc98c8ae0c9ae30dc4049e29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46614
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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New SKU ID 5 is used for LTE touch SKU. This patch does LTE power off
for LTE sku and only use Wifi SAR table for non-LTE sku.
BUG=b:168001586
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4 and 5.
Change-Id: Ic0405d3e52aa813bbb1f350966a9e2825e595ce4
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46643
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:161759253
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage
firmware log:
\_SB.I2C2.SEMTECH SX9324: SAR Proximity Sensor at I2C: 02:28
kernel log:
INFO kernel: [ 11.238644] sx932x i2c-STH9324:00: initial compensation success
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I6294ce291365443dd1c4550ba75cb7f33481b889
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45565
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since google_chromeec_cbi_get_board_version and google_chromeec_cbi_get_fw_config both call cbi_get_unit32 and return 0 as success, non-zero as failure. Let's add more readability for the false condition.
BUG=None
TEST=check with empty CBI value
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia49ac1ee35302f8f6afe8c0eb8e13afdf36c5b2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46566
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use PCIE_CLK_NOTUSED in place of 0xFF for unused PCIe ports
BUG=none
BRANCH=master
TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I35f2bbce35420fa98541a35f77b14df7440e7980
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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According to the schematic, SRCCLKREQ1# is not connected, so disable it
for terrador and todor.
BUG=b:171278849
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I5f7734d64390bfadbdb8d152261103adb8e75f40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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According to the schematic,SRCCLKREQ1# is not connected,so disable it
on voxel.
BUG=b:171279034
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46612
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Asurada EC is using the large packet (256B) mode, and we were
seeing lots of timeout errors on various commands.
The AcceptTimeoutUs in EC SPI driver is hard-coded at 5000,
and that is too small for large packet running in 1M so we
should change EC SPI to the same value that kernel is using (3M).
BUG=b:161509047
TEST=emerge-asurada coreboot chromeos-bootimage; flash and boot
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I9c47324022129ca23ef75d0c80e215da1692636d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46394
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enhance USB 2.0 C0/C1 A0/A1 SI by increasing the level of
"HS DC Voltage Level" and " Disconnect Threshold Adjustment" registers.
COMPDISTUNE0: 0x3->0x7
TXVREFTUNE0: 0x6->0xf
BUG=b:166398726
BRANCH=zork
TEST=1. emerge-zork coreboot
2. check U2 register is set correctly.
3. U2 SI all pass
Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46545
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable acoustic noise mitgation for volteer platforms.
BUG=b:153015585
BRANCH=none
TEST= Measure the change in noise level by changing the values
in devicetree.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I69a6453091bf607d3c5847c99bc077e6b7dbc639
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45053
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
VDD Slope: 62852 -> 62641
SOC Slope: 28022 -> 28333
BUG=b:170531252
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass AMD SDLE/Stardust test
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Id831907aa47be27fef2e33bb884a1118ffec14a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The disconnect voltage needs to be adjusted up because the HS DC voltage
level is 0xF.
BUG=b:170879690
TEST=Servo_v4 USB hub functions
BRANCH=zork
Change-Id: If8662015a45c57e457b4593e55af888084842f58
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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RW_LEGACY region needs to be 1 MiB to accommodate any alternate
firmware. Hence update the flash ROM layout as below:
* Grab ~512 KiB from each FW_MAIN_A/B regions and allocate them to
RW_LEGACY region so that it grows to 1 MiB.
* Remove VBLOCK_DEV region which is not used.
* Re-size the ELOG region to 4 KiB since that is the maximum size of the
ELOG mirror buffer.
* Resize RW_NVRAM, VBLOCK_A/B regions to 8 KiB since no more than that
size is used in those regions.
* Resize SHARED_DATA region to 4 KiB since no more than that size is
used in that region.
* Based on the resizing, allocate each FW_MAIN_A/B regions with 72 KiB.
BUG=b:167943992, b:167498108
TEST=Build and boot to OS in Drawlat. Ensure that the firmware test
setup and flash map test are successful. Ensure that the event logs are
synced properly between reboots. Ensure that the suspend/resume sequence
is working fine. Ensure that the ChromeOS firmware update completes
successfully for the boot image with updated flash map and the system
boots fine after the update.
Change-Id: I53ada5ac3bd73bea50f4dd4dd352556f1eda7838
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46569
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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To support mipi WFC.
1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU
2. add IPU/VCM/NVM/CAM1 in devicetree
BUG=b:163879470, b:171258890, b:170936728, b:167938257
TEST=Build and boot to OS. Capture frames using camera app.
Change-Id: I96f2ef682dff851d7788c2b612765a92228ddf75
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44939
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable caching of memory training data for recovery as well as normal
mode because memory training is taking too long in recovery as well.
This required creating a space in the fmap for RECOVERY_MRC_CACHE.
BUG=b:150502246
BRANCH=None
TEST=Run power_state:rec twice on lazor. Ensure that on first boot,
memory training occurs and on second boot, memory training is
skipped.
Change-Id: Id9059a8edd7527b0fe6cdc0447920d5ecbdf296e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46651
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the metaknight variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:169813211
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_METAKNIGHT
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Change-Id: Ia2e473eb1d0a2c819b874e497de0823fca75645a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add the Chrome OS specific GPIOs (WP, EC, H1, ...) GPIOs.
BUG=None
TEST=emerge-asurada coreboot; # also boots into emmc
BRANCH=None
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: Ieeeee88a09ae4c3af15e2ae93a29684d30dde493
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46386
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure and initialize EC and TPM on Asurada.
BUG=none
TEST=boot asurada
Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46385
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level"
and "Disconnect Threshold Adjustment".
COMPDISTUNE0: 0x3->0x7
TXVREFTUNE0: 0x6->0xf
BUG=b:162614573
BRANCH=zork
TEST=1. emerge-zork coreboot
2. check U2 registers are set correctly
3. test with servo v4 type-c, it's working expectedly.
4. U2 SI pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I278cc0aaddbc9fce595bf57ca69ee8abfc9f5659
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46537
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Correct the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
BUG=b:168265881
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: Id6c4f1a92d7f2ad293df7b63694e9665b85f8018
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46472
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Early JSL silicon hang while booting Linux with ISST enabled. The
malfunctioning silicon revisions have been used only for development
purposes and have been phased out. Thus, drop the ISST workaround.
Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Get rid of legacy pad macros by replacing them with their newer
equivalents.
TEST: TIMELESS-built board images match
Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Update PL1 max and min power values
BUG=None
BRANCH=None
TEST=build and verify on dralat system
Change-Id: I75d47fa721576564f71fbd5d5fd2e820fc3f1925
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Configure board specific DPTF parameters for terrador and todor
BUG=b:171019363,b:170699797
BRANCH=volteer
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add generic LPDDR4x SPD support for the following three memory
parts:
• K4U6E3S4AA-MGCR
• H9HCNNNBKMMLXR-NEE
• MT53E512M32D2NP-046 WT:F
BUG=b:170264065
TEST=none
Change-Id: Ie3163763a0ce291f27c43181d35c070c218b461d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add devicetree and device ID for P-sensor
BUG=b:161217096
BRANCH=NONE
TEST=We can get the data from P-sensor if touch the SAR antenna.
Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com>
Change-Id: I70f303995b106cca9758b36ebcde112ebcc90950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Update devicetree of boten that enable stylus
BUG=b:160752604
BRANCH=NONE
TEST=build bios and verify function for boten
Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com>
Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ied350570a695cca1424a6562e41120bcaf467797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44568
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:170703029
BRANCH=octopus
TEST=emerge-octopus coreboot
Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com>
Change-Id: I2bf642963283b8a31a3bd9504c40541ca2f64b34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
No recent Chromebooks have used I2C for TPM communication, and as a
result, a bug has crept in. The ability to extract Cr50 firmware string
is only supported via SPI, yet code in mainboard and vendorcode attempt
to do so unconditionally.
This CL makes it such that the code also compiles for future designs
using I2C. (Whether we want to enhance the I2C protocol to be able to
provide the version string, and then implement the support is a separate
question.)
This effort is prompted by the desire to use reworked Volteer EVT
devices for validating the new Ti50/Dauntless TPM. Dauntless will
primarily be using I2C in upcoming designs.
BRANCH=volteer
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
This reverts commit c4a5acdabc28778b49a1c088b0736bac83e2ab51.
Reason for revert: Dalboz is missing pull-up on cmd line, so 400khz is not possible.
TEST=Boot Dalboz
BUG=b:159823235, b:169940175
BRANCH=zork
Change-Id: I89653bfeefa522c17ee2d736215bc22aa445871c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The camera sensor component chosen for UFC and WFC have an address
conflict. Resolve it by enabling GPIO based I2C Multiplexer. Also
configure the GPIO that is used as select line.
BUG=b:169444894
TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers
are added for I2C devices multiplexed using I2C MUX under the
appropriate scope.
Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Enable the USB4 retimer driver with GPP_H10 as the power control.
Change-Id: I166bc477f94c159bb411620a6bf77b5d1f194fb2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
To support camera second source GC5035 for kodama, add world facing
camera id as part of the sku id, which is determined by the data in
camera EEPROM. For models other than kodama, the camera id is always 0
and hence the sku id is unchanged.
BUG=b:144820097
TEST=emerge-kukui coreboot
TEST=Correct WFC id detected for kodama with GC5035 camera
BRANCH=kukui
Change-Id: I63a2b952b8c35c0ead8200d7c926e8d90a9f3fb8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45811
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add new memory.c to support DDR4 memory types.
BUG=b:170604353
TEST=emerge-volteer coreboot chromeos-bootimage
Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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Update dptc setting:
Stapm_time_constant 1400
BUG=b:170696020
BRANCH=zork
TEST=emerge coreboot and check "Stapm_time_constant"
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I61d9e00a9d098ad9699b8cf89e70d11de2b95ffd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
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This patch adds some Kconfig hints to make it clearer that the
USE_QC_BLOBS option is required for SC7180 boards and guide the user in
the right direction through menuconfig. Also add those little arrows to
the Trogdor board options that are there on most other boards.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I973cae8026a229408a1a1817c4808b0266387ea7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
|
|
Berknip has SSD/eMMC SKU, we should turn off eMMC if storage is NVMe SSD.
BUG=b:170592992
BRANCH=zork
TEST=1. emerge-zork coreboot
2. Check eMMC is enabled or disabled based on the eMMC bit in
FW_CONFIG.
Change-Id: I7aeabc98fc16bc2837c8dcdc40c3c6a80898cdc9
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
|
HybridStorageMode FSP UPD needs to be set only for optane storage.
Enabling HybridStorageMode causes some extra delay in FspSiliconInit due
to HECI command and hence is avoided for NVMe and SATA scenerios. This
change disables "HybridStorageMode" for volteer baseboard. For boards
using optane HybridStorage needs to be enabled from overwrite devicetree.
We are enabling HybridStorage for volteer and volteer2 as those plaforms
have SKU's with optane storage.
BUG=b:158573805
TEST=Build and boot non optane device and confirm that FspSiliconInit
time is reduced. This saves ~100ms.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add tcc, critical, passive policy, and pl values from thermal team.
BUG=b:169215576
TEST=build and verify by thermal tool
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I4f61eaa7eab2b86b04ff0541886621afb3082b1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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Add generic wifi ACPI entry for wake on lan event.
Change configuration of GPIO 2/WIFI_PCIE_WAKE_ODL to SCI.
BUG=b:162605108
TEST=$ iw phy phy0 wowlan enable disconnect
$ cat /proc/acpi/wakeup | grep WF
WF00 S3 *enabled pci:0000:01:00.0
$ powerd_dbus_suspend
Reboot wifi router, DUT wakes up
BRANCH=zork
Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45745
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable ALS ACPI devices for dooly.
BUG=b:168426118
BRANCH=puff
TEST=Ensure that ALS devices are enabled in ACPI tables.
Change-Id: Idd44d6ae1e7b62939fdfc3a0ab01924d2c1714aa
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
Change-Id: I1e0489ec6730760f74102cdd00e4aaa66975d69a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Make output AML file name uniform.
Change-Id: Ic6cac4748a6159c695888b2737ada677d91f4262
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Create the elemi variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:170604353
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_ELEMI
Change-Id: I6013b6d8b28610a79f5ec49d373b2897799bffef
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Change-Id: I71ee54116ade4d6826dffc31ee879a70d3fc967f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This change switches all mainboard devices to use drivers/wifi/generic
instead of drivers/intel/wifi chip driver for Intel WiFi
devices. There is no need for two separate chip drivers in coreboot to
handle Intel and non-Intel WiFi devices since the differences can be
handled at runtime using the PCI vendor ID. This also allows mainboard
to easily multi-source WiFi chips and still use the same firmware
image without having to distinguish between the chip drivers.
BUG=b:169802515
BRANCH=zork
Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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1. Add speaker amplifier ALC1015
2. Enable dmic+ssp registers for speaker and camera DMIC
3. Correct I2C#2 to LVDS, I2C#3 to Touchscreen
BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status
Change-Id: I5f6f19b40c6fcce8dca9b010ae97ea6e3eeb1473
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46289
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove unused device in Dooly
no SD card reader
no built-in LAN
BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status
Change-Id: I8ab1e156031bfb4d5ea30048d8a10400f2a49411
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Dooly has USBA*2 and USBC*2
BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status
Change-Id: Icb66a8d5382ca9664e7f0b3660f446aeb3cf1dd3
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46126
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Override unused device
SD card reader, built-in LAN
ALC1015 speaker amplifier SPK_AMP_ON
Update touchscreen/lvds gpio pin
BUG=b:170273526
BRANCH=puff
TEST=Build and check DUT function status
Change-Id: Ife14adf59609870abe9f4ba1eabe2573cb6e92dd
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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GPP_A19 and GPP_A20 set no connection, disables DdiPort1Hpd and DdiPort2Hpd
BUG=b:169690329
TEST=build and verify type-c(C0/C1) port functional normally
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46069
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: TH Lin <t.h_lin@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Refactor DPTF section of code under the baseboard devicetree
and overridetree. This makes override mechanism more simpler,
because not all the DPTF fields need to be overridden.
BUG=None
BRANCH=None
TEST=Built and tested on dedede system
Change-Id: I8e7cfe60c010ed4c07f9089325b289519e861f84
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I35dc4be65f0843c3c74695c443dd958676e6c12c
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Allow MRC training in SaGv low, mid and high frequencies.
TEST=Verify memory trains at low, mid and high SaGv point
through FSP debug logs enabled.
Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45196
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix typo for power limit values under comment section in baseboard
BUG=None
BRANCH=None
TEST=Build for volteer system
Change-Id: I879b9587e863360bf4efda4099d96b42b904377e
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add trackpad, touchscreen, and usb port to devicetree
BUG=b:160664447
BRANCH=NONE
TEST=build bios and verify theirs function for boten
Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com>
Change-Id: I057f7d15d20d1a78acd733cc5463357e9c87afb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC.
Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated
with H5ANAG6NCJR-XNC DDR4 memory parts.
BUG=b:161772961
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
successfully.
Change-Id: Ia26315479ce1a749a0f7c9e81f134f7068d7eb0b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot dirinboz, run integrity test, b:169940185
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I6bac8284b67070ff2c5838257f4ae2ead0e69c22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45934
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=WIP
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1191d73a2a3f72f99de187a946162460acbb287a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45935
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=WIP
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I2fcbe35103020c3444902c077b4985f87f970671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45936
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot on Vilboz with emmc
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I9a1e47dbee3fcc7317857d40c5418be30d755d61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45933
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ethernet hardware on jecht variants doesn't support AER, so
disable it to mitigate continuous AER timeout errors in dmesg:
> pcieport 0000:00:1c.0: AER: Corrected error received: 0000:00:1c.0
> pcieport 0000:00:1c.0: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
> pcieport 0000:00:1c.0: AER: device [8086:9c94] error status/mask=00001000/00002000
> pcieport 0000:00:1c.0: AER: [12] Timeout
Change-Id: Ieda82c6e13c2bbc4b3a051a3d2a7ae90728ccdc6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46137
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ethernet hardware on beltino variants doesn't support AER, so
disable it to mitigate continuous AER timeout errors in dmesg:
> pcieport 0000:00:1c.0: AER: Corrected error received: 0000:00:1c.0
> pcieport 0000:00:1c.0: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
> pcieport 0000:00:1c.0: AER: device [8086:9c94] error status/mask=00001000/00002000
> pcieport 0000:00:1c.0: AER: [12] Timeout
Change-Id: I0f592a21d08e79cda251e80cd1f1184c4311e9df
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46136
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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A SATA drive may be connected to SATA0.
BUG=b:162909831
BRANCH=puff
TEST=none
Change-Id: I2a4ce2f89fa6d786358e01add15f2eedfbe4b20f
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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This change drops maxsleep parameter from chip config and instead
hardcodes the deepest sleep state from which the WiFi device can wake
the system up from to SLP_TYP_S3. This is similar to how other device
drivers in coreboot report _PRW property in ACPI. It relieves the
users from adding another register attribute to devicetree since all
mainboards configure the same value. If this changes in the future, it
should be easy to bring the maxsleep config parameter back.
BUG=b:169802515
BRANCH=zork
Change-Id: I42131fced008da0d51f0f777b7f2d99deaf68827
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Use the device aliases provided by tigerlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
volteer variants.
Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44039
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, trogdor devices have a section RO_DDR_TRAINING that is used
to store memory training data. Changing so that we reuse the same
mrc_cache API as x86 platforms. This requires renaming
RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the
fmap table.
BUG=b:150502246
BRANCH=None
TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage
Make sure that first boot after flashing does memory training
and next boot does not.
Boot into recovery two consecutive times and make sure memory
training occurs on both boots.
Change-Id: I16d429119563707123d538738348c7c4985b7b52
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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1. Apply the DPTF parameters received from the thermal team.
BUG=b:169183507
TEST=build and verify by thermal tool
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I1a1a0f9e86e519ac15904fac80cf3c2299213e52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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If Cr50 is running old firmware version and hence does not ensure long
interrupt pulses, override the GPIO PM configuration.
BUG=None
TEST=Build and boot waddledee to OS. Ensure that any chip override
happens before FSP silicon parameter initialization. Ensure that the
suspend/resume sequence works fine. Ensure that the reboot sequence
works fine for 50 iterations.
Change-Id: I455c51d4a63b1b5edadbf00c786ce61b0ba1ff00
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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ALS is not stuffed in octopus boards. Hence disable ALS ACPI devices.
BUG=b:169245831
BRANCH=octopus
TEST=Ensure that ALS devices are disabled in ACPI tables.
Change-Id: I5ad28f01b0515a41b314116eb2d05c520df0f86e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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