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Glados boards do not have an exposed serial port outside
of the servo interface. Set board Kconfig so that a default
built image with Tianocore payload is bootable and doesn't
hang due to trying to send data over a non-existant serial port.
Test: build/boot google/chell with board defaults
Change-Id: Ifad6f805e66438e2c436d9fa235d9be2ecf69179
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Use it wherever the standard numbers were copied to. Bit 31 is set
at runtime unconditionally, so we don't need it here.
Change-Id: I0d853c3b8250a2c7b2d1a91985a555e4b17ad76c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39731
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Further backport the backlight-PWM handling from Skylake. Beside
configuring the PWM frequency in Hz, we also use the PCH's logic
for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux
would toggle it anyway and that might confuse our ASL code.
We assume that the 183Hz value that was set before for Slippy
variants was overridden by Linux with the 200Hz VBT value, like
it was for the Broadwell Chromebooks. So we set 200Hz for them
in the devicetrees. The calculated value for the T440p of 220Hz
seems sane and also matches the VBT.
Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Cyan has no VGA BIOS available (at least not publicly), so
remove related options. Disable SoC serial output by default,
since no production devices have this exposed, but leave it
as a user option so it can be selected as needed (eg,
for use with a Google debug servo).
Change-Id: Ic079a39ca5ad0ac653b52248244b94d4bfbd08a4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39872
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Chrome-EC/PD images for all glados variants need to be built
from the board-specific branch, not master. Including the default
board names serves no purpose and requires users to deselect
the "use built-in EC firmware" in order for the board to build.
Test: build google/chell with defaults
Change-Id: Ic10f11337b85035068cdc4fe8147413e6b7f57ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Create the sushi variant of the hatch reference
board by copying the template files to a new directory named
for the variant.
(Auto-Generated by create_coreboot_variant.sh version 3.0.0).
BUG=None
BRANCH=None
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_SUSHI
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Ie900d09ff55e695527eafe68a5a75cd4a0b6d340
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The board version is part of EC's EEPROM, select Kconfig item to enable
requesting the EC for board version.
BUG=b:152374066
TEST=Verified the mainboard version is from EC's EEPROM.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Idd8aceed83439cb500e2b03153e9f8ba93979ee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Change-Id: Icda241cfac7b428176515d7996a48cb01b1dc976
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39815
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7304b06d7bf34fb7126acfdef811481dc5cba598
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The format for VPD has changed s.t. the first NIC should
always have a zero concat to the end.
Adjust all the respective boards to shift back by one and
adjust drivers/net friends to remove the 'special casing'
of idx == 0.
Background:
https://chromeos.google.com/partner/dlm/docs/factory/vpd.html#field-ethernet_macn
V.2: Fixup a code comment typo while we are here.
V.3: Vary special casing semantics for idx==0 => default mac addr is set.
V.4: Rework to still support the legacy path.
BUG=b:152157720
BRANCH=none
TEST=none
Change-Id: Idf83cc621a9333186dabb668b22c4b78e211930a
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The concerned GPIO is configured as an open drain at the Embedded
Controller side without an external pull-up. This causes leakage in the
PP3300_A rail. So configure the GPIO to have a weak internal pull-up at
the SoC side.
BUG=b:151680590
TEST=Build the mainboard. Ensure that there are no leakages in the
PP3300_A rail.
Change-Id: I5553cf40adb92edc0fecab5c875ec8d72063ba7b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here.
Additionally add processor scope patching for P-State SSDT created by
AGESA, becasue AGESA creates the tables with processors in \_PR scope.
TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are
no errors, decompile ACPI tables with acpica to check whether the
processor scope is correct and if IASL does not complain on wrong
checksum, run FWTS
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The `link_frequency_270_mhz` setting was originally used by the native
graphics init code for Sandy/Ivy Bridge, which is long gone.
The value of this information (which board had it set) is questionable.
The only board that had an LVDS panel and set it to 0 was the ThinkPad
L520, where native graphics init was never reported to work. Also, the
native graphics init only used it for calculations, but never confi-
gured the hardware to use a specific frequency. A look into the docu-
mentation also doesn't reveal any straps that could be used to confi-
gure it.
Change-Id: Ieceaa13e4529096a8ba9036479fd84969faebd14
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39763
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The format for VPD has changed s.t. the first NIC should
always have a zero concat to the end. drivers/net supports
this with the workaround of setting the idx to 1.
The longer term fix is to adjust all the respective boards
to shift back by one and adjust drivers/net friends to
remove the 'special casing' of idx == 0.
Background:
https://chromeos.google.com/partner/dlm/docs/factory/vpd.html#field-ethernet_macn
BUG=b:152157720
BRANCH=none
TEST=none
Change-Id: I510428c555b92398a5199b346dffb85d38495d74
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.
Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10
FWTS does not return FAIL anymore on ACPI tests
Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add camera ACPI configuration for Ripto/Volteer
BUG=None
BRANCH=None
TEST=Build and boot Ripto or Volteer. Start camera app and able to
capture images.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I2b47ccd989192273a29f09bf097e12e357929334
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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This is required for PD notifications on the cros_ec driver.
BUG=b:150649744
TEST=Boot volteer with this patch and verify that PD notifier events are
being generated.
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: I2e72320b025a3dfa7412181586cb142a4503eda5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Micron memory part uses SPD Index 0.
BUG=b:152005386
TEST=Build the mainboard.
Change-Id: I990a95b13d636148f0f922fd5c6d4e489d35ed2c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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1. Configure Audio GPIOs.
2. Set i2c4 configuration.
3. Update PCH HDA configuration
TEST=Verify codecs gets listed with aplay -l command.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Yong Zhi <yong.zhi@intel.com>
Change-Id: Ic0516c7a8fee79ce17343a7f42895d6ef534fec9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add HID field in max98357a_config and allow mainboards to set it.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I22d2d078a9a4eb6ab330da8439737ff5133086d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39286
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I78f06b54a6a03d565cf86f1d7bdf37965c3f6ad0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Updating devicetree to enable ELAN touchpad and ELAN touchscreen on nightfury
BUG=none
BRANCH=firmware-hatch-12672.B
TEST=built and verified touchpad and touchscreen worked
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: Ieba6558ce3897ce2f95f51ed667465d84b4ab189
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Adds GMM into the baseboard of Octopus
For GLK, PCI device 3 is GMM according to
Document#: 569262(Glk EDS Vol-1 rev2-7)
Related to Gerrit review 39579
BUG=b:151115705
BRANCH=None
TEST=Flashed final image on Chromebook
Change-Id: I75b4a835c18c5eeb542b7f7b89deea45a31e47bd
Signed-off-by: Franklin He <franklinh@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The integrated BT is routed via USB2 port 8, add USB configuration
to support integrated BT enumeration.
Change-Id: I46d8c92ba57cd72a91ee15ef4d11f07824c29e9a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Foob360 would prefer to use different SAR values. Since Foob360
sku id is 9.
BUG=b:149362272
BRANCH=octopus
TEST=build
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I8cc5d73629990f19d2c1044debdba4990c54d07e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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Add initial support for waddledee variant board.
BUG=b:151576904
TEST=Build the mainboard and variant board.
Change-Id: I20d41fbbb78c7fd2f964a97ffebbc9c3bbfb1c5c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This is new Elan touch screen IC, which includes touch panel and USI pen.
BUG=b:151514167
TEST=build bios and verify touch screen works fine
Signed-off-by: Tommie Lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: I98801b8c31812637f71d7eaaa0f12b47901dc47a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add Palkia as a variant of Hatch.
BUG=b:150254194
BRANCH=none
TEST=none
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I6a303d9fc2be9ea358ad66cd648738187c974193
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38860
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Volteer uses 4 bits (hardware straps) to indicate what memory
configuration the board is populated with (i.e. which SPD file
to use for the populated memory). This allows for only 16
different SPDs for supporting Volteer and all future variants of
Volteer. Currently, each memory chip needs its own SPD file, so we
can only support 16 different memory chip options for Volteer and
all of its variants.
Generic SPD files are just SPD files that have been stripped down
to contain only fields that are important for the memory controller
(strips out items like vendor info, for example). Using generic SPD
files allows for more than 16 different memory options given it's no
longer a 1-to-1 mapping as similar memory modules from different
vendors can share the same generic SPD file.
BUG=b:147857288
TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto and
verify ripto boots to kernel and "cat /proc/meminfo" reports 8GB
of memory.
Change-Id: I17bd4f4a00b4e3bbaf845d6d321962c11569a186
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39423
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device.
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN - both CNVi and M.2.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Disable the BT module in bootblock and enable it in ramstage. This
allows for loading the BT firmware during reboot.
TEST=Build and boot the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0406a68ffcab2675a1aedb212cb7c8508a5b61fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39446
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable GEO SAR function.
BUG=b:150347463
BRANCH=drallion
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iace9aa0245840328aa13920512747ca7f60e85dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39467
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Provide settings for configuring the link between HD-Audio controller
and display unit for purposes of HDMI/DP Audio playback.
BUG=b:144708516, b:148385924
TEST=none
Change-Id: I225faac68729b28be65b4d8f1f83769a874f84ff
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39356
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Early ec sync needs to be disabled for EFS2 to function.
BUG=b:151115320
BRANCH=none
TEST=none
Change-Id: I384d072d9614a5cd30837f7cdfb777ad5e4f6b19
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Configure trackpad interrupt GPIO.
2. Set i2c0 configuration.
3. Add trackpad ACPI support.
TEST= Verify trackpad working. Verify I2C SCL frequency below 400Khz
on trackpad operation.
Change-Id: I52c578aef591f5be90fb709bab4c8342ea9729e6
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create new variant and build for nightfury.
BUG=b:149226871
TEST=FW_NAME="nightfury" emerge-hatch coreboot chromeos-bootimage
Change-Id: If08692f4a2d216c57499098cc0e35abd708d99d4
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Limit PcieL1Substate for RP9, RP11 for ES1 NVMe warm reboot workaround.
Reference: #613582 Tiger Lake PCH-LP Sightings Report
issue id #1409566330
BUG=none
BRANCH=none
TEST= boot to OS and check warm reboot with NVMe
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie85bf71c43427e326ef2ba674da4566f8f51495a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Enable USB ACPI driver. Add ACPI configuration for all the USB ports.
Since one of the USB ports is used for Bluetooth configure the
reset_gpio used by that port.
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3e7b8f00102c96dcc295601359d3ecfbcd1bea00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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BUG=b:150154457
BRANCH=none
TEST=Build dedede, flash and boot to kernel.
Change-Id: I7248861efd1edd5a0df0e17d39a47c168cab100e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39348
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Drallion.
Change-Id: I146068d8019859be1c27e2a8174dfe7909d42d0a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Add LPDDR3 4GB 2133MHz SPD file.
BUG=b:149226871
TEST=Build and check cbfs has the spd.bin
Change-Id: I1598774a87eecc76082286540beadaa3c26eda69
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39271
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Optane memory module shows up as 2 NVMe devices in x2 config - NVMe
storage device and NVMe Optane memory. Storage device uses rp9 and
optane memory uses rp11. This patch enables rp11. Please note that
these two share clk related pins.
Configuring pciecontroller3 to be set from 2x2. This will by done by
auto detecting optane memory: enabling HybridStorageMode.
BUG=b:148604250
BRANCH=chromeos
TEST='Build, boot and look for two NVMe devices with lspci on Volteer'
Cq-Depend: chrome-internal:2501837
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628
Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2424428
Tested-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Disable WWAN PCIe to allow WWAN enumerate as USB on Volteer.
BUG=b:146226689
BRANCH=none
TEST=lsusb shows WWAN device
Change-Id: I04e49e3ec989d20ea3469fce06051c475b0ed0c8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This is required to transmit button information from EC to kernel.
BUG=b:150830342
BRANCH=None
TEST=firmware_ECPowerButton test passes on puff
Change-Id: I10ba9d55e8997ce2412deb0613cfcaa8f24f271d
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
Change-Id: I6374bc2d397800d574c7a0cc44079c09394a0673
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37984
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=144874778
TEST=Built with Volteer recipe and verified USB functionality
Change-Id: I6cbdbd8a4f65a0fe19e3fb8d7b60b8b849f104e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Add configuration for all the PCIe Root ports and Clock Source.
Configure the Root Ports as disabled and clock sources as not used.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0a1ad7e056907e454a93f51c84e1d99f08b7bdef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39166
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This enables display for use by payload.
TEST=Build and boot the mainboard. Ensure that the screens displayed by
payload are visible.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5fcd70623b15ae39954242605e75b2c5ce02ff14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
BUG=b:150869661
TEST=Build and boot the mainboard. Trigger apreset from EC console.
Trigger reboot from AP console.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0d6dd0b4264c11f7ee0ef436cc819b0bb92974f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Leave all the GPIOs in not connected state so that they can be
configured depending on the use-case. This is done to park the GPIOs in
a known safe state. This will also help to ensure that the required
GPIOs are configured when the concerned use-cases are enabled.
Below GPIOs are configured in Native Function 1 and are required for
boot-up.
* VCCIN_AUX_VID0
* VCCIN_AUX_VID1
* AP_SLP_S0_L
* PLT_RST_L
* CPU_C10_GATE_L
* GPDs
BUG=None
TEST=Build and boot the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5293536f66a6b08c9c2d2a6281684755a0c0b1b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39114
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:147500717
TEST=none
Change-Id: I32fa27b399127dbf8608e0556c77431d2dad652d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
- declare the FPMCU interrupt to be level-triggered
- change EC_PCH_WAKE_ODL gpio to native function mode
- corrected spelling of a signal name in a comment
BUG=b:144933687, b:148179954
BRANCH=none
TEST=none
Change-Id: I62da900d0b71139e55b52d06ec09ca25106f73cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Changes allow to use the integrated panel logic (power sequen-
cing and backlight control) for more connectors. The Kconfigs
GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set
to any port, e.g.
config GFX_GMA_PANEL_1_PORT
default "DP3"
Now that the panel logic is not tied to the `Internal` port
choice anymore, we can properly split it into `LVDS` and `eDP`.
This also adds Comet Lake PCI IDs which should still work the
same as Kaby and Coffee Lake.
Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi.
BUG=none
BRANCH=none
TEST=Build and boot volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Add samsung K4UBE3D4AA-MGCR SPD as memory sku id 1.
BUG=b:148182234
BRANCH=none
TEST=none
Change-Id: Ie00c45de4d31856109cda13051a75cfa2c2548f7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
wpsw_boot is deprecated in favour of wpsw_cur. As such,
coreboot no longer needs to share "write protect" GPIO
with depthcharge.
BUG=b:124141368, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:2088434
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This commit creates a nuwani variant for Grunt. The initial settings
override the baseboard was copied from variant treeya.
BUG=b:144890301
TEST=emerge-grunt coreboot
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Id3a7fc890340e5a88ebc4b516dc2c0b085654999
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39316
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a new ripto variant based off of the volteer baseboard design.
BUG=b:148385924, b:150810535
TEST="emerge-volteer coreboot chromeos-bootimage", flash ripto image
and verify ripto boots to the kernel.
Change-Id: If7606588147500a465f16c7846e2c8429ece93ec
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
|
|
Declare variant_early_gpio_table() weak to allow override by variants.
BUG=b:148385924, b:150810535
TEST=none
Change-Id: Ife5e3b75256f71ecd763c4000fd2c7d7c927bb64
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39300
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
If the ChromeOS EC uses EC early firmware selection (EFS), the AP vboot
build must also enable EC EFS. Puff EC uses EFS, so enable it in the AP
vboot build.
BUG=b:150742950
TEST=Puff can boot with EC EFS with hardware write protect enabled
BRANCH=none
Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: I0877000b7d277106436831f2d69775c25299da9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Internalise smbios_system_sku() strong symbol inwards in the ec_skuid.c
implementation and simply wrap a call to:
google_chromeec_smbios_system_sku().
BUG=b:150735116
BRANCH=none
TEST=none
Change-Id: I05ebfc8126c0fb176ca52c307c658f50611ab6ab
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Leverage the common sku id space helper encoders.
dedede uses the non-legacy SKU ID space.
squash in,
mainboard/google/dedede: Migrate onto get fw_config helper
BUG=b:149348474
BRANCH=none
TEST=only tested on hatch
Change-Id: I0c21a748fddef0985022cb4e77a8db95d6692f4b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Leverage the common sku id space helper encoders and
set the sku id max to 0xff for legacy to ensure we
behave the same.
BUG=b:149348474
BRANCH=none
TEST=tested on hatch
Change-Id: I60a37a5f9659b8df4018872956f95e07a3506440
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Enable read SAR value from cbfs.
BUG=b:150347463
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5f27b6f7245669728e3e394e9c6a39c11bfda3b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
|
|
Only some mainboard vendors have a prompt for this option. Let's be fair
and give this ability to everyone.
Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Update memory parameters based on memory type supported by dedede
1. Update dq/dqs mappings
2. Update spd data for Micron Memory
3. Add SPD data binary files for supported memory types
4. Update other FSPM UPDs as part of memory initialization
BUG=none
BRANCH=none
TEST=Build dedede, flash and boot to kernel.
Change-Id: I7248861efd1ecd5a0df0e17d39a44c168cab200e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39136
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:149775711
BRANCH=firmware-hatch-12672.B
TEST=emerge-hatch coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I856d7b361e70b657966cd4036c79f2fedfabb766
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39126
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
This follows commit 408d1dac9e23250c0e485bbf934771f769b717c1.
Change-Id: I0c0f4ad8bf743010ebdd2d53fcf297aeab64a662
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
It provides no useful information, so it might as well vanish.
This follows commit 0142d441c63a9bb1a7955ea0ba764a2ddbc38d48.
Change-Id: Iad41d8d39c6712cebfa5245f37bc69061b5ac552
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The VBOOT code can be compiled but it asserts with:
ASSERTION ERROR: file 'src/security/vboot/common.c', line 40
Start VBOOT in bootblock to fix the assertion.
Tested on Lenovo X220:
The assertion is gone, the platform boots again.
Change-Id: I48365e911b4f43aecba3b1f950178b7ceed5b2e9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This is new elan touch screen IC, which includes touch panel and USI pen.
BUG=b:149800883
BRANCH=octopus
TEST=build bios and verify touch screen works fine
Signed-off-by: Tommie Lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: Ibec3d08cc740e398a10a5c845181318724afc70a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
|
|
Disable EPS on the SKUs that do not have it.
Change-Id: I7305097beea3484634933ab856fd084933868a10
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
|
|
Enable the GFX device for Jinlon.
Change-Id: I6ba90bf464e315ec364b6f35e7670924a2aba25a
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
|
|
Leverage the common sku id space helper encoders.
volteer uses the non-legacy SKU ID space.
BUG=b:149348474
BRANCH=none
TEST=only tested on hatch
Change-Id: Ic66908afb7abb34527b4177cfd07f03ad718317c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Leverage in Puff to avoid diskswap variants. Later this could become
part of the baseboard definition and hatch diskswap variants migrated
over to use it as well.
BUG=b:149171631
BRANCH=none
TEST=Swap between x4 NVMe drives and 2x2 Teton Glacier hybrid drives and
run lsblk, lspci, and nvme tools to confirm dynamic PCIe configuration
on Puff.
Change-Id: Ie87f0823f28457db397d495d9f1629d85cfd5215
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Leverage the common sku id space helper encoders.
BUG=b:149348474
BRANCH=none
TEST=tested on hatch
Change-Id: I96e10010fd375b127f1e10387d6f7a839bc35fdd
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure GPP_E0 as output for view angle management
Change-Id: Iad640eed855b47e365da55fa994c6a3c4c38caf9
Signed-off-by: Rajat Jain <rajatja@google.com>.
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Configure below ESPI IO decode ranges:
1. 0x200-020F: EC host command range.
2. 0x800-0x8FF: EC host command args and params.
3. 0x900-0x9ff: EC memory map range.
Change-Id: I1e450d6e45242180de715746b9852634de2669c6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Enable Internal Gfx device.
2. Configure DDI0 for EDP.
3. Configure HPD and DDC suppport for DDI1/DDI2.
4. Configure HPD GPIOs.
TEST=Verify display on EDP panel in OS
Change-Id: Ia53428af549ba01ab539f9474a6e5e79b72dff5c
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39132
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8c721c7ccba4f87d4acb9dae74213a46151fe2ed
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The indirection of names is exceedingly confusing for ultimately the single
interrupt trace of EC_PCH_WAKE_ODL between the EC gpio#74 to GPD2/LAN_WAKE# on
the PCH side.
This helps folks chase this indirection down through the code.
BUG=b:147026979
BRANCH=none
TEST=builds
Change-Id: I35d746a202dae06d2f6f1edfaa3889864b09f50d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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WWAN wake event is routed to GPP_D0 GPIO and Pen Detect wake event is
routed to GPP_C12 GPIO. Update the GPE configuration accordingly.
BUG=None
TEST=Build the mainboard.
Change-Id: Id36d2c8265a0b7ea241565f6bb723df6b37446fa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie47265527b2b81748f4f3ad744d35cb81af17b80
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: I663678a4c572fe80298f7388870d5cd403122b98
Signed-off-by: Jeff Chase <jnchase@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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Change-Id: I77c33c19b56dc9bd54e7555ce59f6a07bde3dbb6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This change creates gfx directory under drivers/ so that all drivers
handling gfx devices can be located in the same place. In follow-up
CLs, we will be adding another driver that handles gfx devices.
This change also updates the names used within the driver from
*generic_gfx* to *gfx_generic*. In addition to that, mainboard
drallion using this driver is updated to match the correct path and
Kconfig name.
TEST=Verified that drallion still builds.
Change-Id: I377743e0f6d770eed143c7b6041dab2a101e6252
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Remove MAC address pass through because when MAC address pass through setting
change to "Use dock built-in MAC address", the MAC address always keeps the VPD
value.
BUG=b:149813043
TEST=tested on sarien and the result as below.
(Option) (Result)
- Use pre-assigned MAC address : Pass
- Use Chromebook built-in address : Pass
- Use dock built-in MAC address : Pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ia85ef6ed0c4db82301375edd0968cf7dd2f62dc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Follow latest HW schematics to set GPP_G4 and GPP_G6 to NC pin.
This can save 1mW power comsumption.
BUG=b:149289256
TEST=NA
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Commit 6ae8b50 [chromeec: Depend on events_copy_b to identify wake source]
partially broke resume from suspend on Auron and Slippy variants when
multiple events exist in the EC event queue. In the case of the device
suspending manually and then subsequently having the lid closed, the device
will be stuck in a resume/suspend/resume loop until the device is forcibly
powered down.
Mitigate this by clearing any pending EC events on S3 wakeup.
Test: build/boot several Auron/Slippy variants, test suspend/resume functional
with both single and multiple events in EC event queue.
Change-Id: I7ec9ec575d41c5b7522c4e13fc32b0b7c77d20d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add initial support for waddledoo board.
BUG=None
TEST=Build the mainboard and variant board.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8ab4d52c97b1cfb5549d2fce4b931748a1b1ff1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Turn on EMMC device and enable the HS400 mode. Configure the GPIOs
associated with EMMC.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic27c68f4622eec5b2930dc38186b82d895d3f67c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Add USB port configuration in devicetree. Configure USB Over-Current (OC)
GPIOs.
BUG=None
TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I19f7563013c7d702d52b7f34a207a34abe308621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Remove MAC address pass through because when MAC address pass through setting
change to "Use dock built-in MAC address", the MAC address always keeps the VPD
value.
BUG=b:147994020
TEST=tested on drallion and the result as below.
(Option) (Result)
- Use pre-assigned MAC address : Pass
- Use Chromebook built-in address : Pass
- Use dock built-in MAC address : Pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I1f58e98187feb4e428ca75f7e82c464567528526
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Some Volteer variants might not use SPD files. Allow SPD_SOURCES in
spd/Makefile.inc to be empty.
BUG=None
BRANCH=None
TEST=Build coreboot and see that it builds without error
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I5a8231b999e16503867d3c8df571b11fa0c1f6a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'.
Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change based on google/auron that is similar to peppy.
This will be helpful for the next follow-up commit that will
add ACPI for the ambient light sensor.
Change-Id: Ib2a8356d261d211d5ed5c0b035c94ec56b9c25b3
Signed-off-by: Nicolò Veronese <nicveronese@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Follow thermal table for fine tuning.
1. Update PSV values for sensors.
2. Change PL1 min value from 4W to 5W.
3. Change PL1 max value from 15W to 12W.
4. Change PL2 min value from 15W to 12W.
BUG=b:148627484
TEST=Built and tested on drallion
Change-Id: I957d41e3c14f6dbcec8c3555382895698beabe40
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Proper VR settings will be selected by CPU SKU and cpu_pl2_4_cfg.
BUG=b:148912093
BRANCH=None
TEST=build coreboot and checked IA_TDC from TAT tool.
Change-Id: Ie471dee0c70e1831a822860c0a44455772a2b8be
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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