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2017-05-25mainboard/google/eve: Update VR config settingsV Sowmya
Update Psi2Threshold, IccMax, AcLoadline, DcLoadline VR config settings as per board design. BUG=b:38415991 BRANCH=none TEST=Build and boot eve. Change-Id: I274245821f68fb3151e5563ea0c75eaa1ad32c08 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/19826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-05-24mb/google/soraka: Update camera sensor for sorakaNaresh G Solanki
Soraka uses OV 13858 sensor. Hence update the same. Change-Id: I4dd39a25da47e379cca3f8748250b3ce1ff61e50 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-24mb/google/poppy: Update SPD dataNaresh G Solanki
Though SPD is rightly selected (i.e., H9CCNNNBKTALBR-NUD), it displays wrong part number during boot in coreboot logs. So correct part number info within the SPD. TEST= Build for Soraka & make sure part number is rightly printed. Change-Id: I67f676fb6ee9d685fa7aa41fdc4b00355e6d33c7 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19692 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-24soc/marvell/bg4cd: remove cosmos mainboard and bg4cd socAaron Durbin
The SoC code was never completed. It's just a skeleton that gets in the way of refactoring other code. Likewise, the mainboard was never completed either. Just remove them both. Change-Id: I8faaa9bb1b90ad2936dcdbaf2882651ebba6630c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19823 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-19mainboard/google/poppy/variants/soraka: Add SPD for K3QFAFA0CM-AGCFFurquan Shaikh
BUG=b:37712455 Change-Id: Ia3d13ac7c18be8fa92603b6501a2e5df476adcf0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19766 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-19mainboard/google/poppy: Fix SPD for micron MT52L256M64D2PP-107Furquan Shaikh
Fix SPD as per the vendor-provided data. BUG=b:37712790 Change-Id: Ib87c316479f4a05e64ca4acb540d7aacfa7338e9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-18google/scarlet: Enable innolux,p079zca MIPI panelNickey Yang
TEST=Boot from scarlet, and mipi panel works Change-Id: I52f8f8f966034f5273d7c2e673e5ebdd9dccf748 Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-17mb/google/eve: Remove FPC device from SPI1Duncan Laurie
This device is no longer directly connected to the SOC so it does not need to be enabled in coreboot. BUG=b:35648259 TEST=build and boot on Eve Change-Id: I4ed5a5575ce51ba5f6f48b54fab42e00134ea351 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19728 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-17mb/google/eve: Update touchpad I2C timingDuncan Laurie
The touchpad frequency was still slightly above 400kHz so tweak the timing values manually to get under the spec limit. BUG=b:35583133 TEST=verified the bus frequency with a scope to be < 400kHz Change-Id: I8bd071a8e15a791b7551ac256797e87abd6b5e5a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19727 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-17mainboard/google/poppy/variants/soraka: Enable H1 I2C TPMFurquan Shaikh
1. Add a separate devicetree file for soraka variant and add H1 node. 2. Enable H1 TPM for soraka. BUG=b:36265511 Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19519 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
2017-05-17mainboard/google/poppy: Correct I2C bus number for TPMFurquan Shaikh
TPM is on I2C bus 1. Fix that. BUG=b:36265511 Change-Id: I7fb696ca7281a0c099dd325d794dd4551cf20a53 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19710 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-17google/fizz: Configure SATAXPCIe GPIOs to use native functionShelley Chen
BUG=b:37486021, b:35775024 BRANCH=None TEST=reboot and ensure that device detects SSD Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2017-05-12mainboard/google/reef: Config needed GPIO for pull-up WALijian Zhao
This change is needed to minimize circuit level stress, by adjusting circuit voltage for proper operation. For mem config GPIO changes: To avoid leakge as those pins have internal 20K pull and 3.3K pull down on mainboard, change internal pull up to none. BUG=b:37998248 TEST=Boot up into OS and enter s0ix. Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19577 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-11google/gru: support 800M/928M frequency for bobCaesar Wang
The coreboot had no supported the different frequency for gru yet. e.g: we can't support the bob to run ddr 800M for rev3 board and run 928M for rev4 board. So, in order to support the 800M and 928M ddr frequency for bob different boards. We will use the ram_id and board_id to select the board on bob. Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/19558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-11rockchip/rk3399: enable DPLL SSC for DDR EMI test on bobCaesar Wang
Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to modulate the frequency of the Silicon Creations’ Fractional PLL in order to reduce EMI. We need to turn the DPLL spread spectrum feature on to reduce the EMI noise for DDR on bob. Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/19557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-09google/sand: Add keyboard backlight supportKatherine Hsieh
BUG=None TEST=emerge-sand coreboot chromeos-bootimage and verify the keyboard backlight can be bright and alt+f6, alt+f7 function keys can be used. Change-Id: I86a35551a9348ff6ad26dfccd3b2786282d56069 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/19479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-08mb/google/reef: enable SAR and DSARWei-Ning Huang
Enable SAR and DSAR for reef. BUG=b:37612675 TEST=`emerge-reef coreboot` Change-Id: Ie0a59f8fcc9fb104328ee6d276ecab4193ec8eb8 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://review.coreboot.org/19579 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-05mb/google/poppy: Add eMMC as thermal sensorSumeet Pawnikar
This patch adds the eMMC as one of the thermal sensor under DPTF. Also, updates few comments for better interpretation and mapping. BUG=None BRANCH=None TEST=Built for poppy. Change-Id: I6d05bb7a2f857dc5bc98227c8327b2ff1bd5b913 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/19524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-05-05Revert "google/scarlet: Enable innolux,p079zca MIPI panel"Martin Roth
This reverts commit 39b633b26d6d4cf185fbbdd5a256d0665409bd5b. Commit was accidentally pushed too early and broke the tree. I'll repush the original. Change-Id: Iaca6d43cc8fc0959565d5d151a330c0c7ba38309 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/19596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-05google/scarlet: Enable innolux,p079zca MIPI panelNickey Yang
TEST=Boot from scarlet, and mipi panel work Change-Id: Id5f81867ea50f72cc0bc13074627134e0dc198ba Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> Reviewed-on: https://review.coreboot.org/19476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-05mainboard/google/sand: Update DPTF parameters provided from thermal teamKatherine Hsieh
Update the DPTF parameters based on thermal test result. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU passive point:83, critial point:99 TSR0 passive point:60, critial point:70 TSR1 passive point:50, critial point:90 TSR2 passive point:77, critial point:90 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 4W, max to 12W, and step size to 0.2W 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 5secs Change CPU Effect on Temp Sensor 0 sample rate to 60secs The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs Change Charger Effect on Temp Sensor 2 sample rate to 30secs Change CPU Effect on Temp Sensor 2 sample rate to 120secs BUG=None TEST=build and boot on electro dut Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/19538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-05google/fizz: Enable devices under pci 1c.0Shelley Chen
Turn on device 1c.0 in order to enable devices under it. BUG=b:37486021, b:35775024 BRANCH=None TEST=Boot from NVMe Change-Id: Ide66823283c58d2bea0c9886f762f0581741affe Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19533 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-05mainboard/google/poppy: Enable MODE_CHANGE event in SCI_MASKFurquan Shaikh
This is required to ensure that SCI is generated whenever a host event is set for MODE_CHANGE. Thus, when wake from MODE_CHANGE event occurs, eSPI SCI is generated which results in kernel handler reading host event from the EC and thus causes the wake pin to be de-asserted. BUG=b:37223093 TEST=Verified that wake from mode change event works fine in suspend mode and there is no interrupt storm for GPE SCI after resume. Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jenny Tc <jenny.tc@intel.com>
2017-05-04mb/google/eve: Remove code to set keyboard backlight at bootDuncan Laurie
Remove the code that was enabling the keyboard backlight at boot since this is not desired behavior for this device. BUG=b:35581264 TEST=build and boot on Eve and ensure keyboard backlight does not turn on when booting but can still be enabled in the OS. Change-Id: I7229cf962597c0de74dc005f7afb9408f7a66f42 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-04mb/google/eve: Set SUSWARN# pin to native functionDuncan Laurie
Set GPP_A13/SUSWARN# pin mode to native function 1. This pin is tied to SUSACK# in the schematic and and is intented to be used in Deep Sx so it should not be configured for GPIO mode. BUG=b:35581264 TEST=build and boot on Eve platform, test that Deep S3 and Deep S5 are still functional. (this change should have no visible effect) Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-03google/gru: skip usbphy1 setup for Scarletphilipchen
Board Scarlet doesn't use usbphy1. BUG=b:37685249 TEST=boot Scarlet, check the firmware log, and confirm no errors about USB1 Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/19489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-03mainboard/google/poppy: Add support for cr50 I2C TPMFurquan Shaikh
1. Add support for using cr50 I2C TPM on poppy. This will not be enabled until the next build. 2. Also, configure GPIOs for SPI and I2C TPM only if the corresponding Kconfig options are set. BUG=b:36265511 TEST=Verified on a reworked board that I2C TPM communication works fine. Change-Id: I3b293b8d410a6973a6dfea393c17d0be425b6a28 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-03mainboard/google/poppy: Update GPIO table for next buildFurquan Shaikh
Update GPIO table to match the schematics for next build. Change-Id: I949a14bfaa7972f2257a0b11ee81dcb0771e2f7f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-05-01acpi: fix FADT header version for ChromeOS devicesMatt DeVillier
Haswell, Broadwell, Baytrail, and Braswell ChromeOS devices' FADT version were incorrectly set to 3, rather than the correct ACPI_FADT_REV_ACPI_3_0. The incorrect value resulted in these devices reporting compliance to ACPI 2.0, rather than ACPI 3.0. This mirrors similar recent changes to SKL and APL SoCs. Test: boot any affected device and check ACPI version reported vai FADT header using OS-appropriate tools. Change-Id: I689d2f848f4b8e5750742ea07f31162ee36ff64d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19498 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-04-29rowan: Fix default test HWID.Patrick Berny
Correct the default GBB_HWID to "ROWAN TEST 9387" BRANCH=chromeos-2016.05 BUG=b:35774871 TEST=emerge-rowan coreboot chromeos-bootimage, strings /build/rowan/firmware/image.bin | grep "ROWAN TEST" and look for 9387 in output Change-Id: I7851010305caf056958c8a6a328b0506bf2208cd Signed-off-by: Patrick Berny <pberny@chromium.org> Reviewed-on: https://review.coreboot.org/19488 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-28mainboard/google/soraka: Add support for memory configs 1,2,7 and 8Furquan Shaikh
BUG=b:37712455 Change-Id: I3209aaef774712edab5e9f656ee84bfb6917b1c1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19472 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-28mainboard/google/poppy: Add SPDs for memory config 1 and 2Furquan Shaikh
BUG=b:37712790 Change-Id: I7764b4ec55b0beea82eeb6c379ef38ceeb1fb04e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19471 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28mainboard/google/poppy: Enable separate MRC cache for recovery modeFurquan Shaikh
Enable separate MRC cache for recovery mode. This requires change in flash layout to accomodate another region for RECOVERY_MRC_CACHE. BUG=b:37682566 TEST=Verified following scenarios: 1. Boot into recovery does not destroy normal mode MRC cache. 2. Once recovery MRC cache is populated, all future boots in recovery mode re-use data from the cache. 3. Forcing recovery mode to retrain memory causes normal mode to retrain memory as well. Change-Id: I4c748a316436001c5a33754084ab4a74243e21df Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19457 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-28google/gru: tpm on bob: cr50: add irq clear/irq status for tpm irqJeffy Chen
BUG=b:35647967 TEST=boot from bob Change-Id: I756513f02ac13e159d5b8b1ac2346fa42cf3c219 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf18ed7b8fdf11594f812e5c48a2bd0fde5cb820 Original-Change-Id: I50c053ab7a6f6c14daee4fb2ab1cdcaeee2d67da Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/452286 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19434 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-28google/oak: Configure SD card detect pin with a pull-upJulius Werner
SD card detect pins should normally have a pull-up. It seems that for micro-SD cards this doesn't really matter all that much, but for the full-size slots we have on some Oak-derivatives (like Hana) it does. BRANCH=oak BUG=b:35854317 TEST=Booted Hana, confirmed that card detect no longer seemed stuck-on. Booted Elm and confirmed that SD card behavior didn't change. Change-Id: I9b20e0f6fe310e724d191e36ca0a81ab4fe5f593 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c2781eeef50f52c6f02ee9344274ddf4dcb0a946 Original-Change-Id: I428ac92efb07f94265673b04e0e0dd452649b9fd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/452861 Original-Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/19432 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-04-27mb/google/eve: switch touchpad devicetree to i2c-hid and cros_ec i2c deviceWei-Ning Huang
The new touchpad firmware uses i2c-hid instead of custom reporting protocol. The touchpad also exposed another slave address (0x1e) for kernel to communicate with the touchpad EC. Change-Id: Iecaf14f7b8aed836120569e9ade9c3115bc00264 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://review.coreboot.org/19461 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-04-27google/poppy: Enable PD MCU deviceShamile Khan
In order for PD charge events to properly notify the OS when a charger is attached we need to enable the PD MCU device and event source from the EC. Without this change the charging still happens, but the OS does not notice and update the charge state icon in the Chrome OS UI. BUG=b:35586577 BRANCH=none TEST=On a poppy board that has the VBUS rework applied, plug in a charger to either port and see charge status updated to indicate charging in the power_supply_info tool and the Chrome OS UI. Change-Id: I59dcfc1cb5d11841f56cac7f4ffe461c2f9ec52a Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/19441 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2017-04-27google/fizz: Configure HDMI HPD to use native functionShelley Chen
BUG=b:37684299, b:35775024 BRANCH=None TEST=reboot and ensure graphics are displayed through HDMI port. Change-Id: I74a664b2d42f55adfa64f292f6ede4c956e16fbf Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19451 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-27google/fizz: Enable SATA on port 1Shelley Chen
BUG=b:37486021 BRANCH=None TEST=compile coreboot and make sure sda and sdb show up in /sys/class/block. Change-Id: I11344a4a5fc7e5b5d907d25439f92744a5fb70da Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19450 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-25google/gru: change the sd power sequenceCaesar Wang
In the safety considerations, we should make sure the slot of SD is enabled first, since we want to the power switch of corresponding is powered up. The different boards have the different power switch for sdmmc. Some power switch IC need turn on delay for long time. let's move the slot power of SD to romstage and avoid explicit delays or per-board. BRANCH=none BUG=b:35813418, b:35573103 TEST=check the signal for children of gru, and boot up from sd card. Change-Id: Id164e4c4c900c6b1ca0251fc27db4cd36c56f6ff Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ea1b01cc13628033b85251dbb44407f075efdc85 Original-Change-Id: I48ab543143d3de9be46608fc12d78e09decf8d79 Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/447076 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19430 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-25google/oak: Enable dual DSI for rowan and the BOE 8-lane MIPI/DSI panelDaniel Kurtz
Unlike other oak derivatives, Rowan uses an 8-lane BOE tv097qxm-nu0 MIPI/DSI panel that requires dual DSI support. Rework oak display initialization to special case Rowan, which uses a provided edid struct for its panel, special panel backlight sequencing and needs to configure mtk_ddp and mtk_dsi to use dual dsi mode. BRANCH=none BUG=b:35774871 TEST=Boot Rowan in developer mode and see output on the panel Change-Id: I136ba5bd1ab12c4ad92995e066fc6d6cf54d0898 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19389 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-25mediatek/mt8173: Add support for Dual DSI outputJitao Shi
The MT817x display output pipeline can be configured to drive an 8-lane MIPI/DSI panel using "dual DSI" mode. For the "dual DSI" video data path, the UFO block is configured to reorder the data stream into left and right halves which are then sent by the SPLIT1 block to the DSI0 and DSI1 respectively. The DSI0 and DSI1 outputs are then synchronously clocked at half the nominal data rate by their respective MIPI_TX0/MIPI_TX1 phys. Also, update the call sites in oak mainboard to avoid build breakage. BRANCH=none BUG=b:35774871 TEST=Boot Rowan in developer mode and see output on the panel Change-Id: Id47dfd7d9e98689b54398fc8d9142336b41dc29f Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19361 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-25google/oak: Use edid_set_framebuffer_bits_per_pixelDaniel Kurtz
This helper function was introduced so that mainboards don't need to manually fill in these struct edid fields. BRANCH=none BUG=b:35774871 TEST=Boot Rowan in developer mode and see output on the panel Change-Id: Ic9404a786a28b314b710e037dcae776be4b584ca Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19388 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-24google/oak: Support cr50 over I2C on rowanVadim Bendebury
This patch enables TPM2 using cr50 over I2C for the Rowan board, and adds an mt8173 specific TPM IRQ polling function. The function relies on the appropriate EINT input configured to trigger the ready status on the rising edge. The cr50 TPM is on I2C address 0x50. The cr50 interrupt GPIO is also made available for use by depthcharge via the coreboot tables. BRANCH=none BUG=b:36786804 TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are configured to use IRQ flow control when talking to the Cr50 TPM. Change-Id: If6cdd0e39e4ac86538f27f322c55c329179ee084 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19364 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-24mainboard/google/reef: Remove DRIVER_TPM_I2C_IRQDaniel Kurtz
DRIVER_TPM_I2C_IRQ has been removed. TPM_TIS_ACPI_INTERRUPT now specifies the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine. BRANCH=none BUG=b:36786804 TEST=Boot reef w/ serial enabled firmware, verify verstage sees "cr50 TPM". Change-Id: If66a2a1d461a411e112589c84a434066d48b9399 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19410 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24mainboard/google/eve: Remove DRIVER_TPM_I2C_IRQDaniel Kurtz
DRIVER_TPM_I2C_IRQ has been removed. TPM_TIS_ACPI_INTERRUPT now specifies the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine. BRANCH=none BUG=b:36786804 TEST=Boot eve w/ serial enabled firmware, verify verstage sees "cr50 TPM". Change-Id: Ia1eacd15e71a46a37457ee2f117b156393c3393d Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19409 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24mainboard/google/reef: Add TPM_TIS_ACPI_INTERRUPTDaniel Kurtz
TPM_TIS_ACPI_INTERRUPT specifies the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine. BRANCH=none BUG=b:36786804 TEST=Boot reef w/ serial enabled firmware, verify verstage sees "cr50 TPM". Change-Id: Ic69add8a3ce35be64fb37db4ed40163f6144fc9c Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19408 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24mainboard/google/eve: Add TPM_TIS_ACPI_INTERRUPTDaniel Kurtz
TPM_TIS_ACPI_INTERRUPT specifies the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine. BRANCH=none BUG=b:36786804 TEST=Boot eve w/ serial enabled firmware, verify verstage sees "cr50 TPM". Change-Id: Ifeb09a0a35bff7cd9091f6d027f0065288ca35c9 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19407 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24mainboard/google/poppy: use intel common tis_plat_irq_status()Aaron Durbin
Utilize the intel/common code for tis_plat_irq_status() to remove dependencies and code duplication on for bringing up a board requiring tis_plat_irq_status(). Change-Id: I2aaa1d7d3ce171dc1788438ff9990fce533deb6c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19371 Tested-by: build bot (Jenkins)
2017-04-24Kconfig: provide MAINBOARD_HAS_TPM_CR50 optionAaron Durbin
The CR50 TPM can do both SPI and I2C communication. However, there's situations where policy needs to be applied for CR50 generically regardless of the I/O transport. Therefore add MAINBOARD_HAS_TPM_CR50 to encompass that. Additionally, once the mainboard has selected CR50 TPM automatically select MAINBOARD_HAS_TPM2 since CR50 TPM is TPM 2.0. Change-Id: I878f9b9dc99cfb0252d6fef7fc020fa3d391fcec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19370 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-24mb/google/fizz: Set lid status as openNaresh G Solanki
Lid switch is not available. Hence report lid state as always open. Change-Id: Ia9c82c3ad323912bad51cf55ed80a37b3110b1ef Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19219 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-24mb/google/fizz: Configure PCI root portNaresh G Solanki
Configure PCI root port as per schematic. Change-Id: I10ef682e8c54e22f328db5105d4da39c72ac2bed Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/19390 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-24google/fizz: Configure memoryShelley Chen
Read DRAM SPD and populate MemorySpdPtr fields in UPD data structure for FSP. BUG=b:36490168, b:35775024 BRANCH=None TEST=./util/abuild/abuild -p none -t google/fizz -x -a We are currently working on bringup and have no hardware to test on yet. Change-Id: I191cc6bf1fd8aa461855c538b48fd39e3ffd7848 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/19205 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-24*.asl: Remove obsolete reference to TPM ASL filePatrick Rudolph
TPM ACPI entries are automatically generated, and the old static TPM ASL file is obsolete. Remove the reference to this obsolete static and empty ASL file. Delete src/drivers/pc80/tpm/acpi/tpm.asl. Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19291 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-20mainboard/google/eve: Set touchpad IRQ to level triggeredDuncan Laurie
This commit changes the interrupt configuration for the touchpad to be level triggered so it matches what the device is actually using. When the system wakes from suspend by way of touchpad interrupt, or there is touchpad input while in suspend that does not wake the device (when the device is in tablet mode) the interrupt edge is not seen by the AP so the driver does not handle the event and the touchpad keeps the interrupt asserted and does not send further interrupts. The end result is a non-functional touchpad after resume until it is reset or the driver is reloaded. This happens because the touchpad is actually treating the interrupt as level triggered and expects the kernel driver to read a data packet over I2C before it will de-assert the pending interrupt. BUG=b:35774857 BRANCH=none TEST=Test that the system can reliably wake from suspend by touchpad event via the EC and continue to have a functional touchpad after resume. Change-Id: Iaf7c04d9bc9d945bdcc196dff54c92a2a68368f3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19382 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19google/gru: change kevin boot-time center logic voltage to 925mVDouglas Anderson
Kevin's center logic isn't super clean so it needs 925 mV for center logic. All newer gru variants only need 900 mV. BRANCH=gru BUG=b:37429075 TEST=Reboot tests Change-Id: I8c3bd6c245700b23c27cd5758c35c9993f801cb4 Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/479463 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19357 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-19google/gru: change center logic voltage to 900mVDerek Basehore
It seems that we should only ever run at 900mV on center logic. Changing it to 950mV before might have just masked over problems that are now fixed. BRANCH=none BUG=chrome-os-partner:56940 TEST=on kevin, run stressapptest -M 1536 -s 1000 Change-Id: I5a09b1b403df800396bb2f2e8c76d14a4519d44a Signed-off-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/391032 Reviewed-by: Douglas Anderson <dianders@chromium.org> Commit-Queue: Lin Huang <hl@rock-chips.com> Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/19356 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-19mainboard/google/poppy/variants/soraka: add soraka boardYH Lin
Create Soraka board which derives from Poppy, a KBL reference board. More Soraka specific changes need to be done later on. BRANCH=master BUG=b:36995255 TEST=Build (as initial setup) Change-Id: I8af68d2cf475df56336aa0e3bebe86a54ece1999 Signed-off-by: YH Lin <yueherngl@chromium.org> Reviewed-on: https://review.coreboot.org/19343 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-19mainboard/google/poppy: Provide nhlt variant APIFurquan Shaikh
Move current NHLT configuration implementation to baseboard so that variants can leverage it or provide their own configuration. BUG=b:37375693 Change-Id: I2a4317c112f9e3614bd01eb6809727b73328d29d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19326 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide memory configuration variant APIFurquan Shaikh
Add support for memory configuration by providing weak implementation from the baseboard. All SPD files are present under spd/ directory. SPD_SOURCES must be provided by the variants to ensure that required SPD hex files are included in the SPD binary. BUG=b:37375693 Change-Id: Ic9bcc03d5a35bebd14061680f264ac072b3c0634 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19325 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide cros_gpio variant APIFurquan Shaikh
Add support for ChromeOS GPIO ACPI table information by providing weak implementation from the baseboard. BUG=b:37375693 Change-Id: I641afe6bb45f106ddebde081a8ac2c64278ebeb9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19324 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Add variant API for board_id and gpioFurquan Shaikh
Provide APIs for board_id() and gpio table functionality. Default weak implementations are provided from the baseboard. BUG=b:37375693 Change-Id: Ic3c946e6cb12b3c8ef3e83a1037ed0fc8cffbded Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19323 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide baseboard and variant conceptsFurquan Shaikh
In order to be able to share code across different poppy variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/poppy - code variants/poppy/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:37375693 Change-Id: If6c1c5f479cfffe768abf27495d379744104e2dc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19322 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Prepare sharing directory for variantsFurquan Shaikh
Clean up Kconfig file in order to support variants for poppy. Add BOARD_GOOGLE_BASEBOARD_POPPY that can be set by various poppy variants to use the common baseboard configs. BUG=b:37375693 Change-Id: I399ecc8c3efb3af26e1fcf60fe2c75b24769fc0f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19321 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mb/google/poppy: Add camera supportV Sowmya
Add camera related support * Enable the SA Imaging Unit and CIO2 devices. * Enable TPS68470 PMIC and populate related ACPI objects. * Enable OV cameras and populate related ACPI objects. * Enable Dongwoon AF DAC and populate related ACPI objects. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that ACPI tables have the required entries for all the camera devices. Change-Id: Ifbe878bb6b25fc976e935fee16c4d59fadd47fe2 Signed-off-by: Sowmya V <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18969 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-19mb/google/poppy: Add Image Processing Unit ASLSowmya
This patch includes ipu.asl file in the main DSDT definition to add ACPI entries for IMGU and CIO2 devices. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that DSDT table has the entries for IMGU and CIO2 devices. Change-Id: Ib7485315cb9468da7c6aa090862657a265121493 Signed-off-by: Sowmya V <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/19110 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-18mainboard/google/poppy: Clean up gpio.h fileFurquan Shaikh
1. Update formatting of gpio table to fit everything within 80 column limit. 2. PEN_RESET gpio is non-existent. Get rid of it. BUG=b:37375693 Change-Id: I1bcc4168659f365547e5f7227df8659e4bc7f243 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-18mainboard/google/poppy: Enable deep S3 in DC modeFurquan Shaikh
Enable lower power state when running on battery. Deep S3 is not enabled when in AC mode to support standard "docked" config. BUG=b:36087058,b:36723679 TEST=Verified following behavior with USB mouse: 1. If AC is connected when entering S3, USB mouse is able to wake up. 2. If AC is not connected when entering S3, USB mouse does not wake up. 3. If AC is connected when entering S3 and removed after entering S3, USB mouse does not wake up. 4. If AC is not connected when entering S3 and attached after entering S3, USB mouse does not wake up. Change-Id: I141a8d4779de004e27fcd9357cef787a38a27b24 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19276 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-15google/slippy: fix internal mic for falco/wolf variantsMatt DeVillier
The HDA verb for falco/wolf's internal mic was wrong, preventing the mic from working properly in Windows and macOS (the Linux driver overrides the verb table, so wasn't affected). Set the verb connector/jack bits properly, to no connector / no jack detect, in order to fix. Also, make (2) small non-functional fixes: On falco, NID 0x1A was being disabled twice (instead of 0x1A and 0x1B both being disabled - copy/paste error). On wolf, NID 0x19 was set to an internal analog mic, where it should have been disabled (again, copy/paste error). Both these errors were introduced when consolidating/upstreaming and were not present in the original Chromium sources. Test: boot Windows [8/8.1/10] and verify mic functional with Realtek drivers on both falco and wolf. Change-Id: I9c343dda4762f0b1f814318c155e22c59d2da8db Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19262 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-15mainboard/google/eve: Remove 'probed' setting from rt5663 codecDuncan Laurie
Remove the 'probed' setting from the Realtek 5663 headset codec I2C device. This was added when we had a hardware issue that was preventing I2C operation because the clock/data lines were swapped. With new and/or reworked hardware this is no longer a problem and we do not want the I2C layer in the kernel to talk to the device before the rt5663 driver. BUG=b:35585307 BRANCH=none TEST=Boot on Eve and verify rt5663 driver still loads properly. Change-Id: Ice38889e8f5d3fd1307056cab10fbe3f4e197749 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19304 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-14google/slippy: clean up NGI and move to libgfxinitMatt DeVillier
- remove old, buggy NGI code from falco/peppy variants - remove superfluous INTEL_DP/INTEL_DDI configs, since already selected by northbridge/haswell - always use libgfxinit when use native init config selected - enable NGI/libgfxinit for all slippy variants The reset of the old Haswell NGI code will be cleaned up in a subsequent patchset. Test: select MAINBOARD_DO_NATIVE_VGA_INIT, observe panel init using SeaBIOS and Tianocore payloads on peppy, wolf variants Change-Id: Id5727cad7f714ffa57e77e2a25505e3c28f55237 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18824 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-04-14mainboard/google/eve: Remove ACPI ALS deviceDuncan Laurie
Remove the ACPI ALS device from the EC configuration because this system has an ALS that is presented through the new EC sensor interface rather than the legacy ACPI interface. BUG=b:37179776 BRANCH=none TEST=Boot an Eve device and ensure that 'acpi-als' device is not present in /sys/bus/iio/devices. Change-Id: Ie18b8a661e4d16464784ca8a227586036e7631de Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19265 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-14mainboard/google/eve: Set UART0 to skip initialization in FSPDuncan Laurie
Set UART0 to "PchSerialIoSkipInit" so the pins for this device are not set back to native mode by FSP when configured as GPIO input by coreboot. Now that FSP is not touching the pins I also removed the workaround to reconfigure the pins after FSP. BUG=b:35647877 BRANCH=none TEST=Verify that GPP_C8-GPP_C11 are configured as GPIO input once the OS is booted and they are not set back to native function by FSP. Change-Id: Ifec4fa3e66ceeb660bad00c66bc7bd44bb457a01 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19264 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-14mainboard/google/eve: Enable internal pull-down on USB_C{0,1}_DP_HPDDuncan Laurie
These lines act as inputs to both EC and AP and when the corresponding TCPC mux is in low power mode the line is floating. Add an internal pull-down to each GPIO to prevent it from floating in this state. BUG=b:35775012 BRANCH=none TEST=Verify that the kernel does not see a device present on DP when the TCPC mux is in low power mode. Change-Id: Ie229f84871e9994467c0ab660cc7e271a51d9cbb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19263 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-13mainboard/google/reef: Configure sdcard card detect (CD) pin GPIO_177Venkateswarlu Vinjamuri
This configures GPIO_177 as native function. This enables OS to boot from sdcard. BUG=b:35648535 TEST=Check OS boot from sdcard. Change-Id: I73901d4a1b39752cbc452f3286d494587dac95d4 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18948 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-04-13mainboard/google/snappy: Increase weida touchscreen reset delayWisley Chen
Weida touchscreen controller needs 130 ms delay after reset BUG=b:35586513 BRANCH=reef TEST=Verified that touchscreen works on power-on and suspend/resume on snappy. Change-Id: I8418e742a69a2d6395baa2799a4da42a9bb5b312 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/19245 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13google/eve: Disable Deep S3 in AC modeDuncan Laurie
In order to support a standard "docked" config disable Deep S3 when connected to AC power. This allows USB devices to wake the device from suspend if it is externally powered, but still retains the lower power state when running on battery. BUG=b:36723679 BRANCH=none TEST=manual testing on Eve for USB wake behavior: 1) when suspended on battery USB keyboard does not wake 2) when suspended while connected to AC a USB keyboard does wake 3) if suspended with AC, and then AC is removed, system does not wake with USB keyboard 4) if suspended without AC, and then AC is added, system does not wake with USB keyboard (it cannot get enabled without waking and re-suspending) Change-Id: I670e39d42cdb5b80612206da899be82ef3b2cbf2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19240 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13google/eve: Enable WiFi SAR featureDuncan Laurie
Enable the Intel WiFi SAR feature for Eve, which will be used to provide wifi power tables based on values read from VPD. This is enabled based on CONFIG_CHROMEOS because it relies on the presence of VPD code from vendorcode/google/chromeos. BUG=b:36727652 BRANCH=none TEST=test on Eve by setting "wifi_sar" in VPD and ensuring that the ACPI WIFI device gets the expected "WRDS" and "EWRD" tables with the values that were set in VPD. Change-Id: I11c129baca891221177575108ac09ba1707b516e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19241 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13soc/intel/skylake: Split AC/DC settings for Deep Sx configDuncan Laurie
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled in both DC and AC states. However since using Deep S3 disables some expected features like wake-on-USB it is not always desired to enable the same state in both modes. To address this split the setting and add a separate config for Deep Sx in AC and DC states. All motherboards that set this config were updated, but there is no actual change in behavior in this commit. BUG=b:36723679 BRANCH=none TEST=This commit has no runtime visible changes, I verified on Eve that the Deep SX config registers are unchanged, and it compiles for all affected boards. Change-Id: I590f145847785b5a7687f235304e988888fcea8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19239 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13mainboard/google/poppy: Enable internal pull-down on USB_C{0,1}_DP_HPDFurquan Shaikh
These lines act as inputs to both EC and AP. Thus, add internal pull-downs to prevent them from floating. BUG=b:35648530 Change-Id: I42326c810775d5449e99e52e81870970247ce335 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19243 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13mainboard/google/poppy: Add support for cr50 SPI TPMFurquan Shaikh
Put all configs required for enabling cr50 SPI TPM on poppy under POPPY_USE_SPI_TPM so that it can be enabled any time for testing SPI TPM on this board. Also, add required callback for irq status and devicetree config for GSPI0. BUG=b:36873582 Change-Id: I67793093c006c1325fc16f669a96126525f83243 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19238 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-11scarlet/gru: skip display because mipi driver not readyShunqian Zheng
Scarlet don't have eDP and MIPI driver is not ready, skipping display for now or else Scarlet would be stuck in reading eDP HPD because there even not power for it. TEST=boot to kernel on Scarlet Change-Id: I02ab4ef21bf77b98414f537aca57b46c11922348 Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/19237 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-11google/eve: Limit memory SKU 5 to 1600MHzDuncan Laurie
Due to issues with stability limit the SKU with K4EBE304EB-EGCF memory to 1600MHz instead of 1866MHz. BUG=b:37172778 BRANCH=none TEST=pass stress testing on devices with this memory Change-Id: I02af7e9c35e2c5b0b85223d58025cbd29841d973 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19227 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10google/eve: Update I2C bus timingDuncan Laurie
Update the I2C rise/fall timings based on newly measured values on a new board with updated pull-up resistor values. Touchscreen: rise time 98ns, fall time 38ms Touchpad: rise time 111ns, fall time 41ns TPM: rise time 112ns, fall time 34ns BUG=b:35583133 BRANCH=none TEST=Each I2C bus frequency was verified on a scope to be ~400MHz Change-Id: Ibb3a15fa0cc862f36c1b9c63ac7847221020c4c0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19202 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-083rdparty/libgfxinit: Update submodule pointerNico Huber
Some renamings force us to update our code: * Scan_Ports() moved into a new package Display_Probing. * Ports Digital[123] are called HDMI[123] now (finally!). * `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`. Other noteworthy changes in libgfxinit: * libgfxinit now knows about ports that share pins (e.g. HDMI1 and DP1) and refuses to enable any of them if both are connected (which is physically possible on certain ThinkPad docks). * Major refactoring of the high-level GMA code. Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/18770 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-06gru: Initialize I2C bus for ARC2C0608Philip Chen
BUG=b:35583511 TEST=check i2c bus 0 initializes from ap console log Change-Id: Ibb6709159f5ed28ad0b62397d2ddb504dec55167 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/19105 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-05mainboard/google/reef: increase trackpad data hold timeAaron Durbin
Even though the i2c spec has no minimum data hold time in fast mode the trackpad vendor indicates 300ns is their minimum. However, the topology of the board uses FET isolation to cross voltage domains. Therefore, the default 300ns which should work isn't reflected on the device side of the voltage isolation circuit. Therefore, increase the data hold time to show an observed data hold time of more than 300ns on the device side. BUG=b:36469182 Change-Id: I1b70f2f53c5a29cc7cfd5035a71ca5811b3bcba0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19065 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-05mainboard/google/poppy: Change SD card detect to GPP_E15Furquan Shaikh
SD card detect pin is moved to GPP_E15 in the next build. Update device tree and gpio config accordingly. BUG=b:36012095 Change-Id: Ic0ff72cdcb0f1ca27abc7eb8da9ccd8a21b28522 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19107 Tested-by: build bot (Jenkins) Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com>
2017-03-29mainboard/google/reef: turn off DMIC_CLK_B1 in S0ixSathyanarayana Nujella
Wake On Voice stream capture configuration is mono. It is sufficient to keep DMIC_CLK_A1 on in S0ix; so, turning off DMIC_CLK_B1. Power saving should be visible in the boards which has more than one DMIC connected. BUG=None BRANCH=None TEST=WoV and quad channel DMIC capture works Change-Id: Ic46d4c7b30b945eba47a05d78386f48e4a675a03 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/19018 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Tested-by: build bot (Jenkins)
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28chromeos / broadwell / jecht: Make save_chromeos_gpios() jecht-specificJulius Werner
This callback was only required for a single mainboard, and it can easily be moved to mainboard-specific code. This patch removes it from the global namespace and isolates it to the Jecht board. (This makes it easier to separate vboot and chromeos code in a later patch.) Change-Id: I9cf67a75a052d1c86eda0393b6a9fbbe255fedf8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18981 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-28vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by defaultJulius Werner
The virtualized developer switch was invented five years ago and has been used on every vboot system ever since. We shouldn't need to specify it again and again for every new board. This patch flips the Kconfig logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the latter for Lumpy which seems to have been omitted incorrectly, and hide it from menuconfig since it's a hardware parameter that shouldn't be configurable.) Since almost all our developer switches are virtual, it doesn't make sense for every board to pass a non-existent or non-functional developer mode switch in the coreboot tables, so let's get rid of that. It's also dangerously confusing for many boards to define a get_developer_mode() function that reads an actual pin (often from a debug header) which will not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set. Therefore, this patch removes all those non-functional instances of that function. In the future, either the board has a physical dev switch and must define it, or it doesn't and must not. In a similar sense (and since I'm touching so many board configs anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC. Instead, it should just be assumed by default whenever a Chrome EC is present in the system. This way, it can also still be overridden by menuconfig. CQ-DEPEND=CL:459701 Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18980 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Remove VBOOT_DYNAMIC_WORK_BUFFER Kconfig optionJulius Werner
VBOOT_DYNAMIC_WORK_BUFFER and VBOOT_STARTS_IN_ROMSTAGE are equivalent in practice. We can't have a dynamic work buffer unless we start in/after romstage, and there'd be no reason to go with a static buffer if we do. Let's get rid of one extra option and merge the two. Change-Id: I3f953c8d2a8dcb3f65b07f548184d6dd0eb688fe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18979 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Select SoC-specific configuration for all Chrome OS boardsJulius Werner
Some Chrome OS boards previously didn't have a hardcoded vboot configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE, etc.) selected from their SoC and mainboard Kconfig files, and instead relied on the Chrome OS build system to pass in those options separately. Since there is usually only one "best" vboot configuration for a certain board and there is often board or SoC code specifically written with that configuration in mind (e.g. memlayout), these options should not be adjustable in menuconfig and instead always get selected by board and SoC Makefiles (as opposed to some external build system). (Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for Pistachio/MIPS was never finished. Trying to enable even post-romstage vboot leads to weird compiler errors that I don't want to track down now. Let's stop pretending this board has working Chrome OS support because it never did.) Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19022 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-27ec: Use EC_ENABLE_LID_SWITCH for all mainboards with LID using chromeecFurquan Shaikh
Instead of defining a separate LID device for mainboards using chromeec, define EC_ENABLE_LID_SWITCH for these boards. Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18964 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-27mainboard/google/rambi: Move SIO_EC_ENABLE_PS2K to onboard.hFurquan Shaikh
Instead of defining SIO_EC_ENABLE_PS2K by default for all boards and doing an undef in variant/onboard.h, move the definition of SIO_EC_ENABLE_PS2K to variant/onboard.h. This avoids dependency between different *.asl files. Change-Id: I83e4ce42a594e952a443c618d7ef9840113027b9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18965 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-24mainboard/google/snappy: Update DPTF settingsWisley Chen
1. Remove CPU throttling effect of the charger sensor Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965 (mb/google/reef: Remove CPU throttling effect of the charger sensor) to remove CPU throttling effect of the charger sensor since it's not relevant to throttle CPU based on the charger sensor. 2. Change TSR1 influence from 200 to 100 3. Change TSR2 sample period from 120s to 30s BUG=b:35585781 BRANCH=reef TEST=built, and verified on snappy by thermal team. Change-Id: Ic3fc51c4288b24f4e64950e5b148aed4495a1c3b Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-03-23google/fizz: Update device tree from schematicShelley Chen
BUG=b:35775024 BRANCH=None TEST=Compiles successfully Change-Id: I92cf9baa4c3aefc6983511543d875e74a6b0bf94 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/18944 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-23google/fizz: Transfer gpio from schematicShelley Chen
Transfer the gpio assignments in the fizz schematic into gpio.h. BUG=b:35775024 BRANCH=None TEST=./util/abuild/abuild -p none -t google/fizz -x -a Change-Id: If05aa2859f2511c3f616dc3fb38bca4fb8524697 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/18797 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-23google/fizz: Remove poppy-specific configsShelley Chen
- Remove spd files/directory - Remove audio blobs - Remove dptf.asl contents - Remove MKBP - Remove acpi table initialization BUG=b:35775024 BRANCH=None TEST=Compiles successfully Change-Id: I5d717d23224956ee1653c5ded28abd05cd254c3a Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/18857 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 14:28:08 +0000