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2019-08-07mb/google/hatch: Kohaku: Add touchscreen controller to device treeTim Wawrzynczak
The touchscreen controller was never added to the device tree, and the next board rev will have this IC connected. Set it up in the device tree with conservative power resource timings from the datasheet. BUG=b:138869702 BRANCH=none TEST=compiles; current board rev does not have touch IC Change-Id: I759fb32f31c8eee0e6bd664c6a82308354ef5d08 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07mb/google/kohaku: Enable stylus pen deviceSeunghwan Kim
Enabling stylus pen device and pen_eject event. - Adding enable_gpio for power sequencing - Configuring GPP_H4 and GPP_H5 as native function - Adding PENH device node for pen ejection event BUG=b:137326841 BRANCH=none TEST=Verified pen input operation and pen_eject event (pop-up and wake from s0ix on pen ejection) Change-Id: Ic252a1f90c0fc6cb9b1e426d75a8b503824681f3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-07mb/google/octopus: Add custom SAR value for VortininjaWisley Chen
Vortininja needs different SAR values than meep. Use sku-id to load SAR values. BUG=b:138261454 BRANCH=octopus TEST=build and verified SAR values by sku id Change-Id: I7b3ab51e1d6cada4faaba1b9d72bd9eacf6b04dd Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-08-05mb/google/helios: Set SPKR_PA_EN PIN high for boot beepSubrata Banik
This patch makes SPKR_PA_EN PIN output and high for boot beep to work in pre-os environment. BUG=b:135104721 BRANCH=NONE TEST=Boot Beep is working with required ALC1011 depthcharge code changes. Change-Id: I012462f93e9e2bcafe5f18ce7d04e3fcd1db9ffa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
2019-08-05mb/google/octopus: Add EMRight digitizer supportWisley Chen
The device Vortininja uses the variant meep, and supports WACOM/EMRIGHT digitizer. BUG=b:138276179 BRANCH=octopus TEST=verified that WACOM/EMRIGHT digitizer can works. Change-Id: I2bed4edb0261953f122f1d9ccca1fe4fa9406b33 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-08-05mb/google/drallion: Add new mainboardThejaswani Putta
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake. BUG=b:138098572 Test=compiles Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05mb/google/sarien: Increase Wacom touchscreen reset delay to 120 msCasper Chang
Increase reset delay to 120ms of touchscreen to meet wacom touchscreen T4 specification and resolve re-bind hid over i2c driver failed after touchscreen firmware auto update. BUG=b:132211627 TEST=Stress touchscreen firmware auto update 200 times and not found re-bind driver failed. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I488660aefdc6df27077efc7fec2f3b99adbaef9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/34665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com> Reviewed-by: Nick Crews <ncrews@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-08-03mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold timeFrank_Chu
After adjustment Touch Pad CLK: 383.4 KHz Touch Screen CLK: 381.6 KHz Audio codec CLK: 386.0 KHz TouchPad SDA hold time: 0.325ns BUG=b:137722634 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-03mb/google/octopus: Add custom SAR values for droid/blorbSheng-Liang Pan
droid/blorb needs to use different SAR values than bobba. Use sku-id to load the SAR values. BUG=b:138091179 BRANCH=octopus TEST=build and verify SAR load by sku-id Change-Id: I71b5d69ffbba82018a682202df73b604332dd9e7 Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34542 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-03mb/google/hatch: Enable PmTimerDisabled config to reduce S0ix power usageSubrata Banik
BRANCH=none BUG=b:138152075 TEST=Build for cometlake board with the PmTimerDisabled policy in devicetree set to 1. With PmTimerDisabled = 0 >> iotools mmio_read8 0xfe0018fc 0x00 With PmTimerDisabled = 1 >> iotools mmio_read8 0xfe0018fc 0x02 Bit 1: ACPI Timer Disable (ACPI_TIM_DIS): This bit determines whether the ACPI Timer is enabled to run. - 0: ACPI Timer is enabled - 1: ACPI Timer is disabled Change-Id: I83f49505a804c99d7978e5d541ea9fe8ead9b88f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-08-02mb/google/hatch: Fine-tune Kohaku I2C CLK frequencyPhilip Chen
Add rise time / fall time to I2C config in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). BUG=b:138258384 BRANCH=none TEST=probe I2C0/I2C2/I2C3 SCL on Kohaku board, verify all of them run at 395-399 kHz. Change-Id: Id98079e717f0db3fdcb88f85e45693925d11d7fd Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34559 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/intel/icelake: Make use of common thermal code for ICLSubrata Banik
This patch ports CB:34522 and CB:33147 changes from CNL to ICL. TEST=Build and boot dragonegg Change-Id: I0b983005f16fe182e634eac63fef4f6b22197a85 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34649 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/intel/skylake: Make use of common thermal code for SKLSubrata Banik
This patch ensures skylake soc is using common thermal code from intel common block. TEST=Build and boot soraka Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/hatch: Initialize SSD GPIOs in bootblockShelley Chen
Moving these to bootblock as we are seeing some instances where devices are rebooting into the recovery broken screen with the 0x5a error (no bootable storage device in system). This needed to be done for KBL platforms and never got transferred to hatch. Please reference https://review.coreboot.org/c/coreboot/+/23647 BUG=b:137681648 BRANCH=None TEST=Run autotest faft_bios and faft_ec suites Change-Id: I8cf09c26d77d890f5d0490709504e9edf485a93f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34484 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2Seunghwan Kim
Applying first tuned DPTF parameters and TDP PL1/PL2 values for kohaku. More fine-tuning will happen later. BUG=b:1704071 BRANCH=none TEST=build Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34397 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/hatch/variants/hatch: Set PCH Thermal Threshold value to 77 deg CSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled. BUG=133345634 BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Hatch. Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33147 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/kukui: Enable config for coreboot displayYongqiang Niu
BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I478e06686158dd77b075bcef8a41763ae26c79f9 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31521 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/octopus: Override DDI1 DDC SDA/SCL for HDMIWisley Chen
The device Dorp uses the variant Meep, and supports HDMI. -sku33 (HDMI) -sku34 (HDMI + keyboard backlight) -sku35 (HDMI + Touchscreen) -sku36 (HDMI + keyboard backlight + Touchscreen) BUG=b:136522841 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I59ba2e56cf2f83ca9d533454570bcdd39c0a2e7c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34509 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/octopus: Override VBT selection for DorpWisley Chen
For dorp HDMI sku, select VBT which enables HDMI output. -sku33 (HDMI) -sku34 (HDMI + keyboard backlight) -sku35 (HDMI + Touchscreen) -sku36 (HDMI + keyboard backlight + Touchscreen) Cq-Depend: chrome-internal:1502253 BUG=b:136522841 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I62262378f85bb899073ffac7804be876e649e429 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-07-30mb/google/hatch: Enable chipset_lockdown coreboot config for hatchSubrata Banik
This patch enables lockdown configuration for hatch family (hatch, kindred, helios and kohaku) BUG=b:138200201 Change-Id: Ia6dc90156dc76fde490b25cf833da3cf80f664f2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-30mb/google/hatch: Add option to enable WiFi SAR configsFurquan Shaikh
This change adds a user selectable option to enable all WiFi SAR configs that apply to hatch. BUG=b:138177048 Change-Id: I4b72f90896841e7c556d4a1b8cdad8ca89d01021 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-29mb/google/octopus: Add keyboard backlight supportWisley Chen
Dorp device support keyboard backlight, so enable it. BUG=b:138413969 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: If0c7b22b4be2a5d5216404a6944ac887883e9a47 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com>
2019-07-26mb/google/hatch/helios: Update GPIO and device treeTim Wawrzynczak
Based on updated schematics, change polarity of USI_INT, and add the reset and enable GPIOs to the touchscreen ACPI node. The stop GPIO can't be used with the current implementation of _ON, as the way it's wired will cause power sequencing to fail. BUG=b:137133194, b:138240502 BRANCH=none TEST=Compiles, don't have next board rev to test with Change-Id: I1dfb8e649418e4c5e9b897fb4bc11393adc21ea2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-25mb/google/poppy/variant/nami: add sku ids of bardRen Kuo
add two sku ids of bard: 0x1009CE0 0x1009CE2 BUG=b:137892804 TEST=emerge-nami coreboot Change-Id: I299ccb36739d83e38f37e0b2cbba44c34343c975 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__Kyösti Mälkki
Use explicit simple PCI config accessors here. Change-Id: Ifa3814fdd7795479ca5fdbfc4deb3fe8db9805f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-23mb/google/octopus/variants/fleex: Remove gpio NC setting for enabling I2C0Frank Wu
Enable I2C0 in fleex then verify EMR function successfully BUG=b:135968368 BRANCH=octopus TEST=EMR function working normally with I2C0 in Grob360S. Change-Id: I784ff32418bc839bcec14fbfd7236f708828690e Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-07-23mb/google/hatch: Add FP MCU to helios device treePhilip Chen
BUG=b:136606255 Change-Id: I8fa29dc96e7a066f6708ede6b7bee2382c7008cb Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21mediatek/mt8183: support more EMCP LPDDR4X DDR bootupHuayang Duan
Support SANDISK SDADA4CR-128G, SAMSUNG KMDP6001DA-B425, KMDV6001DA-B620 EMCP LPDDR4X DDR bootup. BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM Change-Id: I7de4c9a27282d3d00f51adf46dcb3d2f3984bfff Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-07-21mb/google/kukui: Introduce a new 'Jacuzzi' familyHung-Te Lin
The 'Jacuzzi' is a different base board that will share most of Kukui design. For AP firmware, there will be only a few changes expected, mostly in display (for MIPI bridge) and EC/keyboard so we want to create it as variants inside Kukui folder, not forking a new directory. BUG=b:137517228 TEST=make menuconfig; select 'krane' and build; select 'jacuzzi' and build. Change-Id: Ic2b04e01628dc3db40f79f9bbdd5cc77d9466753 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34344 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21soc/intel: Expand SA_DEV_ROOT for ramstageKyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21mb/google/hatch: Remove hatch_whlPhilip Chen
Hatch_whl variant is deprecated. BUG=b:137180390 Change-Id: I88fa201398ad5fb70da48d022f1ae86fecafa660 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34432 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-21mainboard/google/kahlee: create treeya variantChris Wang
This is based on the grunt variant. BUG=b:135551210 BRANCH=none TEST=emerge-grunt coreboot chromeos-bootimage Ensure that image-treeya.*.bin are created Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I40f3c9de87350777b02dd91d8c5b9dbe2eb9f6b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-21mb/google/hatch/var/kindred: Implement variant_devtree_update()David Wu
This change provides an implementation of variant_devtree_update() for kindred that disable eMMC controller when SKU ID = 1 or 3 BUG=b:132918661 TEST=Verify eMMC is disabled when SKU ID = 1 or 3 Change-Id: I8ccb4dae54f223881e0ced9e034bf45b994cc6f2 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-21mb/google/hatch: expose get_board_sku() as globalDavid Wu
BUG=None TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I217e13acd337034554ff055e8bf5011558d1f8bf Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21mb/google/hatch: Add support for variant_devtree_update()David Wu
This change adds support for variant_devtree_update() that allows variant to update device tree. BUG=None TEST=emerge-hatch coreboot chromeos-bootimage Change-Id: I0e9ad360b6c02c83fe49387ce7bc66d56448ffb9 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21mb/google/eve: Enable wake from MKBP events in S3Aseda Aboagye
We would like to wake eve up in suspend from an MKBP event. This commit simply enables MKBP events to wake the system in suspend using the existing host event interface. There is an accompanying series of patches in the EC firmware for eve that will allow a MKBP wake mask to be configured. BUG=chromium:786721 BRANCH=firmware-eve-9584.B TEST=Build and flash eve, generate MKBP events on the EC and verify that the system wakes up in suspend. Change-Id: I75b05c83a4204d55df11589299a7488d04bbd073 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34454 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19mb/google/octopus: Disable unused USB devicesKarthikeyan Ramasubramanian
Disable unused USB devices in the device tree so that the concerned ACPI objects do not get exported to the OS. BUG=b:133513961 BRANCH=octopus TEST=Boot to ChromeOS. Ensure that the USB devices are disabled based on port status and the concerned ACPI objects are not exported. Change-Id: I0faccdfb8a9df9ec52130437433b15973e3d6f1a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-19mb/google/octopus: Add ACPI configuration for USB devicesKarthikeyan Ramasubramanian
Add devicetree configuration for USB devices so that USB Port Capabilities (_UPC) and Physical Location of Device (_PLD) ACPI objects can be exported to the OS. BUG=b:133513961 BRANCH=octopus TEST=Boot to ChromeOS. Ensure that the _UPC & _PLD ACPI objects are exported for the configured USB devices in the SSDT table. Change-Id: I832ffe305d256296b7447035c5e5dcafb7c296d9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-19google/nocturne: Add MKBP events as a wake sourceAseda Aboagye
We would like to wake nocturne up in suspend from an MKBP event. On Nocturne, MKBP events are notified to the host via a GPIO from the EC, EC_INT_L. However, the AP cannot wake from suspend from this GPIO. Therefore, we'll use the host event interface to wake the system instead. This commit simply enables MKBP events to wake the system in suspend. BUG=chromium:786721 BRANCH=firmware-nocturne-10984.B TEST=Build and flash nocturne, generate MKBP events on the EC and verify that the system wakes up in suspend. Change-Id: I6aff4d38051c939257533229fd0085e42c01d02f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2019-07-19sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supportedPatrick Rudolph
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-19mb/google/hatch: Fix SD card is detected as read only issueSubrata Banik
This patch configures GPIO pin GPP_G7 as NF1 with internal pull down. As per schematics SD host controller SD_WP pin is not connected to uSD card connector. Configured gpio pin as NF1 with internal pull down in order to overcome gpio default state in hatch which makes SoC SD_WP pin is enable. BUG=b:137729527 BRANCH=None TEST=Able to write/read data to/from sd card after mounting card device. Change-Id: I0187267670e1dea3e1d5e83d0b29967714d6065e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34396 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-19mb/google/helios: Add ALC1011 in device tree to enable speaker ampsSathya Prakash M R
Following changes are done to enable ALC1011 codec on Helios 1. ACL1011 4 devices to I2C4 2. GPIO H13 is set to GPO as per schematics Verified SSDT table and i2cdetect from kernel. Signed-off-by: Naveen Manohar <naveen.m@intel.com> Change-Id: I0d71e3bd2d4493d059a33023c1afe1b630181d4f Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-18soc/intel: Use config_of_path(SA_DEVFN_ROOT)Kyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I53324603c9ece1334c6e09d51338084166f7a585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18mb/google/hatch/var/helios: Implement variant_memory_sku()Furquan Shaikh
This change provides an implementation of variant_memory_sku() for helios that overrides memory ID 3 and 4 to 0 and 1 to workaround the incorrect memory straps in hardware for board id 0 and unknown. BUG=b:133455595 Change-Id: I38fab1f91decac5d0a146e5a6c74e88f677af305 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-18mb/google/hatch: Add support for variant_memory_sku()Furquan Shaikh
This change adds support for variant_memory_sku() that allows variant to return memory SKU ID. Current implementation of memory_sku() is renamed to weak implementation of variant_memory_sku(). Functionally this change should be the same as before for all hatch variants. This function will be overriden by helios in a follow-up CL. BUG=b:133455595 Change-Id: I509c263ec08e0060c12ef1ea9fed673f1e3f3a41 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-18mb/*/*/gpio: Use static for const structuresPeter Lemenkov
Autoport generates these structures as static so let's make it consistent. See also commit 128205fd with Change-Id I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7 ("autoport/bd82x6x.go: Improve gpio.c generation"). Change-Id: I4e07bd755ca4a65b76c69625d235a879fe7b43cb Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33524 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18mb/google/hatch: Add FP MCU to kohaku device treeShelley Chen
BUG=b:137654283 BRANCH=None TEST=Make sure can see FP MCU spidev in dmesg on bootup Change-Id: Iffa13f29e1abdf430e8dc4a0ee1a931a9e69168c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34371 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-18mb/google/hatch: Disable wireless chargingSubrata Banik
This patch makes VGPIO_3 GPIO PIN output and low independent of cnvi is connected or not. BUG=b:123062346 BRANCH=None TEST=boot up Hatch device and make sure VGPIO_3 gpio pin is driven low. Change-Id: I629b99676f56747de1b244724709e14069250097 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34376 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16mb/google/hatch: Disable Bluetooth in bootblock and enable in ramstageShelley Chen
Currently, bluetooth FW is not loaded after a reboot. In order to do this, we have to disable the bluetooth disable gpio (GPP_C14) in bootblock and re-enable it in ramstage. BUG=b:137307516 BRANCH=None TEST=boot up Hatch device and make sure (in dmesg) that proper bluetooth FW in loaded Change-Id: Ic5e447d9de57790f7a100e9e03f36b047c19d8f9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34354 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16mb/google/octopus/variants/garg: support LTE power sequenceMarco Chen
GPIOs related to power sequnce are GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:137033609 BRANCH=octopus TEST=build image and verify on the DUT with LTE DB. Change-Id: I7bf6fee087c885c22363b44aa98aa61f91be90b4 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-07-16mb/google/octopus: add variant_smi_sleepMarco Chen
Allow variants to customize their own smi sleep flow. BUG=b:137033609 BRANCH=octopus TEST=built Change-Id: I75db544d333a640848da9072878687c802c1c1a4 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34340 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-16mb/google/octopus: add variant_early_override_gpio_tableMarco Chen
Allow variants to override GPIO configurations of baseboard in the bootblock stage. BUG=b:137033609 BRANCH=octopus TEST=built Change-Id: I18d380cdf58f0f24e1bb1bff394ed8a91188a22c Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-07-16mediatek/mt8183: add a new configuration for KodamaPeichao Wang
These configuration files can be used to build Kodama firmware. BUG=b:135490566 TEST=check variant: kodama via make menuconfig; make -j Change-Id: I72e80e800ba041df1dda2b0f84470d1ef58bc946 Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33616 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-15mb/google/sarien/variants/arcada: Set data hold time for touchpadCasper Chang
Elan's touchpad requires min 0.3us data hold time. To fine tune the data hold time of i2c1 to meet specification of Elan's touchpad. BUG=None BRANCH=None TEST=Verified data hold time of i2c1 is around 320ns Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I0fa9db3b50e74f193261be96bd9e305bb19841e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Crews <ncrews@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-07-13mb/google/hatch: Fix trackpad configuration in overridetreeFurquan Shaikh
Hatch and variants use GPP_A21 for trackpad IRQ and wake. Fix overridetree.cb to advertise the right IRQ. Change-Id: Ib87c858b89e8726c3bc80f83be0729ef4625268e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34248 Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13mb/google/octopus: Add custom SAR values for BluebirdSeunghwan Kim
Bluebird needs to use different SAR values than Casta. Bluebird sku id is 2. CQ-DEPEND=CL:*1435310 BUG=b:129725065 BRANCH=octopus TEST=build Change-Id: I107a8519832fcf906b94f958a3dc508d19bb4727 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34080 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch: Update AC/DC loadline valuesRizwan Qureshi
Update the AC/DC loadline values for all domains. Using the same values as in arcada. BUG=None BRANCH=None TEST=Build and Boot hatch EVT Change-Id: If8ea48794d11dc68e40e6504c0d46a2b273a8ab6 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11google/kukui: Adjust LCM ID voltagesYu-Ping Wu
Currently some of the LCM ID voltage gaps are below 100mV. For example, the voltage difference between ID 2 and 3 is 503-440=63mV. To reduce the risk of misrecognition from the hardware level, the voltages are adjusted so that all the voltage gaps are larger than 100mV. The RD2 resistor values are also updated. BUG=b:136987483 TEST=emerge-kukui coreboot Change-Id: Ib5c1f927fb54d8c9579f030e42eeec5a27daaceb Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34192 Reviewed-by: You-Cheng Syu <youcheng@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11board/kukui: Remove ADC tolerance from boardidHung-Te Lin
The tolerance of ADC is +-10mV, but the resistors may also introduce 1% variation, and causing the final measured voltage to vary around 5%. By the advisory from hardware team, checking the tolerance seems not really solving or helping anything so we should just ignore that and try to find best matched ID (this also aligns to what Gru did). BUG=b:136990271 TEST=Booted on Krane and no longer seeing ADC out of range BRANCH=None Change-Id: Ie02ca5aaafbcfa8f411d973ad0266eee385d6878 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34161 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: You-Cheng Syu <youcheng@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch/variants: Fix nonworking touch padFrank_Chu
Correct ELAN Touch pad IRQ GPIO to GPP_A21 BUG=b:135507215 BRANCH=none TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I60816a4652fa39ab2a91034b268efe8f84a13e17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33954 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-11mb/google/hatch: Enable/disable GPIO clock gatingTim Wawrzynczak
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off. BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called. Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-11mb/google/hatch: Enable LPIT inclusion in DSDTTim Wawrzynczak
Include the lpit.asl file in Hatch's DSDT definition. BUG=b:130764684 BRANCH=none TEST=S3 suspend/resume and S0ix entry/exit work correctly. Ran > 200 iterations of suspend_stress_test and no issues found. Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-11mb/google/hatch: Disable GPIO community dynamic clock gatingTim Wawrzynczak
The dynamic clock gating is causing boards to miss interrupts whose pulses are shorter than 4us. Disable it using FSP UPDs. BUG=b:130764684 BRANCH=none TEST=Compiles Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-11mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L)Furquan Shaikh
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since it needs to trigger on both edges. With GPIO IRQ, it is necessary to configure the trigger type in coreboot to match the ACPI configuration. This is because: 1. ACPI configuration is used by intel-pinctrl driver in Linux kernel to re-configure the trigger type for the pad in GPIO DW0 config register. This is done when kernel driver probes and requests irq for its device. 2. On resume from S3, the pad configuration gets reset and coreboot sets the trigger type to LEVEL. However, kernel driver does not probe again. This results in the trigger type being configured incorrectly. This change updates the GPIO configuration for GPP_H0 to set the same trigger type as advertised in ACPI for the kernel. BUG=b:132672011 TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0 works fine on boot as well as after suspend/resume. Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-10mb/google/octopus: Remove LPDDR4 RAMID index 5,6 CH[1] only SKUKevin Chiu
From Intel EDS: Table 3-5. LPDDR4 Configurations CH00 CH01 CH10 CH11 "x32 BGA" "x32 BGA" "x32 BGA" "x32 BGA" "x32 BGA" "x32 BGA" "Unpopulated" "Unpopulated" CH[1](CH10/CH11) can't use alone without CH[0] BUG=b:135498646,b:136694293 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: I03af74301aad3e688c97992b37c59b20a4fff58a Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34069 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-08mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen andFrank Wu
increase reset off delay time Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power sequence. Increase reset_off_delay time from 1ms to 3ms to met the HW requirement. BUG=b:135287161 BRANCH=None TEST=local build and measure sequence with Goodix touch screen Change-Id: I33140869990aa4715c780b0fa322921e450530ef Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33808 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07mb/google/hatch: Update GPIO settings for SD card and SPI1 Chip selectKrishna Prasad Bhat
This patch updates the following GPIO settings. 1. Set Native termination for GPP_G0 - G4 SD card pins. 2. Set GPP_B19 to NF1. BUG=b:123907904 TEST=Verified SD card functionality on hatch. Checked for SD detection, transferred files to and from SD card. Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-07mb/google/hatch/var/kindred: Add Raydium touchscreen supportDavid Wu
Add Raydium controller BUG=b:135728282 BRANCH=master TEST= 1. FW_NAME="kindred" emerge-hatch coreboot chromeos-bootimage 2. boot up on kindred DUT to check touchscreen device by evtest /dev/input/event3: Raydium Touchscreen 3. Raydium TS is working Change-Id: Id963300ab0dadcb78786c5a1328c2a4098a48a05 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33857 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07mb/google/hatch/var/kindred: Update ELAN GPIO/IRQ and add Synaptics TouchpadDavid Wu
Update ELAN GPIO and IRQ setting and add Synaptics Touchpad BUG=b:132708463 BRANCH=None TEST=Verify ELAN/Synaptics touchpad is working fine. Change-Id: I883ce2e50ca5c6bd2b1ca76cbe24177055cc5d60 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-07mb/google/hatch/variants/kindred: Enable eMMC supportDavid Wu
Enable eMMC support for kindred. Cq-Depend: chromium:1666982 BUG=b:135464155 BRANCH=none TEST=Boot kindred onboard eMMC. Change-Id: I040af6da30313f8dd59e3ef910b290922e090cdc Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33618 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev paramFurquan Shaikh
This change gets rid of unused dev param to pmc_set_afterg3. BUG=b:136861224 Change-Id: Ic197d6fb8618db15601096f5815e82efc2b539c1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-03mb/google/octopus: Override DDI1 DDC SDA/SCL for Garg HDMIKevin Chiu
garg 2A2C DB: SKU ID - 1 garg HDMI DB: SKU ID - 9 garg LTE DB: SKU ID - 17 For HDMI SKU9, GPIO needs to be overriden to enable DDI1 DDC SDA/SCL. BUG=b:134912735 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: I6ad8e5aa52f503121b10fe353e4bf4021aee2061 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-07-03mb/google/octopus/variants/fleex: Enable EMR function for Grob360SChris Zhou
Enable EMR Pen Stylus function for Grob360S BUG=b:135968368 BRANCH=octopus TEST=EMR function working normally with HW reworked Fleex. Change-Id: Ia220dc0d3051b79b110b4df66df108f701776478 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33802 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-03mb/google/octopus: Add custom SAR values for BlooguardTony Huang
Google project name is Bloog. Bloog is 12-inch LCD. Blooguard is 14-inch LCD so would prefer to use a different SAR values instead. Use sku-id to load the SAR values. BUG=b:135078377 BRANCH=octopus TEST=build and verify SAR load by sku-id Change-Id: Id80df28a961eb1f62714558df2b219aa552ecb97 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-07-02mb/google/hatch: Set trackpad irq and wake to GPP_A21Shelley Chen
Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for trackpad interrupts due to ITSS not honoring the INVERT config. Now that's fixed, we can configure trackpad wake and interrupts on GPP_A21 only. BUG=b:130436471 BRANCH=None TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad 2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure through "mosys eventlog list" that the wake source is the trackpad.\ 3. Run "echo mem > /sys/power/state", wait until device goes into S3, click trackpad to ensure device wakes. Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-02mb/google/hatch: Add INVERT to all IOAPIC padsShelley Chen
Now that ITSS config is fixed, we can set the IOAPIC pad configs correctly. BUG=b:123967687 BRANCH=None TEST=Make sure Hatch is booting and tested out trackpad to make sure can move cursor and wake by clicking on the trackpad after running powerd_dbus_suspend. Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33819 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02mb/google/reef/variants/: fix Samsung K4F6E3S4HM-MGCJ densityKevin Chiu
Samsung K4F6E3S4HM-MGCJ density is 16Gb BUG=b:121228792 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage MemTotal: 8041964kB in /proc/meminfo Change-Id: Ie8ecd82b92d4e82d3955cf773febca30f6280a5e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-06-28mb/google/kohaku: Correct trackpad i2c addressSeunghwan Kim
Correct i2c address of trackpad. It should be 0x20. BUG=None BRANCH=None TEST=Verified trackpad works on pre-evt system Change-Id: I7ded21ce8ff9e907e436777a27edb4273512011d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-06-26mb/google/hatch: Add a GPIO to enable/disable FPMCU powerPhilip Chen
A FPMCU power-control pin (GPP_C11) is added to the latest hatch reference schematic. Even though this is not implemented in hatch rev1 board, the future hatch family boards with FPMCU should all have this control pin. On the old boards without this control pin, GPP_C11 is a floating TP, and thus this patch should be backward-compatible. BUG=b:130307667, b:135216932 TEST=build Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: I6a84eeb6aab562258e749a8a5d09dadfa0e43587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-26mb/google/hatch: Remove pulls on NC padsFurquan Shaikh
There is no need to add internal termination (PU/PD) on the not-connected pads. This change gets rid of the terminations on the NC pads. Change-Id: I3df538d7127e5ef75e6e6ff9db3524e26f0450ed Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-06-26mb/google/hatch/variants/baseboard: Update PL2 power limit valueSumeet Pawnikar
Update PL2 power limit value from 44W to 64W. BUG=None BRANCH=None TEST=Build and Boot hatch EVT Change-Id: I3f4b5ab8bf0ce9464c322c148843f5a3e8d706d9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-06-25atlas: enable GEO_SARCaveh Jalali
BUG=b:131634035 BRANCH=none TEST=verified SAR data shows up in ACPI SSDT table. Change-Id: I65ef59c9616b1cae3fa4c4b18bbfe4ed098d2891 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-21mediatek/mt8183: support SAMSUNG and MICRON EMCP LPDDR4X DDR bootupHuayang Duan
Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR From the calibration log of MICRON MT29VZZZAD8DQKSL, we found the begin pass range of RX window earlier than with other DDR type. So need change the DQS starting offset to increase the scan range of RX window. BUG=b:80501386 BRANCH=none TEST=Boots correctly on EMCP DRAM Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>
2019-06-21mb/google/octopus: Override VBT selection for GargKevin Chiu
Garg proto build has 3 SKUs: garg 2A2C DB: SKU ID - 1 garg HDMI DB: SKU ID - 9 garg LTE DB: SKU ID - 17 For SKU#9, VBT will need to be overridden to enable DDI_C output to HDMI BUG=b:134912735 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Cq-Depend: chrome-internal:1380847 Change-Id: I6c0ec086496eaf217ea8e326f5084d886d0e698f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-06-21mb/google/octopus: expose get_board_sku as globalKevin Chiu
BUG=b:134912735 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: I1fb7b5eeac48f2cd9c24fa1d3ac3fe4b390762d2 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33448 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21mb/google/hatch/variants/kindred: Update memory strap GPIOsDavid Wu
According to the latest schematic (b:127996858#comment38), MEM_CONFIG_0 --> GPP_H19 MEM_CONFIG_1 --> GPP_H22 MEM_CONFIG_2 --> GPP_F10 MEM_CONFIG_3 --> GPP_F3 BUG=none BRANCH=none TEST=Boot kindred proto board Change-Id: Ib79f9454116583a94fe1fd53a37ed928d32988d5 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-06-21sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetreeArthur Heymans
Set up generic decode ranges based on the devicetree settings. Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-21soc/intel/skylake: Clean up KconfigArthur Heymans
This does the following: - select MAINBOARD_USES_FSP2_0 on Kabylake (does not support FSP1.1) - Remove stale Kconfig option on intel/saddlebrook - select SOC_INTEL_KABYLAKE on intel/kblrvp Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-21qcs405: Update bootblock sizeNitheesh Sekar
Increase the size of bootblock from 96K to 128K. Change-Id: Ifc6e7239ed2978a8490fa229945ebd5ed9182298 Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33159 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21mb/google/hatch: Do not pull down GPP_F2 internallyPhilip Chen
There is already an external pull-up/down resistor tied to this pin to identify if the board is single-channel or dual-channel memory SKU. BUG=b:135496271 BRANCH=none TEST=build Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: Ie218657fd9dde113ab26cf5551d1dff1b6e392b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-21google/kukui: Increase SPI flash speed to boot fasterMengqi Zhang
Increase SPI flash speed from 26MHz to 56MHz and set correct tick_dly to get faster boot process. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: I8f44883b4f4a198146330caf5420dc39d5592a0a Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32462 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21mediatek: Add SPI tick_dly settingMengqi Zhang
Add spi tick_dly setting for high-speed spi xfer. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21mediatek/mt8183: Add SPI GPIO driving settingMengqi Zhang
Set SPI GPIO driving to support SPI FLASH. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: I95002ec71abd751c33c089185db04ed4a8686699 Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32460 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21google/kukui: Enable RTCYou-Cheng Syu
Enable RTC so that we can see correct timestamp in CrOS eventlogs. BUG=b:134461866 TEST='mosys eventlog list' shows correct timestamp on Kukui Change-Id: Ie9ef7c9343c781e348429cd5376a4a5519641e16 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-06-21google/kukui: Revise FMAP firmware layoutHung-Te Lin
Adjust FMAP sections that - ELOG only needs 4K (by driver limitation) - SHARED_DATA only needs 4K or less (for netboot params) - SMMSTORE is probably not needed since UEFI@ARM is not available yet - VPD can be smaller (most x86 devices have only 16/8K for RO/RW) - Increase RW_LEGACY to 1M (recommended value) - Move all new saved space to CBFS BUG=b:134624821 TEST=Built Kukui image and boots on Rev2 units. Change-Id: Id2910df73ea47bfa32e056d631d1c3e5f1eed0d1 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-21mb/google/snappy: Remove unneeded 'else'Elyes HAOUAS
'else' is not needed after a 'break' or 'return'. Change-Id: I7b6c319a58b9f4f47de19336d18d00b73d3d3772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vlado Cibic Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-21mediatek/mt8183: Calibrate vsim2 to 2.7 VHsin-Hsiung Wang
The default voltage of vsim2 is set to 2.76V for sim card usage. In general, 2.76V of vsim2 is composed of 2.7V main voltage and 0.06V calibration voltage. However, vsim2 is used for the tx_ovdd power of display port IT6505 on the kukui board design which needs 2.7V. So we set it to 2.7V with modifying calibration value. BUG=b:126139364 BRANCH=none TEST=measure vsim2 voltage with multimeter Change-Id: I4dffdde89cbde91286d92e6c2b445f0b3d0ad2fe Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-20mb/google/hatch: Remove unused USB2 port5 from baseboard devicetreeAamir Bohra
Hatch newer board revision do not use USB port5 for discrete BT. Hence remove the port configuration and UBS2 P5 asl entry. The older board version would continue to use USB2 P5 hence moved the entry to overridetree.cb Change-Id: I98297d6b81e3184b7b0a14710f3790f5df30d68b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-06-19grunt: Change Bayhub eMMC base clock to 200MHzRaul E Rangel
The clock was previously set to 52MHz to workaround the fact that depthcharge didn't support tuning. Tuning has now been enabled in depthcharge: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/1655553 BUG=b:122244718 TEST=Verified on grunt that it speeds up boot by 130ms Change-Id: If847cea2a7848bcd175958db86e652d4f710201a Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 08:39:33 +0000