| Age | Commit message (Expand) | Author |
|---|---|---|
| 2016-11-03 | google/veyron*: change .ddrconfig from 14 to 3 | ZhengShunQian |
| 2016-11-03 | google/veyron*: add DDR configs for new samsung DDR | ZhengShunQian |
| 2016-08-01 | Add newlines at the end of all coreboot files | Martin Roth |
| 2016-01-22 | google/veyron_*: Add dual-rank 2GB Hynix module to SDRAM configs | David Hendricks |
| 2015-08-28 | veyron: add Nanya NT5CC256M16DP sdram | jinkun.hong |
| 2015-04-22 | google/veyron_*: add ELPIDA F8132A3MA and FA232A2MA sdram | jinkun.hong |
| 2015-04-22 | google/veyron_*: update sdram-ddr3-samsung-4GB.inc | jinkun.hong |
| 2015-04-21 | veyron: add new SDRAM configuration with ram-code 1101b | ZhengShunQian |
| 2015-04-21 | veyron: The ODT function is disabled for LPDDR3 | jinkun.hong |
| 2015-04-21 | veyron: Sync up SDRAM configurations | Julius Werner |
| 2015-04-15 | google/veyron_*: Remove unused sdram-ddr-hynix-2GB.inc | huang lin |
| 2015-04-15 | Brain: Initial mainboard import | David Hendricks |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |