| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-08-18 | cpu/intel: Enter romstage without BIST | Kyösti Mälkki |
| 2019-03-06 | Remove DEFAULT_PCIEXBAR alias | Kyösti Mälkki |
| 2018-08-01 | mb/google,samsung/*: Add LPC TPM chip driver to devicetree | Matt DeVillier |
| 2017-07-24 | Update files with no newline at the end | Martin Roth |
| 2017-06-04 | google/slippy: populate PEI SPD data for all channels | Matt DeVillier |
| 2017-05-31 | google/slippy: add board-specific USB port info | Matt DeVillier |
| 2017-02-20 | google/slippy: consolidate variants' common mainboard.asl code | Matt DeVillier |
| 2016-12-05 | Add/Combine Haswell Chromebooks using variant board scheme | Matt DeVillier |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |