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Because Markarth PCIe port 1 use for eMMc not SD. So we need override
PCIe config for Markarth. And also the Markarth have NVMe and eMMC
SKU. Follow Winterhold to look at the NVMe CLKREQ signal before
initializing the ports allowing us to identify which device is populated
and only initialize that device.
BRANCH=none
BUG=b:275669215
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I0b4e4067a30019d742c7589a52badf93b7091615
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74133
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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On Skyrim, there isn't a need for a sleep GPIO table. Remove the TODO
and filler table and function to reduce unnecessary function overhead.
BUG=None
BRANCH=Skyrim
TEST=Build Skyrim BIOS image.
Change-Id: Ia9d55a5e2295bb2e2c2957c4f5207362f616022c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Having L1.2 enabled on the SD port increases the kernel resume times by
between 30 & 40ms. This patch disables L1.2 on SD to get that time
back.
As with needing to have hotplug enabled on the SD card, this seems like
a driver issue, so hopefully that will get sorted out and this patch
can be reverted.
BUG=b:274025743
TEST=resume times are decreased.
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2c409fa2cd66c712c5ba7104635499d63fa0d2be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Use die_no_apcb to cause a build error when the APCB or SPD sources are
not found.
TEST=builds with and without matching APCB and SPD sources
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I62dce2c71061bfc5c01e0344b7dc115a47669140
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This sets the location of the skyrim MP2 firmware within the mainboard's
blobs directory, and adds the Kconfig option to the mainboard directory
so that it can be enabled in a saved .config file.
The skyrim MP2 firmware is skyrim specific, so it should not be placed
in the main PSP AMD_BLOBS directory.
We will also only want to enable the MP2 firmware for chromeos builds as
it's not useful for non-chromeos builds.
BUG=b:259554520
TEST=Build MP2 firmware into image, see that it gets loaded
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I04be6f2d0b605d4eca37fd927a70310259dc106c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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set pwr_on_varybl_to_blon to 0x1c, which means fw will delay 112ms
between backlight on and vary backlight.
BUG=b:271704149
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table;
measure the power on sequence on whiterun
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ib966d2ebd4ef4a8085695901ec5da160f467e32e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add UPD usb3_port_force_gen1 for skyrim
The default setting is set to disable
Skyrim -> set default as disable
BUG=b:273841155
BRANCH=skyrim
TEST=Build, verify the setting will be applied on skyrim.
Change-Id: Id53bed82a9fef93b574c3f30830555e02d7f4737
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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It seems like the hotplug enable might be doing more than just enabling
devices to be hot-plugged, so re-enable the feature for the SD card.
Removing it from SD increased resume time and may have caused reboot
issues for SD after resume.
This is a partial revert of CB:73512
BUG=b:273620322
TEST=See resume time go down on Skyrim
BRANCH=Skyrim
Change-Id: I4814d4377d0ba8a1e9b308853b3e02a4a27bd8d5
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73868
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Enable Frostflow platform to send the fuse SPL (security patch level)
command to the PSP.
BUG=b:274028833
BRANCH=none
TEST=FW_NAME="frostflow" emerge-skyrim coreboot chromeos-bootimage
Then get "PSP: SPL Fusing Update Requested." in the firmware log.
Change-Id: I6437d5324877702f2f8b4c69d4c850543e1b74be
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73884
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This will be tracked directly in the bug, so a code comment is not
needed.
BUG=263161283
TEST=none
BRANCH=Skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4d5af35762354c8825d30f813098547a7e009e35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73828
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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We're not going to move the AMDFW binary around at this point, so get
rid of the TODO.
BUG=None
TEST=None
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If802c3ee19f4e6a3a74da49bbda55f6a89fa8060
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73827
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Because Mendocino doesn't support PCIe Gen4, PSPP on this platform does
not save any power, so leave it disabled.
BUG=273889287
TEST=None
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1a1c6692cd0a44469a35582042b92eeec31073fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Follow thermal team's request on b/248086651 comment#32. Update the
thermal table setting for each mode and the conditions of temperature
switching.
BUG=b:248086651,b:241180483
TEST=emerge-skyrim coreboot
Change-Id: Ibcf6c110029d39bdc6bfaf46c234a4073ee69f30
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
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Add new memory MT62F2G32D4DS-026 WT:B to replace H9JCNNNBK3MLYR-N6E．
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
MT62F1G32D2DS-026 WT:B 2 (0010)
MT62F2G32D4DS-026 WT:B 3 (0011)
K3LKBKB0BM-MGCP 4 (0100)
BUG=b:273177939
BRANCH=None
TEST=emerge-skyrim coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I545bd8d9f88e7b3055acef4066769e6fcb766cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73681
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If recovery APCB is not passed, amdfwtool will build amdfw*.rom with
AMD_BIOS_APCB_BK entry pointing to the same offset as AMD_BIOS_APCB
entry. This will help to save 40 KiB flash space in each FW slot. On
ChromeOS, this means saving ~120 KiB flash space.
BUG=b:240696002
TEST=Build and boot to OS in Skyrim.
Change-Id: Ib3bbc1eededae20b2cd48f514722a207c46536a0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73662
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to file thermal_table_0310, adjust the STT settings.
BRANCH=none
BUG=b:257149501
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.
Change-Id: If4500c85dcea051aca15602f1fb4b5ec80b73e67
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
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Change stop_delay_ms time(T3) from 180 to 150 to meet specification.
T3 min-value of HID-I2C should be 150ms.
BUG=b:267280863
TEST=emerge-skyrim coreboot chromeos-bootimage.
Change-Id: I7ef7db4edaecece1fa5ab07e30a80e556ed35f8b
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add new ram_id:0011 for Micron MT62F1G32D2DS-023 WT:B.
Add new ram_id:0100 for Micron MT62F2G32D4DS-023 WT:B.
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
H58G56BK7BX068 0 (0000)
MT62F1G32D2DS-026 WT:B 0 (0000)
K3KL9L90CM-MGCT 1 (0001)
H58G66BK7BX067 1 (0001)
MT62F2G32D4DS-026 WT:B 1 (0001)
MT62F512M32D2DR-031 WT:B 2 (0010)
H58G56BK8BX068 3 (0011)
MT62F1G32D2DS-023 WT:B 3 (0011)
H58G66BK8BX067 4 (0100)
MT62F2G32D4DS-023 WT:B 4 (0100)
BUG=b:271188237
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot
Change-Id: I59a6a6dff249cd4fe982a4de824848f1bac0ecba
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73510
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0
Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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For simplicity, OEM devices are given a single codename per build variant. Winterhold was intended to be the lead device and was chosen as the code name for this OEM. Unfortunately, Winterhold was cancelled. We attempted to rename Winterhold to Whiterun to avoid future confusion. Again, unfortunately, since some devices were already built, changing the name requires a manual change to force the firmware to be taken by the DUT. This was not a reasonable path forward, so we're abandoning the naming to Whiterun.
This reverts commit af69de494e2c32140ce5e00a1562c2845345b1bf.
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Idef95f0f4f369b235937e1806ce57c427e441f21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73583
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Implement `smm_mainboard_pci_resource_store_init` to store the
resources for XHCI devices. These stored resources are later used by
the elog code to log XHCI wake events.
Example elog contents:
```
244 | 2022-10-11 15:49:24 | S0ix Enter
245 | 2022-10-11 15:49:29 | S0ix Exit
246 | 2022-10-11 15:49:29 | Wake Source | GPE # | 31
247 | 2022-10-11 15:49:29 | Wake Source | PME - XHCI (USB 2.0 port) | 256
248 | 2022-10-11 15:50:08 | S0ix Enter
249 | 2022-10-11 15:50:16 | S0ix Exit
250 | 2022-10-11 15:50:16 | Wake Source | GPE # | 31
251 | 2022-10-11 15:50:16 | Wake Source | PME - XHCI (USB 2.0 port) | 257
```
BUG=b:186792595
TEST=Ran on skyrim proto, verified that wake events show in elog
Change-Id: I529f541a8932267a8825773ddc582beafb27da63
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68325
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Winterhold boards populate either NVMe or eMMC, but not both.
This means that there is always one link that is unpopulated. The PCIe
configuration code takes longer to verify that a link is unpopulated
than to just train the link, so this slows down the boot by roughly
80ms vs the case when the device is present. Not training the device
at all lowers boot time by another 20ms, for a total of 100ms saved.
Looking at the NVMe CLKREQ signal before initializing the ports allows
us to identify which device is populated and only initialize that
device.
BUG=b:271569628
TEST=Boot Whiterun and eMMC or NVMe correctly work, boot time is lower.
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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These ports are not hot pluggable, so drop the parameter, which
will result it in being set to zero / not enabled.
BUG=none
TEST=build boot skyrim, verify all PCIe devices functional.
BRANCH=skyrim
Change-Id: Iaa55cc765e8f073b31f25771633789ac13e2fffa
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Enable both L1.1 and L1.2 substates for the WiFi, SD card reader,
and SSD (both NVMe and eMMC). If a given device does not support
a particular substate, then it will not be enabled during PCIe
enumeration by coreboot.
BUG=b:270690572
TEST=build/boot multiple skyrim/whiterun/frostflow SKUs with different
storage configs, verify WiFi/SD card/SSD all functional and have L1
substates enabled insofar as they are supported by the device.
BRANCH=skyrim
Change-Id: Ib84df8b9d97282ae696414e52c4a65cfb0a81194
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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This allows variants to override the skyrim port descriptors.
BUG=None
TEST=Tested with following patches
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8cff44f5b39d130a7191a69970cae8a88bb5d475
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Enable whiterun/winterhold platforms to send the fuse SPL (security
patch level) command to the PSP.
BUG=b:254568112
TEST=On a platform that supports SPL fusing, a message indicating
that fusing was requested will appear in the coreboot console log,
followed by a puff of smoke when the fuse is set and the message
"OK" again on the debug console. (Kidding about the smoke.)
BRANCH=skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I45578597234ba672c89ac421b4626088faca27d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72914
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Move the sustained_power_limit_mW setting from the baseboard
to variants. This setting will be needed before STT is enabled,
but once STT is enabled, this setting should be removed.
BUG=b:265267957
BRANCH=none
TEST=Build/Boot to ChromeOS
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I7b9779600cfa8c7581732e936a714728fd618d20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Skyrim does not have a cardbus socket, so disable it.
Maybe cardbus support shouldn't be enabled by default?
BUG=None
TEST="PC Card (PCMCIA) is supported" no longer shows up
in dmidecode output.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic941b075e8b5082b5e61e728a77fd79c0ebba35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Only Frostflow supports the stylus, so remove the gpio-keys ACPI node
from Skyrim.
The Kconfig value DRIVERS_GENERIC_GPIO_KEYS is still enabled for all
Skyrim variants, since coreboot will drop the driver from the BIOS image
if there are no references to it (in the devicetree). If some other
design ends up using the stylus in the future we won't have to bring it
back.
BUG: none
TEST: build_packages --board=skyrim chromeos-bootimage --autosetgov
Change-Id: I9ffe215741b72b678d74405769f35167d8ded4b5
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Add new ram_id:0011 for Hynix H58G56BK8BX068.
Add new ram_id:0100 for Hynix H58G66BK8BX067.
The RAM ID table has been assigned as:
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
H58G56BK7BX068 0 (0000)
MT62F1G32D2DS-026 WT:B 0 (0000)
K3KL9L90CM-MGCT 1 (0001)
H58G66BK7BX067 1 (0001)
MT62F2G32D4DS-026 WT:B 1 (0001)
MT62F512M32D2DR-031 WT:B 2 (0010)
H58G56BK8BX068 3 (0011)
H58G66BK8BX067 4 (0100)
BUG=b:270629852
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot
Change-Id: Ida5c8354af71cd92c056a33e38d1fadfc5704977
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73252
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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According to thermal_table_0215, adjust DPTC and STT settings.
BRANCH=none
BUG=b:257149501
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id7df3f9bfa3f0e1337c502bc7db9e09e12cd956a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73081
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SPL parameter for DPTC settings is not available for STT-enabled
platforms. It needs to be removed to avoid confusing STT calculations.
BUG=b:265267957
BRANCH=none
TEST=Run the WebGL aquarium with 5000 fish and verify that
there are no power drop peaks.
Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
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This is causing some issues, so disable it until those issues can be
resolved.
BUG=b:271437658, b:271199389, b:270077971
TEST=Screen always lights up on boot & after S0i3
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id4aa441e4b4f76168f8243b6abafa1cf1ea08dbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Handle the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE.
Previously, the EC sent the host event EC_HOST_EVENT_MODE_CHANGE when
body detection changed between lap/desk mode. However, that event is a
wake event, which resulted in spurious AP wake events being triggered
when the EC detected lap/desk mode changes while the AP was suspended.
To resolve this, the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE was
added, which will not be a wake event. This CL adds handling for the new
event to acpi/ec.asl to switch DPTC tables when a change is detected.
BRANCH=none
BUG=b:261141172
TEST=bodydetectmode on|off, verify host event is received
Change-Id: Iabeb7891489a209f45504804355f1fa817082976
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73298
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable HAS_RECOVERY_MRC_CACHE config and add RECOVERY_MRC_CACHE FMAP
section to cache the MRC training data in recovery mode.
BUG=b:270569389
TEST=Build and boot to OS in Skyrim. Ensure that the Type 0x63 BIOS
directory entry is populated with the appropriate MRC_CACHE FMAP
section.
Change-Id: I3f0f41c20b61c96473e887521f84f3ad240adc2b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
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Use fw_config to probe fingerprint.
BUG=b:269986245
TEST=emerge-skyrim coreboot chromeos-bootimage. Test result is pass
with 1000 reboot cycles.
Change-Id: I4b4bca42dd78dfd5b8636ff3cb05406d2d0c94f7
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
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Remove ACPI node for pen eject event to meet project design.
BUG=b:265106657
TEST=emerge-skyrim coreboot chromeos-bootimage
Change-Id: I732de49c6319397d93671c48a6518c7c7e955fdc
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73154
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
MT62F1G32D2DS-026 WT:B 2 (0010)
H9JCNNNBK3MLYR-N6E 0 (0000)
K3LKBKB0BM-MGCP 3 (0011)
BUG=b:265190498
BRANCH=None
TEST=emerge-skyrim coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I860f10552e4e4180e09ab805ca82b108fdc8f21a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73049
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Setup FW_Config for our project.
Configure USBHub\PIXA Touchpad\Audio(rt5682s & alc1019).
BRANCH=None
BUG=b:262798445, b:268621319
TEST=emerge-skyrim coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I2c590ae36d4d089f70e1799189cd414f825e5b8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch makes EC wake up AP from s3/s0ix for OS shutdown/hibernate
when the state of charge drops to low_battery_shutdown_percent.
BUG=b:255465618
TEST=emerge-nissa chromeos-bootimage (EC: https://crrev.com/c/4243898)
Verify system resumes from s0ix and then enter S5 on nivviks with steps:
1. disconnect AC
2. powerd_dbus_suspend --disable_dark_resume=false
3. fakebatt 5
4. fakebatt 4
Change-Id: I63b5246432687e38ddfc5733ac3a115c3456d7e9
Signed-off-by: Ivan Chen <yulunchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73082
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Based on product spec v1.4, update T3 timing from 180 ms to 150 ms.
BRANCH=none
BUG=b:262734395
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the Elan touchscreen works fine.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I0d8f1e008276fccdfbb8c76cfebaccbe71160b64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73130
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Based on product spec v1.4, update T3 timing to 150 ms from 300 ms
BRANCH=none
BUG=b:269041202
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the Elan touchscreen works fine.
Change-Id: Ie5bd4bc2c8be2e43470edd374af0623162067497
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
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Create the whiterun variant of the skyrim reference board by
copying the winterhold files to a new directory named for the variant.
BUG=b:265955979
BRANCH=None
TEST=emerge-skyrim coreboot and boot up on Whiterun
Change-Id: I3539f84e79c05936fe006bfe9d08743d6a9a6ba7
Signed-off-by: Isaac Lee <isaaclee@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72483
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a FMAP region to support caching GOP-driver-modified VBIOS tables.
Select SOC_AMD_GFX_CACHE_VBIOS_IN_FMAP if CHROMEOS && RUN_FSP_GOP.
Default USE_SELECTIVE_GOP_INIT to y if CHROMEOS && RUN_FSP_GOP.
BUG=b:255812886
TEST=build/boot skyrim, verify cached VBIOS data differs from VBIOS
in CBFS, cached VBIOS data is used when not booting in recovery
or developer modes.
Change-Id: I5857fa4a15250bf6478bffa96b16200e318492b1
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Follow thermal table to modify setting.
"stapm_time_constant_s" = "200" to "275"
BRANCH=none
BUG=b:257149501
TEST=emerge-skyrim coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I7fe05fe1c17258a3323b8d04302212e76a388797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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2/5
of split changes of https://review.coreboot.org/c/coreboot/+/58552/28
Change-Id: I18f73462a3995038fe93750320dfc053fec969ba
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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The keyboard reset is not being used on this board, so disable the
functionality.
BUG=None
TEST=Check register values
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4a9f8f254dfefcb32a77f558f984bcdd6004d34b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72913
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This reverts commit 8e1bb93fb88bc9cc20aab33a1fe09fb4c0c652a0.
Reason: Enabling L.2 breaks some devices on this bridge. Reverting
until a workaround is found and additional testing is done.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9f721178244e7764e9b08e419db8a8c05ecc29a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72916
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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GPIO 67 is not currently used on skyrim, so set it as no-connect.
Since it's now free for other purposes, make sure that the
SPI-ROM-SHARING functionality is disabled.
BUG=b:268330591
TEST=Examine registers after change
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id083baf41d25920eca09795453a01aac1d00d0f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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BUG=None
TEST=Verify that DMI type 3 - Chassis Information Type field has changed
from Desktop to Laptop
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I76c8970fe3fdc2ea322a07f114ad03a0373e152c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72907
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add configuration to bump up the SPI flash bus speed from 66 MHz to 100
MHz for starting next phase.
BUG=b:267539952
TEST=None
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Id46201351780bb5bc05422ff36dad6972285690e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Mendocino SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add configuration to bump up the SPI flash bus speed from 66 MHz to 100
MHz starting the board version of the current phase.
BUG=b:260127676
TEST=Build and boot to OS in Frostflow with 100 MHz SPI bus speed.
Observe that the boot time improved by 100 ms compared to 66 MHz SPI
flash bus speed.
firmware log:
SPI fast read speed: 100 MHz
At 66 MHz:
Total Time: 1,563,384
At 100 MHz:
Total Time: 1,462,570
Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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This enables L1.2 for the SSD port.
link_hotplug is unused on Mendocino, so remove it while I'm here, just
as code cleanup. This has no functional difference.
Enabling L1.2 on other devices currently causes problems. Debug is
ongoing.
BUG=b:265890321
TEST=Build & boot, look at states enabled in lspci. Test device
functionality.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8940856a127c8a4ba45148cbbf07a08b621beb4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:266696987
BRANCH=None
TEST=Observe kernel ec panic handler run when ec panics
Change-Id: I9b50ab3c0bcef192ef89f173852cda222f1533c7
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
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Follow thermal team's request on b/248086651 comment#27. Update the
thermal table setting for each mode and the conditions of temperature
switching.
BUG=b:248086651
TEST=emerge-skyrim coreboot
Change-Id: Ida10d9b10c33dea11440879afda07c04c1eccb9f
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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The mp2 PCI device is still present when no mp2 firmware is loaded. When
this device isn't explicitly enabled in the mainboard's devicetree, the
chipset devicetree default of the device being disabled is used. This
results in coreboot's resource allocator not allocating resources to the
device and since the bridge doesn't have enough MMIO space reserved, the
Linux kernel can't assign resources to it. To fix this problem, enable
the mp2 device in the mainboard's devicetree so that it gets its
resources assigned by coreboot. An equivalent change was verified on
Chausie.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1076ccacc6f51bf195b8280a6df5ad1849771519
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72196
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update setting for touchpad I2C frequency and hold time to meet touchpad
i2c SPEC.
- Frequency: 380 ~ 400 kHz
- hold time : 0.3 ~ 0.9 us
BUG=b:261159229
TEST=On frostflow, touchpad i2c spec from EE measure
Frequencies: I2C0 (Touchpad): 393.7 kHz
Hold time = 0.604 us
Change-Id: Iecf4960a12aa56ac307fb9022e47c4e94a2551c1
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72114
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn on the dxio_tx_vboost_enable for frostflow in coreboot.
It needs to confirm the PCIe Signal Integrity after enabled.
BUG=b:259007881, b:248221908
BRANCH=none
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Iaac331737c83ac7a4a1261c32151359e126a009e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Turn on the dxio_tx_vboost_enable for markarth in coreboot.
It needs to confirm the PCIe Signal Integrity after enabled.
BUG=b:263534907, b:263216451
BRANCH=none
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I0798c1d9788e1911c2643bf387722b072aa79045
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
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Skyrim doesn't use the firmware TPM, so remove the binary from the
image.
Note that because this was not used, removing it doesn't change the boot
time.
BUG=None
TEST=Boot
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia627b128c3346a2556c5306de7506519d1f2d70c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Winterhold runs with the SPI fast read speed set to 100MHz. This
decreases boot time by roughly 100ms.
BUG=None
TEST=Examine boot times.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I879e17fb0212910c7f90ba0e78ee16bea8b7cffa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Update USB port Type-A Port A0 setting.
BUG=b:261650602
TEST=emerge-skyrim coreboot. Ensure that USB-A port is enumerated correctly in the output of lusub command.
Change-Id: I9563f7b141c34b613cf896f1ce92178617a62c93
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71854
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
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Update settings for touchpad I2C frequency and data hold time.
I2C frequency and data hold time need to meet touchpad spec.
- I2C frequency: 380kHz - 400kHz
- Data hold time: 0.3us - 0.9us
BUG=b:262320419
TEST=On winterhold, touchpad i2c measurement from vendor,
Frequencies: 395 kHz, Data hold time: 0.66 us
Change-Id: I40fa6f9e88656d4ec02a4120f75a2a9413b5abaa
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO.
Previously, we flagged as an error any device which set the
'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.'
There's no reason to require explicit disablement however, so drop the
superfluous 'disable' flag, and change the _CRS generation to check if
the GPIOs will be exported via the 'has_power_resource' flag instead.
BUG=b:265055477
TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only
listed under PRx, not under _CRS.
Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Morthal has been overcome by events.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ice46f4c7400772dbf51eb9d20b61af277daa8513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Update devicetree based on the schematic_20230105.
BUG=b:263534907, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot
Change-Id: I437425ac4a7cdb883dc213f5f6bb5f8a33a5577b
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71714
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
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Update setting for touchpad I2C frequency.
And meet touchpad i2c SPEC (380 ~ 400 kHz).
BUG=b:261159229
TEST=On frostflow, touchpad i2c spec from EE measure
Frequencies: I2C0 (Touchpad): 389 kHz
Change-Id: Ie9efd4e597e2701c98064185e5b39a6e256a5f1c
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71772
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
|
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Enable DPTC support for markarth.
BUG=b:263216451
TEST=emerge-skyrim coreboot
Change-Id: I18c2c840037f65f4f2ca92054247cece28843e45
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71720
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Because skyrim is loading ramstage from SPI with the DMA engine, the
size of the compressed image is less important to load speed than
decompression time.
Because the LZ4 decompression is so much faster than LZMA, compressing
with LZ4 saves us roughly 30ms in boot time.
For size, we're spending roughly 57KiB:
fallback/ramstage 0x9b00 stage 130864 LZMA (305316 decompressed)
fallback/ramstage 0x9b00 stage 189126 LZ4 (305316 decompressed)
Right now we have 2MiB empty space in Skyrim's RO before this change,
and roughly 550KiB empty space in RW, so there aren't currently any
size worries.
Just for fun, I also tested uncompressed ramstage, and it was still
18ms faster than LZMA, but that makes it roughly 12ms slower than LZ4.
BUG=b:264409477
TEST=Boot skyrim, look at boot speed.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Iedde6fc2db9d702c0ff2b0081e7baa254ac6699f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
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Add new ram_id:0000 for Micron MT62F1G32D2DS-026 WT:B.
Add new ram_id:0010 for Micron MT62F512M32D2DR-031 WT:B
The RAM ID table has been assigned as:
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
H58G56BK7BX068 0 (0000)
MT62F1G32D2DS-026 WT:B 0 (0000)
K3KL9L90CM-MGCT 1 (0001)
H58G66BK7BX067 1 (0001)
MT62F2G32D4DS-026 WT:B 1 (0001)
MT62F512M32D2DR-031 WT:B 2 (0010)
BUG=b:263296326, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot
Change-Id: I3a0d3edb813ef91bfdc68f7400be64fb679dfc04
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
|
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Configure GPIOs based on b/263534907#comment4 from EE.
BUG=b:263534907, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I5346a4322a6538d69d3482948166cfb5bd182021
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71635
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot.
It needs to confirm the PCIe Signal Integrity after enabled.
BUG=b:259622787
BRANCH=none
TEST=confirm the setting has been set correspondingly with checking
the FSP log.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71647
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
H58G56BK7BX068 0 (0000)
K3KL9L90CM-MGCT 1 (0001)
H58G66BK7BX067 1 (0001)
MT62F2G32D4DS-026 WT:B 1 (0001)
BUG=b:263296326, b:263216451
BRANCH=None
TEST=FW_NAME=markarth emerge-skyrim coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I4f00d444bd59443ecba29c6c155d676bab7a3d82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Create the markarth variant of the skyrim reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:262092858
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_MARKARTH
Change-Id: Ifbace841ca56d8659aaffdc31fb2bc4367d96f82
Signed-off-by: Chao Gui <chaogui@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
|
winterhold/whiterun has different H/W topology to skyrim that the eMMC device
is on a different GPP:
skyrim: GPP1 -> SD
winterhold : GPP1 -> eMMC
BUG=b:263763288
BRANCH=none
TEST=s0i3 stress over 2500 cycles.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ie6af4287057c6befa0b787ac28d7898166401b29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
|
|
Update setting for touchpad I2C frequency.
And meet touchpad i2c SPEC (380 ~ 400 kHz).
BUG=b:261159229
TEST=On frostflow, touchpad i2c spec from EE measure
Frequencies: I2C0 (Touchpad): 390.1 kHz
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ied00e43e87404489af2b570206a70b685e554b78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71564
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I4f2f02623b060ef0ebefc5aceb713c77a8b1e9a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71523
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
add dptc power parameter for tablet mode
sustained_power_limit_mW_tablet : 12w
BUG=b:257187831
BRANCH=none
TEST= validate the parameter changes for each mode by AGT
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I22d3f9c79a1eaaccfbef3766019516edb3523964
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70674
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
|
|
Power resource for Bluetooth device is not configured correctly in the
device tree. Fix Bluetooth devicetree configuration.
BUG=b:262785310
TEST=Build Skyrim BIOS image and boot to OS. Ensure that the DUT is able
to connect to a Bluetooth headset.
Change-Id: Id980424349537be35860dec04cc823d419cefe2f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71068
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
add dptc support for different power parameter on tablet/clamshell
mode.
BUG=b:257187831
BRANCH=none
TEST=validate the parameter change for each mode by AGT.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I96e04d113d18b42f3457056a5e4fa311ceccffb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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1.Config setting for touchpad I2C
BUG=b:261159229
TEST=On frostflow, touchpad i2c spec from EE measure
Frequencies:
1.I2C0 (Touchpad): 385.7kHz
Change-Id: I4ca72ee7fabd4b641eb17451ed8d942c5df52dde
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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This will help to integrate RO SPL table in RO partitions such that it
is used before PSP verstage is loaded. After PSP verstage, SPL table in
RW partition gets used.
BUG=b:243470283
TEST=Build Skyrim BIOS image and boot to OS.
Change-Id: Ic2061f66381d7e9a8018e6f28aa0bc2ca6010f6f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70777
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Update RAM ID table because H9JCNNNFA5MLYR-N6E is using spd-4.hex
instead of spd-9.hex.
Reserve RAM ID 3 for it, so the RAM ID table remains the same.
BUG=b:261530632
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot chromeos-bootimage
Then boot devices successfully
Change-Id: I1b683168310f74a07d246af8618b977cce32287a
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Add PCIe RTD3 support for Skyrim
BUG=b:245550573
TEST=Boot/Reboot cycles and Suspend_stress_test 10 times
Signed-off-by: JasonNien <finaljason@gmail.com>
Change-Id: I7f01827613eea2f254bc42c7f5aebeeb969b163a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70740
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Replace `Store (a, b)` with `b = a`.
Change-Id: Ib75ccc10c8086086f5db4ced1163b74c9835364b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Now that gpio.h will only include the defines in the IASL case, gpio.h
can be included instead of soc/gpio.h in the files that will be directly
or indirectly included in the DSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifc8d8fe4e4148e5b5628f32778368d1fc7f44e5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70510
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Based on the SKU plan, add FW_CONFIG definition.
BUG=b:260473966
BRANCH=None
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I727f69e8fe340cfe624adb5a49bd080ba9544786
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70418
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Replace the amdblocks/gpio.h and soc/gpio.h includes with the common
gpio.h which will include soc/gpio.h which will include amdblocks/gpio.h
in the AMD SoC case.
Since baseboard/ec.h and indirectly baseboard/gpio.h files will get
included in the DSDT, the soc/gpio.h includes in those aren't replaced
with a gpio.h include for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib982e338b5c6bc145ec1a8f6dd75175a42dfb426
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70436
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Enable Dynamic DPTC support.
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I957511c44278a7cffb7cb5d7e099eb13232b6a1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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DTTS indicated Dynamic Thermal Table Switching.The proposal would like
to develop the schematic for switching 6 thermal table by lid status,
machine body mode and temperature. After entering the OS, the thermal
table would be table A. If the “Motion” or “Lid status change” is
detected. The thermal table would switch to laptop mode or lid close
mode.
Once the higher environment temperatures are detected,the thermal
table would switch to the corresponding power throttle table (B, D or
F). Based on these table switching mechanisms, no matter how the
end-user uses Chromebook,they could enjoy more humanized thermal
designs.
Release Over Over Release .
Temp. Temp. Temp. Temp. .
-------------------------------------------------------- .
Desktop mode Table A Table B 50C 45C .
Lid open (Default) .
-------------------------------------------------------- .
Desktop mode Table C Table D 55C 50C .
Lid close .
-------------------------------------------------------- .
Laptop mode Table E Table F 45C 40C .
-------------------------------------------------------- .
On the proposal, the transmission rules are list below:
1. Table A is the default table after booting.
2. A, C, E (Release Temp) can switch to each other.
3. B, D, F (Over Temp) can switch to each other.
4. A and B, C and D, E and F can switch to each other.
5. If Lid open/close or mode switch event trigger, temperature release
tables will translation to each other, temperature over tables will
translation to each other.After that event trigger, EC will check the
new temperature condition and decide if the temperature need to be
trigger.For example, if table A will switch to table D, table A will
switch to C with Lid close event, if temperature is over 55C, EC will
trigger temperature to switch form table C to D.
6. EC will trigger 3 times body-detection events during power on boot
without any body-mode and lid status change. For this case if the
previous table label is on same group, we will based on the temperature
to decide the table.
For example, assume table A is current table. When the temperature
reaches 50C, than the table is switched from A to B. The current table
is B. When the temperature is downgrade below 45C, the table is
switched form B to A. The same rule is for C and D, E and F.
BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
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Enable STT and set 6 thermal table profiles for Dynamic Thermal Table
Switching Proposal support.
BUG=b:232946420
BRANCH=none
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Ie0740cb5bb16cd53c2ee6937e32a974346012823
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
|
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Enable SOC_AMD_COMMON_BLOCK_ACPI_DPTC for Morthal boards, to enable
support for the low/no battery boot feature.
BUG=b:217911928
TEST=build_packages --board=skyrim chromeos-bootimage --autosetgov
Change-Id: I3eb6bee6601e34420a90f33f8f2c45cf3fe37f9b
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70216
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable DPTC support for frostflow.
BUG=b:257187831
TEST=emerge-skyrim coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Iac7b8789a5189827fe98cb06328d666300841a5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69931
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Expand DPTC_INPUT macro to supoort 13 DPTC thermal table parameters for
dynamic table switching support.
BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Add new ram_id:0100 for memory Samsung K3LKBKB0BM-MGCP.
Add new ram_id:0101 for memory Samsung K3LKCKC0BM-MGCP.
The RAM ID table has been assigned as:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNCP3MLYR-N6E 1 (0001)
MT62F2G32D8DR-031 WT:B 2 (0010)
H9JCNNNFA5MLYR-N6E 3 (0011)
K3LKBKB0BM-MGCP 4 (0100)
K3LKCKC0BM-MGCP 5 (0101)
BUG=b:254758998
BRANCH=None
TEST=FW_NAME=frostflow emerge-skyrim coreboot
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I8ff879ff7185f5a0ca1b9632820aba3b0f5d02c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
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Set Package Power Parameters from AMD DevHub document #57316.
"stapm_time_constant_s" = "200"
BRANCH=none
BUG=b:257187831
TEST=emerge-skyrim coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I15a69df1436aba05bc19eaffd79394e5ca9bdb3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69565
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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The Skyrim devices share a common set of DPTC values to enable booting
with low/no battery. Rather than duplicating them in each variant's
overridetree.cb, move them into the baseboard/devicetree.cb.
BUG=b:217911928
TEST=tast run <IP> power.ShutdownWithCommandBatteryCutoff
Change-Id: I20f0a8259c2fc986da23026da88feadd69942046
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69904
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All parameters of DPTC_INPUT() need to be configured on devicetree
when SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enabled. The parameters without
configurations on devicetree would be 0 when
SOC_AMD_COMMON_BLOCK_ACPI_DPTC is enable. Follow AMD DevHub document
#57316. Configure vrm_current_limit_mA, vrm_maximum_current_limit_mA
and vrm_soc_current_limit_mA on devicetree with thermal table config E
as default table for SMT. Since the dynamic thermal table switching
mechanism is still under cooking, after discussing with thermal team,
suggest adopting config E(limit Soc not reach to max power) as default
thermal config to avoidany thermal-related issue during phase build.
Once the dynamic thermal table switching mechanism is finished, will
change the default value to config A.
BUG=b:258572474, b:248976976, b:259167917, b:257394883
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: Ic1e7a46cac4119c7237d96a7bd0d23c8db028680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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It shouldn't be assumed that all variants of skyrim will use the same
gpio for TPM interrupts.
Use the PSP's new mailbox command to tell it what gpio the tpm interrupt
comes in on.
BUG=b:248193764
TEST=tast run <ip> hwsec.TPMContest
Verify log entry:[DEBUG] PSP: Setting TPM GPIO to 18...OK
Use incorrect GPIO in mailbox cmd and verify TPMContest test
failed.
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Change-Id: I9f4005e10987caf9f32e5ac99ff5f2b9467e586c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69874
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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