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path: root/src/mainboard/google/reef/variants
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2016-09-28google/reef: Mark touchpad and touchscreen as probed devicesDuncan Laurie
Add the 'probed' flag to the touchpad and touchscreen devices so they are probed by the kernel before being loaded, in case they do not exist or are replaced with another vendor. BUG=chrome-os-partner:57686 Change-Id: I0a61964e6874cd99fab0c21fa404a43548fc8ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16743 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-26mainboards/google/reef: use chromeec's ASL lid switch implementationAaron Durbin
Defer to the lid switch implementation provided by the chromeec. BUG=chrome-os-partner:56677 Change-Id: Ida451dc29c8cf55fb88015e48a9e0bca3740f645 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16733 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-09-21mainboard/google/reef: Enable cr50 TPM interruptDuncan Laurie
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low. BUG=chrome-os-partner:53336 Change-Id: Ib0247653bdcbaccb645cd16b81d7ec3c38f669af Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16673 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19Revert "mainboard/google/reef: Enable cr50 TPM interrupt"Duncan Laurie
This reverts commit 24de342438208d9b843e87627f15b9a272285b0f.
2016-09-19mainboard/google/reef: Enable cr50 TPM interruptDuncan Laurie
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low. BUG=chrome-os-partner:53336 Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19mainboard/google/reef: Configure WLAN as wake sourceVaibhav Shankar
This implements PRW method for WLAN and configures PCIe wake pin to generate SCI. BUG=chrome-os-partner:56483 TEST=Suspend the system into S3 or S0ix. System should resume through wake event from wifi. Change-Id: I9bd078c2de19ebcc652b5d981997d2a5b5f0b1b7 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16611 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-15mainboard/reef: add variant support to ASL codeAaron Durbin
There are certain board-specific options for reef variants. The big one is the DPTF settings. Rearrange the ASL files such that dsdt.asl is the main landing area. The ACPI options for Chrome EC are contained in the variant/ec.h header so the actual code #includes can just reside in dstd.asl. Since most of the mainboard specific peripherals are auto generated by the acpigen from devicetree there's no real separate need for mainboard.asl. The one thing not addressed in this CL is the notion of a variant having the Chrome EC or not (along with lid, etc). Future indirection can be provided when needed to address that requirement. BUG=chrome-os-partner:56677 Change-Id: I5c888f5fc64913dcff010c28f87e69ac5449e6b6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16604 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-14mainboard/google/reef: Configure PERST_0 pinVaibhav Shankar
This configures PERST_0 in devicetree. For boards without PERST_0, the pin should be disabled. For boards with PERST_0 the correct GPIO needs to be assigned. BUG=chrome-os-partner:55877 Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16603 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-13mainboard/google/reef: add MKBP EC event as SCI event.Gwendal Grignou
Add MKBP as a SCI event: the EC is then able to send events coming from the sensors. BUG=b:27849483 TEST=With EC configure to send MKBP events, check sensor information are retrieved by the kernel. Change-Id: Ib06241bfcdc8567769baff4f3371cc0c6eab3944 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/16594 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12mainboard/google/reef: Enable lpss s0ixVenkateswarlu Vinjamuri
This setting enables lpss to power gate in S0ix. BUG=chrome-os-partner:53876 Change-Id: I0a0fecb0e2b6e5e2f89ac505dd603f4be1bc161e Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16558 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12mainboard/google/reef: Disable CLKREQ of unused PCIe root portsVenkateswarlu Vinjamuri
1. Removes PCIe blocker for S0ix. 2. Set the correct PCIe root port for wifi/bt on EVT. 3. Turn off CLKREQs of unused PCIe root ports to power gate the IP. Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-08mainboard/google/reef: move devicetree to baseboardAaron Durbin
Move the current devicetree.cb to be under variants/baseboard. New variants can provide their own devicetree as needed. BUG=chrome-os-partner:56677 Change-Id: Ib109ca4be883884b318264500d14aa8d40e3072a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16510 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-06google/reef: Enable 20K pull ups for LPC CLKRUN and LAD0:3 linesShamile Khan
The pull up for CLKRUN is required to resolve keyboard slowness and malfunctioning observed on some reef systems. The CLKRUN signal was probed and found to be floating when the pull up was not enabled. Also Added pull ups for the LPC Multiplexed command, address and data lines LAD0:3 because the LPC Interface specification requires them. BUG=chrome-os-partner:55586 BRANCH=none TEST=When a key is pressed, the character is immediately visible on the screen. Also the interrupt count for i8042 increments immediately in /proc/interrupts. Change-Id: I16df1a0301a3994c926a609f61291761219f9e01 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/16426 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-06mainboard/google/reef: drop remaining proto board referencesAaron Durbin
The last vestige of the proto boards is the memory sku id gpios. The internal pullups are still required because there's only pulldown stuffing options available on the reef boards. BUG=chrome-os-partner:56791 Change-Id: I04d541a897ec9aacbf2011293d18242fa32896d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16432 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-06mainboard/google/reef: add baseboard nhlt configurationAaron Durbin
Move the current NHLT configuration implementation to the baseboard area such that other variants can leverage it or provide their own configuration. BUG=chrome-os-partner:56677 Change-Id: If0d48cacdc793492e1618d0eda02a149e33f0650 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16431 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: add baseboard memory configurationAaron Durbin
Move the current memory configuration implementation to the baseboard area such that other variants can leverage it. The swizzle config is exported as a global to allow duplicate swizzles to use the same structure while still allowing different memory SKUs. BUG=chrome-os-partner:56677 Change-Id: I57201118053051c01f0e3f164ab4bbaf650b892b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16430 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: provide cros_gpio variant APIAaron Durbin
Add support for Chrome OS gpio ACPI table information by providing weak implementation from the baseboard. BUG=chrome-os-partner:56677 Change-Id: I517764b78f47fb7b3637482ff9efc053cdd1ac69 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16422 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: consolidate gpio related defines to one placeAaron Durbin
Since multiple boards will be living within one directory move all the macros for defining anyting related to GPIOs to the gpio.h header file. That way, when other boards land they can override or use them as is. BUG=chrome-os-partner:56677 Change-Id: I36967e57fc61ef354e0b51d1ff1396ce562fa805 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16421 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: declare mainboard_ec_init() in each C fileAaron Durbin
There's no common EC header file in the code base, and I didn't want to use a header file for single declaration. Therefore, just move the declaration to each file that uses that symbol. BUG=chrome-os-partner:56677 Change-Id: Ibaebb0ea6a07029aec02d5185cf05ffb8593b117 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16420 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: add variant API for board_id and gpioAaron Durbin
Provide APIs for the board_id() and gpio table functionality. Default and weak implementations are provided from the baseboard. BUG=chrome-os-partner:56677 Change-Id: I02d8deb7f60f8c4842916a9d35f51d8af74b1da4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16419 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-04mainboard/google/reef: provide baseboard and variant conceptsAaron Durbin
To further the ability of multiple variant boards to share code provide a place to land the split up changes. This patch provides the tooling using a new Kconfig value, VARIANT_DIR, as well as the Make plumbing. The directory layout with a single variant, reef (which is also the baseboard), looks like this: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/reef - code variants/reef/include/variant - headers New boards would then add themselves under their board name within the 'variants' directory. No split has been done with providing different logic yet. This is purely a organizational change. BUG=chrome-os-partner:56677 Change-Id: Ib73a3c8a3729546257623171ef6d8fa7a9f16514 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16418 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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