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2018-01-12mainboard/google/kahlee: Enable PCIe Lane 2Martin Roth
The Port initializer had been changed from PortDisabled to PortEnabled, but engine inializer hadn't been updated from PcieUnusedEngine to PciePortEngine. Update this so the port works. Also change disabled port to PcieUnusedEngine. BUG=b:71818026 TEST=PCIe device now shows up on D2F4 Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23210 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Chris Ching <chingcodes@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-10mainboard/google/kahlee: Update SPD MakefileMartin Roth
The .spd.hex text is added to the name by the build process. This was causing a failure because we were trying to add the files: 'file.spd.hex.spd.hex' to the build. Remove the additional .spd.hex text. BUG=b:71535311 TEST=Build Change-Id: I11df7a90c979503676a66c6502900a13f1a8e359 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2018-01-05mainboard/google/kahlee: Update Grunt devicetree.Justin TerAvest
Grunt's devicetree dropped some entries when it was split from the kahlee variant. This commit restores: spd_addr_lookup - memory information for AGESA dram_clear_on_reset - keeps DRAM contents on reset uma_mode - needed for vbios uma_size - needed for vbios Change-Id: I1d8cdc97594867f1d706318370055087976a5104 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-21google/kahlee: Select fanless SMU firmwareMarshall Dawson
Don't rely on the cascading default values. Ensure Kahlee uses the fanless versions of the SMU fimware by selecting it. Change-Id: I0761266f2a4026ebc251b64074c10481118734a2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-14mainboard/google/kahlee: Update overcurrent pinsMartin Roth
The overcurrent pins on kahlee weren't mapped correctly, causing the USB-A port to stop working. None of the EHCI only ports are used for external connectors, so all of the overcurrent pins should go to the XHCI connections. This is also true of the Grunt board. On Grunt, this also means that we don't need OC3, as it doesn't map to anything in the XHCI controller, as it's coming from an internal hub. BUG=b:70636233 TEST=Build & boot Kahlee, verify USB-A port is working again. Change-Id: I53336a18a26bd9be27c7265fddbcd780632656bf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2017-12-12google/kahlee/grunt: Add SPD filesMarc Jones
MEM_ID SPD 0000 hynix-H5AN8G6NAFR-UHC 0001 hynix-H5ANAG6NAMR-UHC 0010 micron-MT40A51216JY-083E 0011 micron-MT40A1G16KNR-075E 0100 samsung-K4A8G165WB-BCRC 0101 samsung-K4AAG165WB-MCRC BUG=b:69268926 TEST=build test Change-Id: I1fd6335b3f8842252c42009a0a91a5b6ed3ea238 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-12soc/amd/common: Move Agesa related headersRichard Spiegel
Move AGESA related headers in soc/amd/common to soc/amd/common/block/include/amdblocks. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, headers moved). Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-11soc/amd/common: Move files to common/blockRichard Spiegel
The following files need to be moved: amd_pci_util.c, amd_pci_util.h and spi.c. The remaining files are AGESA related and will be part of a separate issue/commit. BUG=b:62240201 TEST=Build with no error gardenia and kahlee (no code change, just folder reorg). Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-09mainboard/google/kahlee: Update GPIOsMartin Roth
- The touchscreen interrupt was moved from the GPIO 3, as originally suggested to GPIO 11. This changes the gevent from 2 to 18. - Add EMMC reset on GPIO 93. - Add EMMC bridge PCIe reset on GPIO 40. - Set device enables to high. - Remove extra SCI comment from GPIO 130. - Set individual device PCIe reset pins to high. - Enable global PCIe reset on GPIO 26. - Mark LPC_CLK1 as unused. - Update net names based on latest schematics. - Set Direction and level/edge correctly for SCIs/SMIs. - Remove SCI for pen detect. - Add comments. BUG=b:70234300, b:69681660, b:69305596 TEST=build grunt Change-Id: Ib591e4278ed23d0963ecb19ad9c326498b4c7796 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-09mainboard/google/kahlee: Update PCIe port mapMartin Roth
- Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on PCIe port 1, so move the OemCustomize file into the variant directory. - Add comments in baseboard version so it's easier to understand. - Update reset pins, put the definitions in gpio.h BUG=b:70255003 TEST=Build and boot Kahlee. Build Grunt. Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-12-07kahlee/ec.c: Use new wide IO functionRichard Spiegel
In preparation to deleting early_setup,c, change early_ec_init() to use new southbridge.c function sb_set_wideio_range and remove <#ifdef __PRE_RAM__>. BUG=b:64033893 TEST=Build, boot and check serial output, search for "Covered by wideIO xx", which should match earlier message "Range assigned to wide IO xx" generated within modified early_ec_init(). Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06google/kahlee: Set USB OC pinsMarc Jones
Set the USB over current pins for the Grunt baseboard and Kahlee mainboard. Removes the ACPI ASL OC code, which is not used on Stoney Ridge SOC. BUG=b:69229635 TEST=Build and boot Kahlee. Not tested with OC test fixture. Change-Id: I5a9b3409d9c91b89fd02f8eecf9e04c435f14342 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-02mainboard/google/kahlee: Remove usb_oc.asl filesMartin Roth
These files aren't needed for the overcurrent functionality. BUG=b:69305596, b:69229635 TEST=Build Grunt & Kahlee. Overcurrent wasn't yet enabled so no other testing was needed. Change-Id: I8dcd50a249e387ccf1142949b359cee09942460a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-12-02mainboard/google/kahlee: Add Baseboard GPIOsMartin Roth
Add initial baseboard GPIOs based on grunt schematics. BUG=b:69305596 TEST=Build grunt Change-Id: I4efcee7dbf54fb9ea82e5e9394db805bb69203c8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-12-01mainboard/google/kahlee: Update Kconfig string used in makefilesMartin Roth
Update the variable ${CONFIG_VARIANT_DIR} to use parens instead. Either is valid, but since we use parentheses everywhere else, it's better to be consistent. BUG=b:69691210 TEST=Build grunt & kahlee Change-Id: Ieffabaae5516a893f1dc1f7195a17c4cdeae8853 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22656 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-29google/kahlee: Add SPD functionMarc Jones
Add the mainboard_spd_read function in romstage and call the variants function. Grunt is the baseboard and has soldered down memory, so add it for the default weak SPD functions and build the SPDs in cbfs. Kahlee overrides the weak SPD function and falls back to the soc I2C SPD functions. BUG=b:67845441 TEST=Build and boot Kahlee. Change-Id: I789002bfadc1a2b24f9046708986d29c0e2daf33 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-29google/kahlee: Rename board_id to memory_skuMarc Jones
The GPIOs used in board_id are meant to indicate the memory configuration. Rename board_id to memory_skus. Report the board_id received from the EC. BUG=b:69649438 Change-Id: I84bacead3daf829c97f595c4c11a243953243c29 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22561 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-28mainboard/google/kahlee: Update Grunt for 16MB ROM chipMartin Roth
- Update Grunt to 16MB chip in Kconfig. - Move chromeos.fmd into variant directory & update Kconfig with the new location. - Add Grunt specific chromeos.fmd file. BUG=b:69691210 TEST=Build grunt; Build & Boot Kahlee Change-Id: I8d2f5e3255984d0d9a18df560f84f6db03b73a78 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-28mainboard/google/kahlee: Update chromeos.fmdMartin Roth
- Remove SI_ALL section. This is no longer needed as the PSP dirctory is placed into the RO coreboot section. - Add 1MB Legacy section. - Add Memory cache section. These sections are called "MRC", which is an Intel term, but AMD platforms will use the same regions for saving the same sort of data. BUG=b:65497959, b:67035984 TEST=Build & boot kahlee Change-Id: I5e41a0aa6bd4b29b8014c6559126a29cd7ed45d8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-22Create SOC description file soc.aslRichard Spiegel
Request from commit 519680948b (move carrizo_fch.asl code to soc), merge several includes into a single file in soc directory. Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl. Then copy the required section from dsdt.asl into a new soc.asl. Affected boards: amd/gardenia and google/kahlee. BUG=b:69368752 Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22541 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-20amd/stoneyridge: Fix SPD files and functions camel caseMarc Jones
Remove ugly camel case in the soc/amd/common and Stoney Ridge SPD files and functions. Update the related mainboards. Also, remove a unreferenced function prototype, smbus_readSpd(). Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mb/google/kahlee: Move ec.h into variant include directoriesMartin Roth
The mainboard directory is included through the PI makefile - most mainboard directories aren't in the include path at all. Move the ec.h file into the baseboard/variant directory that is already in the include path. BUG=b:69220826 TEST=Build Change-Id: I89d361b700c66ba576de724927574fdab9461fc6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mainboard/google/kahlee: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h I missed this file in the Kahlee cleanup. BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: Id9b303cb3cee8088fb5cca5257566c033d28c692 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mainboard/google/kahlee: Update memory.cMartin Roth
This fixes some issues with the initial implementation that was copied from reef. - The board ID value shouldn't be size_t - it's not a size. - Kahlee doesn't even need the memory.c file - it uses an SoDIMM. BUG=b:68293392 TEST=build stoney platforms, boot kahleebo Change-Id: Ife5660d36912e887edfd0365a9f16c5a172c9c86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22515 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-15variants/kahlee: Add thermal ASLMarc Jones
Connect the EC thermal to Kahlee and Grunt thermal ASL. Intialize GNVS thermal values in the mainboard finalize. BUG=b:67999819 Change-Id: I89159a5fd3c639e511139b8c5948b6a4ee19aaa3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-15google/kahlee: Get power plug notification from the ECMarc Jones
Set the EC SCI reporting mask to include the power plug reporting. BUG=b:65637324 TEST=Check power_supply_info on AC/DC. Change-Id: I58814fc495081ffe8e47162da0fa4fbeba49d67b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to socRichard Spiegel
Code within carrizo_fch should be SOC specific instead of board specific. BUG=b:64034810 Change-Id: I5de2020411794bfcd3730789f62af9c9834a018b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22455 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-14mb/google/kahlee: Remove direct AGESA header includesMartin Roth
All Stoney AGESA headers should be included only through agesawrapper.h BUG=b:66818758 TEST=Build and boot tested Change-Id: I642f5caf8a37ae4042c32fec3a92e0995193cb7a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mb/google/kahlee: Add getter function for GPIO arrayMartin Roth
Instead of getting the address of the GPIO function with an extern, add a getter function and make the GPIO arrays static. TEST=Build Grunt; Build & boot Kahlee BUG=b:69164070 Change-Id: I3defcb66696459b915d7d4f43234d5c08ab7d417 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22435 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mb/google/kahlee: Remove mainboard.hMartin Roth
mainboard.h only had a single function definition. Move it into baseboard/variants.h and get rid of the file. TEST=Build grunt/kahlee BUG=b:69164070 Change-Id: I6b7d50d5c949733d77c42b4daf56ed1f97ed6954 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mainboard/google/kahlee: Add Grunt variant frameworkMartin Roth
Update common files and add files for grunt to the variant directory. BUG=b:68293392 TEST=Build only Change-Id: I7b80e470058872d6613e66e64c8dd1494942e9b9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13mainboard/google/kahlee: Add baseboard frameworkMartin Roth
BUG=b:68293392 TEST=Build only Change-Id: Ie4d039b4da10a992fc9dd2b0221fd4a1644aae6a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10google/kahlee: Use devicetree register values for UMAMarshall Dawson
Set the UMA memory size to 128 MiB. This value was empirically tested by AMD as the lowest value one could use. BUG=b:64927639 TEST=default, and 64, 128, 256, 384MB non-legacy configurations. Change-Id: I2bc808d8b402c3eb16a1a5962f3fa9d6b224cf52 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21335 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10google/kahlee: Add defines in OemCustomize.cMarshall Dawson
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max supported for the device. AGESA's DRAM procedures follow the BKDG and may vary depending on the number of slots on the motherboard. DIMM numbering and ordering is also affected by this value. Replace hardcoded integers with defined values for DIMM slots and number of channels. Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21853 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10google/kahlee: Move DRAM clear override to devicetreeMarshall Dawson
Kahlee needs to keep its DRAM contents after a reset. Move this override out of the OemCustomize.c file to a devicetree register setting. Change-Id: I3196cb8b94bec64e8ce59e4285cf8d97f442bd3d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21858 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-09mainboard/google/kahlee: Move usb_oc.asl into variant/acpiMartin Roth
This compares to the acpi directory in other variants. BUG=b:68293392 TEST=Build and boot kahlee Change-Id: I05d402995b280d6f020bc2575063dbffefa30670 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09mainboard/google/kahlee: Define MEM_CONFIG3 for Kahlee variantMartin Roth
Even though this GPIO isn't used for Kahlee, it needs to be defined so that the weak version of the variant_board_id() function can compile. BUG=b:68293392 TEST=Build and boot kahlee Change-Id: Ia8daf70fbafe02ec37c6b5eb8421cdb11de3be8b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07mainboard/google/kahlee: Add MAINBOARD_FAMILYLann Martin
BUG=b:68865273 Change-Id: Ia2e9b10035e9dd502a563cdf8324ea8ea1922db3 Signed-off-by: Lann Martin <lannm@chromium.org> Reviewed-on: https://review.coreboot.org/22359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-04mainboard/google/kahlee: remove unused FILECODE macroAaron Durbin
From what I can tell FILECODE isn't used at all in this file. Remove it. Change-Id: Ie88140e63a4917f470f42119c1fe4e8c7d2584ca Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-03google/kahlee/acpi: Serialize method _CRSPaul Menzel
ASL+ Optimizing Compiler/Disassembler version 20170831 shows the remark below. ``` dsdt.aml 87: Method (_CRS, 0x0, NotSerialized) Remark 2120 - ^ Control Method should be made Serialized \ (due to creation of named objects within) ``` So, serialize the method. Fixes: commit 4a51ea8470 (google/kahlee: Add ASL for Elan touchpad) Change-Id: I664f493318cbfd80d91565c0d29ec918278c4906 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/21901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-03mainboard/google/kahlee: Prepare for variantsMartin Roth
Move files that are particularly specific to the mainboard into the variant directory. Files that only have small areas of mainboard specific pieces use #if to separate between the boards. Add memory.c to split out the variant board id into a weak function. Add baseboard/gpio.h to satisfy the build - this will be updated in the next commit. BUG=b:68293392 Change-Id: I7c1beb45f571f2547f3b5b0d7ec78923d0cec761 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-28mainboard/google/Kahlee: Combine BiosCallOuts filesMartin Roth
There's no need to have these separated. BUG=b:64932381 Test=Build & Boot Change-Id: I22898d3bf95d5e9a8fc2643bfccae1e2f5b29e44 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22google/kahlee: Add PSP to devicetree.cbMarshall Dawson
Add the missing device and ensure it shows up in the devicetree prior to PCI enumeration. Change-Id: Ia2c4ba1200422b36c533e86065a4fcd10c4b2722 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20kahlee: Set Kahlee GPEsMarc Jones
Add GPE configuration table. Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22). Set the EC and PCIE/WLAN SCI GPIO signals. Set GPE ASL methods for: PCIE/WLAN 8h EHCI 18h XHCI 1fh Note EC GPE3 methods are in the EC ASL. BUG=b:63268311 BRANCH=none TEST=Test lidswitch powers the device on and off at the login screen. Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22096 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20stoneyridge: Fix USB ASLMarc Jones
Stoney Ridge has one EHCI controller and one XHCI controller. Also, update the Kahlee and Gardenia mainboards ASL to match. Change-Id: I5749ca0640796732e74e551147f8c4446317b77e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20Stoney Ridge Platforms: cast AGESA tables to void *Martin Roth
In the original AGESA headers, these tables are not defined as const. Cast them to void * so that they'll work with either version of the headers. BUG=b:64766233 TEST=Build in cros tree and upstream coreboot, with old headers and updated headers. Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22059 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20Stoney Ridge Platforms: Make AGESA callout tables commonMartin Roth
There was no reason to have the AGESA callout tables in each mainboard, so move them to soc/amd/common. Move chip specific functions into the stoneyridge directory: - agesa_fch_initreset - agesa_fch_initenv - agesa_ReadSpd Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which to use. Soldered-down memory still needs to be supported in a future commit, as stoney supports both DDR3 & DDR4. A bug has been filed for support for the upcoming Grunt platform. BUG=b:67209686 TEST=Build and boot on Kahlee Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-16src/mainboard/google/kahlee: Remove legacy tablesRichard Spiegel
Remove IRQ and MP tables. Modern OS use ACPI instead of legacy tables. Use Kconfig for reversable configuration if using old OS. BUG=b:62241143 Change-Id: I5fc833c8af47b5f6fad757e129250e6202810dbb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-16src/mainboard/kahlee: Default AMD FW position to 1MBMartin Roth
For Kahlee, the AMD firmware directory should be in the 1MB location so that it's in the RO cbfs section. BUG=b:65484600 TEST=Build & boot Change-Id: I650d8bc0bfa773f5fb5dc11167fe3db3b9550b68 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22003 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-15google/kahlee: Add SMI sleep handlerMarshall Dawson
Notify the EC the system is going to sleep. Change-Id: I025e268a4f806d827348d91effff43a6a339a148 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-15google/kahlee: Add SMI apmc handlerMarshall Dawson
Forward the apmc call to the chromeec. Change-Id: Id724c1abf15617ad1ba28f2c0247455b014c1867 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-13google/kahlee: Add AGESA_DO_RESET in bootblockMarc Jones
Support the required AGESA_DO_RESET in bootblock. BUG=b:64719937 BRANCH=none TEST=Check AGESA reset request in booblock does a reset in the serial console or ec console. Change-Id: I462a1f81b8d209c15417946a314f2bfb9b226e4d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-11mainboard/google/kahlee: Add EC_IN_RW flagMartin Roth
Depthcharge was complaining that the GPIO for this flag wasn't set. The GPIO also needs to be an input, not an output. BUG=b:67614692 TEST=Depthcharge no longer complains that there is no GPIO set for flag5. The system boots again. Change-Id: Ib854e97b0a3aa42a95ceb8a42a9776f0345ff8b1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-08ec/google/chromeec: Add library function google_chromeec_events_initFurquan Shaikh
mainboard_ec_init implemented by all x86-based mainboards using chromeec performed similar tasks for initializing and recording ec events. Instead of duplicating this code across multiple boards, provide a library function google_chromeec_events_init that can be called by mainboard with appropriate inputs to perform the required actions. This change also adds a new structure google_chromeec_event_info to allow mainboards to provide information required by the library function to handle different event masks. Also, google_chromeec_log_device_events and google_chromeec_log_events no longer need to be exported. Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-02mainboard/amd: Add required callouts to Stoney BiosCallouts.cMartin Roth
Hook the new required AGESA callout functions into the callouts tables. BUG=b:66690176 TEST=Build and boot Kahlee - see the functions get called. Change-Id: Ife9c2b20e59ede404edb1f700238e425fea35914 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27google/kahlee: Fix GPIO ASLMarc Jones
Use a single define and set the CROS GPIO ASL device to match the Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN field in the GPIO ASL. This addresses the TEST indicated below. BUG=b:65597554 BRANCH=none TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030. Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26binaryPI boards: Fix indirect AGESA.h includeKyösti Mälkki
Change-Id: I3f6030879da61168adf42db0a4913d70a737594e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-20google/kahlee: Prevent AGESA memory clearMarc Jones
The Linux Pstore area must not be cleared on a reboot. Set the option to not clear the memory in AGESA. BUG=b:64193190 BRANCH=none TEST=Memory clear isn't called in AGESA. Change-Id: I9b8286ade718fa80bf3badd478ab9a7df643ab98 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21596 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-20google/kahee: Fix number of memory channelsMarc Jones
Kahlee has a single memory channel, not two. This corrects DMI type 17 reporting and the memory clear functions. BUG=b:65403853, b:64193190 BRANCH=none TEST=AGESA DMI reports the correct number of DIMMs. Change-Id: Ic263d2677a480448beaf3850391b1a3d4ed38657 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-19AGESA binaryPI: Clean up amdfamXX.h includeKyösti Mälkki
Change-Id: Iba8b8d33e1f10e28745234988d97d4fafd04c798 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-11kahlee: Add RO_VPD region in FMAPMarc Jones
The RO_VPD region is required for ChromeOS. BUG=b:65408869 TEST=Build and check coreboot.rom with fmap_decode. Change-Id: I9c475acc5e34a3a41f815990fb1f363963c7b9b9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23soc/amd/stoneyridge ACPI: Sync sleepstates.asl definitionsKyösti Mälkki
Sync file with southbridge/amd/common/sleepstates.asl. SSFG was meant to be used as a mask to enable sleepstates _S1 thru _S4. However as a logical instead of bitwise 'and' operation was used, all the states were enabled if only one was marked available. Change-Id: I674953f1a5add74e16ddd84c252e8d21501ffefd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-22google/kahlee: Enable ALS connected to ECAkshu Agrawal
Kahlee has an ambient light sensor connected to the EC. TEST=Can see the device in /sys/bus/iio BUG=b:62030268 Change-Id: Id1138a0fc5270489a734bdf8b1f4ac02d358c0df Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/21146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14stoneyridge: Rename hudson to southbridgeMarc Jones
Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-10google/kahlee: Set eMMC slotMarc Jones
Set AGESA SD/eMMc variable to non-removable eMMc. BUG=b:63891719 BRANCH=none TEST=Boot eMMC on Kahlee. Change-Id: I76ed9cec36a9688ebe75db2077f1ece4ab750c16 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-04google/kahlee: Add ChromeOS SMBIOS Board IDMarc Jones
Kahlee uses 3 GPIO(144, 140, 135) pins to identify the board revision. Change-Id: Ia9693db6d6506af7ff40db0b3ce4cc6c1469f6ef Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04soc/amd/stoneyridge: Use generic gpio libraryMarc Jones
Use the genric GPIO library. Add the required functions. Also, update the Kahlee mainboard dependency to match. Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-03google/kahlee: Add Realtek audio codec ASLIvy Jian
Add the RT5650 codec ASL for proper Linux driver loading. Devices visible to OS: /sys/bus/acpi/devices/AMDI1002:00 /sys/bus/acpi/devices/I2SC1002:00 Change-Id: I60b256f68372c9d17d67c9cb2accaca616a0b9a5 Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Add mainboard GPIOs to ACPIMarc Jones
Add the Google mainboard GPIOs to the ACPI table. Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Fix CTRL+U USB bootMarc Jones
The EC KBC controller was not initialized, so the EC wouldn't put keys in the output buffer. With nothing in the buffer, vboot didn't try to boot the USB stick. Add the driver to setup the KBC called by EC init. BUG=b:62066405 BRANCH=none TEST=Boot Kahlee with USB stick and CTRL+U boots the stick. Change-Id: If9346fda558e802536c7de38da5b21fd25320e40 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20480 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31google/kahlee: Move mainboard_ec_init to chip init phaseMarc Jones
Move mainboard_ec_init out of mainboard enable to the more appropriate mainboard init phase. Change-Id: Ieabcecf70e4de0b42fc639d031755b6d0b66f08a Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31soc/amd/stoneyridge: Move ACPI MADT table to socMarc Jones
Move the mainboard MADT tables to generic soc ACPI code. Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20277 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31google/kahlee: Add EC and GNVS ACPIMarc Jones
Add ACPI support for the Google EC, which requires GNVS support for passing information from the EC to firmware and OS. Change-Id: I0a308bcd608a135cc9633273a05527f020b60743 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/20276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Enable TPMMarc Jones
Set up the TPM decode to SPI prior to verstage. Enable LPC TPM and remove the mock data. Note, Kahlee TPM is on SPI, but decoded by the LPC block. BRANCH=none BUG=b:62103024 TEST=coreboot and Depthcharge reports TPM found. Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Save VBNV data to CMOSMarc Jones
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data to be used in multiple stages and depthcharge. Fixes developer mode USB boot. Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Set DDI port 2 to DPMarshall Dawson
Set DDI port 2 type to Display Port. Change-Id: Idc5e57e01d4f0073ac50533c1b04a95bcae67473 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31google/kahlee: Setup the I2S audio codecMarshall Dawson
Inform AGESA to setup an I2S codec instead of an Azalia codec. This is step one for audio to work. ASL to connect the driver and the hardware is in a follow-on patch. Change-Id: I7ece5d8c317ddc76e0e6b2a005256bc384fe51e2 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/19841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-28google/kahlee: Add ASL for Elan touchpadIvy Jian
Add ASL for the Elan touchpad driver connection in ChromeOS. This is based on the Auron and Rambi ASL. The AMD ACPI code doesn't have the auto table generation the newer Intel Chrome SOC use. Device visible to OS: /sys/bus/acpi/devices/ELAN0000 Change-Id: Id3fc8c8855b0296f43a502e81143498d663468ec Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28google/kahlee: Fix ASL whitespace and formattingMarc Jones
Clean up the ASL whitespace and formatting to match the iasl -d style as other parts of coreboot. Change-Id: I61689cb55dc26cbad160d45aa0a36c00b386fe0c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28google/kahlee: Remove conflicting AAHB IRQ ASLIvy Jian
The AMD internal A-link (AAHB device) doesn't support an IRQ, so remove it. This solves a conflict with the GPIO IRQ required for touchpad operation. Change-Id: Iefaf33cfb2babc29d35b5372fc3a338a72c78a4a Signed-off-by: Ivy Jian <ivy_jian@compal.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Set SERIRQ to continuous modeMarc Jones
The Kahlee Nuvoton EC firmware doesn't support SERIRQ quiet mode, yet. Set continuous mode until the quiet mode feature is available. This allows keyboard and other EC based interrupts through. Change-Id: If77c91fde2bd0f4da85413879fefb753ae6297de Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19840 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Pass GPIO setting in amdinitenvMarshall Dawson
GPIOs for I2C3 were being unset in amdinitmid if the GPIO enable table wasn't passed. It had been initialy set in amdinitreset. Pull the GPIO settings into their own file that can be used in bootblock and later stages. Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Update PCIe link/lane configurationMarshall Dawson
Enable: GPP0 x1 - WLan GPP1 x1 - Card Reader Change-Id: Idbfc2a3260b85949810bdd8dc904e59f8a779e48 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Set FADT legacy and 8042 supportedMarc Jones
The EC is a legacy 8042 device. Don't set LEGACY_FREE and correctly report in the FADT. Change-Id: I041ea4b44372178f3d6073b6ebc8003abc097703 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19836 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Add ChromeOS and ChromeECMarshall Dawson
Add the basics for building as a ChromeOS device. ChromeOS and ChromeEC are dependent on each other, so bring them in together. The EC is a Nuvoton and you can find additional details in the Chromium EC repo. Add the Google HWID "Kahlee TEST 6421". The chromeos.fmd for Kahlee takes advantage of the AGESA located outside cbfs and includes typical RW, VPD, and MRC areas. There are some updates required to depthcharge, vboot, GPIOs, and the ChromeEC before we have a complete-ish system. Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27google/kahlee: Update GPIO tableMarshall Dawson
Update GPIO settings based on the schematic. Change-Id: Ic8a876198a3ba9029d1aabb273418923e40bfcc6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-27google/kahlee: Update for single DIMMMarshall Dawson
Update for a single DIMM with an SPD at address A0. Change-Id: I646f079c99cbaffd7094773243600c3030308325 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19833 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Remove AMD IMCMarshall Dawson
Kahlee does not use the AMD IMC. Remove the files and calls. Change-Id: Ia837551b592b4f473eb38c06c516586fb6c95c88 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19832 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Update KconfigMarc Jones
Update for the Stoney Ridge FT4 package and the on chip UART. Change-Id: I11468834a9ef03da084c156c74d55a19416d98c4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19831 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27google/kahlee: Start Kahlee mainboardMarc Jones
Copied from amd/gardenia. Update the appropriate board name strings. Uses the soc/ structure. Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 09:21:34 +0000