Age | Commit message (Collapse) | Author |
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Program USB Overcurrent pins as per board schematics definition.
BUG=none
BRANCH=none
TEST=Build and boot kunimitsu from USB device.
Change-Id: I6aeb65953c753e09ad639469de7d866a54f42f11
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT.
Platforms that remain to have explicit MMCONF_SUPPORT are
ones that should be converted.
Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17527
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of defining the same functions for reading/clearing boot-mode
switches from EC in every mainboard, add a common infrastructure to
enable common functions for handling boot-mode switches if
GOOGLE_CHROMEEC is being used.
Only boards that were not moved to this new infrastructure are those
that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific
mechanism for reading boot-mode switches.
BUG=None
BRANCH=None
TEST=abuild compiles all boards successfully with and without ChromeOS
option.
Change-Id: I267aadea9e616464563df04b51a668b877f0d578
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17449
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Add the DIMM SPD data for memory types that are not used yet
but are on the matrix and may be used in future builds.
Also fix a typo in the part number string for one type.
BUG=chrome-os-partner:58666
TEST=build and boot on eve p0
Change-Id: I20401d7afb69f1c3ae1a3b0d6e3ec9097f54ef96
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17437
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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In preparation of merging the lpss i2c config structures on
apollolake and skylake move the i2c voltage variable to its
own field. It makes refactoring things easier, and then there's
no reason for a separate SoC specific i2c config structure.
BUG=chrome-os-partner:58889
Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17347
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Add the eve board files using kabylake and FSP 2.0.
BUG=chrome-os-partner:58666
TEST=build and boot on eve board
Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17177
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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