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path: root/src/mainboard/google/dragonegg
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2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-19src: Drop unused 'include <cbfs.h>'Elyes HAOUAS
Change-Id: If5c5ebacd103d7e1f09585cc4c52753b11ce84d0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-05mainboard: Enable PRESERVE flag in all vboot/chromeos FMD filesHung-Te Lin
For Chrome OS (or vboot), The PRESERVE flags should be applied on following sections: RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE, RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768), SI_PDR (chromium:936768) With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in the future. But it's still no harm to use it if there are multiple sections all needing to be preserved. BUG=chromium:936768 TEST=Builds google/eve and google/kukui inside Chrome OS source tree. Also boots successfully on eve and kukui devices. Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-11soc/mainboard: Update mainboard UART KconfigLijian Zhao
After f5ca922 (Untangle CBFS microcode updates) got merged, all mainboard using intel apollolake, cannonlake, coffeelake, glk, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. BUG=N/A TEST=Build and test on Sarien platform, by default we can still get console from cbmem, and enable CONSOLE_SERIAL can get logs from UART port 2. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de Reviewed-on: https://review.coreboot.org/c/30853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-03mb/google/dragonegg: Make WP_RO range align with winbond specificationSubrata Banik
This patch ensures to make memory protected range between 01C00000h - 01FFFFFFh as per winbond spi datasheet https://www.winbond.com/resource-files/w25q256jv%20spi%20revb%2009202016.pdf section 7.1.15 BUG=none BRANCH=none TEST=build and boot dragonegg. Change-Id: Ife451233f60ef680088babbc824bfc5a17078cb9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30551 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-15mb/{intel,google}/{icelake_rvp,dragonegg}: make use of cpu_get_cpuid() ↵Subrata Banik
helper function This patch replaces cpuid(1) references from icelake mainboard with x86 cpu common code library functions cpu_get_cpuid(). - cpu_get_cpuid() -> to get processor id (from cpuid.eax) Change-Id: Ia12d95d911dd6ee60a3a35937264fef668ad9e35 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2018-12-03mb/google/dragonegg: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ief858f6612d1c7b4b0c286cf5938f8c29055f1b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-27mb/google/dragonegg: Enable audioSubrata Banik
BUG=b:116191230 BRANCH=None TEST=1. verified boot beep support at depthcharge. Change-Id: Ia4843185dd79a35476c4f0fc0666ebaf3773db4c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29753 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/dragonegg: Enable trackpadSubrata Banik
BUG=b:112282079 BRANCH=None TEST=1. run evtest and make sure trackpad shows up in list 2. Able to wake system from S3 using trackpad Change-Id: I86d6b7815147d558065611604363bb607119c154 Signed-off-by: Shelley Chen <shchen@google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29752 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/dragonegg: Enable ps2 keyboardShelley Chen
BUG=b:112332115 BRANCH=None TEST=ensure at bootup that /sys/devices/pnp0/00:05 exists and driver link to '../../../bus/pnp/drivers/i8042 kbd' Also, can now see keyboard in evtest. Change-Id: I2a6b382be84bc5201beafe21ff8ddee3738bc5c2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/29750 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-27mb/google/dragonegg: Add initial mainboard code supportAamir Bohra
This patch includes support for both ICL ES0 and ES1 samples. Detailed document is here: Documentation/soc/intel/icelake/iceLake_coreboot_development.md TEST=Able to build and boot dragonegg. Change-Id: I2cc269cb0050bf5b031f48cfe114485c55ab8fa9 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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