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This is missing configuration of Wiloc projects.
Following Wilco projects configuration. CB:32436
The power architecture on this platform is different than most of our
other x86 devices and needs some special handling to ensure it powers
up again after an EC reset.
BUG=b:150165131
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6da89de9401793a4e5c56a23c1018527819718cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40663
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, Deltaur’s I2C speed has not been tuned yet, so slow down
the H1 I2C to avoid I2C error for short term.
Error logs:
Reading cr50 TPM mode
I2C receive timeout
I2C read failed: bus 3 addr 0x50
BUG=b:154310066
TEST=Check H1 has no I2C error occurring and can be updated by gsctool.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I85a63c1ab9a51d254873377a36d56823af11f0a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40644
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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By default, the ACPI status method _STA returns false for the PS/2
keyboard and mouse device of the Wilco EC, so the OS does not enable it.
Enable these devices, by defining the macro SIO_EC_ENABLE_PS2K.
BUG=b:154790509
TEST=Check Keyboard is functional under OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I31c74ddb3608589e5a4753c7e487f250b112bb1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40745
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Cirque touchpad uses I2C_HID driver.
BUG=b:152931802
TEST=Touch pad can work well in the OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3f8d5abad2f153f395ba7e3f979ad3d2526e040c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Chip drivers not overrided if out of domain. Only device can get
override, so move the code under domain.
BUG=b:152924290,b:152931802
TEST=Touch screen and Touch pad can work well.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iaaa73e36ec268d26ebd3cafab79179fe22a926a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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If set variant early gpio table NULL, it will override the baseboard
table. Move early gpio table to variant level.
BUG=b:154310066
TEST=Check H1 has no I2C error occurs.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie4c4648ccf918446a499019a4f77f64e43a92c76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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When CONFIG_SEPARATE_VERSTAGE=n, all verstage code gets linked into the
appropriate calling stage (bootblock or romstage). This means that
ENV_VERSTAGE is actually 0, and instead ENV_BOOTBLOCK or ENV_ROMSTAGE
are 1. This keeps tripping up people who are just trying to write a
simple "are we in verstage (i.e. wherever the vboot init logic runs)"
check, e.g. for TPM init functions which may run in "verstage" or
ramstage depending on whether vboot is enabled. Those checks will not
work as intended for CONFIG_SEPARATE_VERSTAGE=n.
This patch renames ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE to try to
clarify that this macro can really only be used to check whether code is
running in a *separate* verstage, and clue people in that they may need
to cover the linked-in verstage case as well.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2ff3a3c3513b3db44b3cff3d93398330cd3632ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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SMBus uses 7-bits address, change it from 8-bits to 7-bits.
BUG=b:151702387
TEST=Check Memory SPD data is correct in console log.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1720b4d6aa0bc785ad86234b3523bb0676ec5c82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Deltan will be using the integrated Intel GbE for LAN
functionality. Deltaur will not have a LAN port, and so does not need
the GbE region. This patch adds a new FMAP descriptor file which
explicitly supports the GbE region (chromeos-gbe.fmd), and removes the
GbE region from chromeos.fmd. Deltan is then assigned chromeos-gbe.fmd,
and Deltaur is assigned chromeos.fmd.
BUG=b:150165131
TEST=emerge-deltaur coreboot chromeos-bootimage
and use ifdtool -p tgl -t image-delta{ur,n}.bin to make sure FMAP aligns with IFWI
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib93d5ba7f8dbf273ba7c1163022661ede1f44ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update memory topology for spd info. Deltan supports SODIMM and
Deltaur supports MEMORYDOWN.
BUG=b:151702387
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If314894325d6f222807030a36f8c4cefecfe5bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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H1 uses I2C3 in the HW schematics and connects to GPP_H6 and GPP_H7.
Previous setting was wrong so correct it.
BUG=b:150165131
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I43c18baea66b927d51689579a40a53f72b94ef36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40487
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Reference Arcada to add device tree for Cirque touchpad.
BUG=b:152931802
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia354702c8054b5826d45896f7bff268335726028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Reference Drallion to add device tree for Melfas touch screen.
BUG=b:152924290
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I7b0a42119891c6c2d5978d7f33eefffa2d62df76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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- Configure devicetree for enabling GbE on variant
and remove from baseboard.
- Configure Kconfig to enable GbE region.
- Configure fmd to incorporate GbE.
BUG=b:151102809
Cq-Depend: chrome-internal:2843183
Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I1c36b132546049e3e775585c41164072f4ece73e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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For Deltaur and Deltan variants return proper SKU ID based on EC
firmware type and sensor detect GPIO value
BUG=b:152544516
TEST=make build successful for deltan
Change-Id: I20a497739e5062400b093648c3a634203dec6105
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Update dq, dqs map based on deltan schematics.
Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This initial devicetree attempts to correctly configure the status of
each PCI device. Not all required drivers are instantiated, nor are
all of the SoC options fully selected yet.
PCIe root ports are enabled and clocks are assigned.
USB ports are assigned.
BUG=b:150165131
BRANCH=none
TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I911ec08b0db3647d131113a138fb74a55612fd62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This configuration sets up all of the GPIO pads for the first rev of
the board.
BUG=b:150165131
BRANCH=none
TEST=util/abuild/abuild -p none -t google/deltaur -x -a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4f6398808809492dcb345ccaa09e199fa35e40cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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Created a new Google baseboard using Tiger Lake named deltaur, taking
volteer as a starting point.
BUG=b:151102807
TEST=make build successful
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib98f328df22f39e7d9d625a3292954881ee15b15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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