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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Also includes lines sorted
Change-Id: Idf2b41f471f531b2a9c3e620563e3c658dea4729
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31267
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This board has more or less the same as the p5qpl-am except for DDR3
memory and different colors on the ports. Tested with Arch Linux with
kernel 4.20.0-arch1-1-ARCH.
What is tested and works:
- 800/1066/1333 MHz CPUs and DDR3 sticks at 800/1066 MHz
Some bugs are still present in the DDR3 raminit code though.
- Ethernet
- Internal programmer with both coreboot and stock firmware.
- PCI and PCIe x1 slots
- All USB ports
- S3 resume
- SATA ports
- PEG
- Rear audio output
Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/27089
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The initial timestamps are now pushed on the stack when entering the
romstage C code.
Tested on Asus P5QC.
Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This removes the need to synchronize the devicetree and the romstage
writing to FD.
Change-Id: I83576599538a02d295fe00b35826f98d8c97d1cf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30244
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2b3ad53766bc9cef5ae00392814a03a3e177ad35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30705
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3b9217a7d9a6d98a9c5e8b69fe64c260b537bb64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This mainboard has the BSEL straps hooked up to the SuperIO
similar to the ASUS P5GC-MX and might therefore require a restart.
Tested:
- FSB 800, 1067 and 1333MHz CPUs
- USB
- Ethernet
- Serial
- 2 DIMM slots
- SATA
- Libgfxinit (VGA)
TESTED with SeaBIOS (sercon disabled) and Linux 4.19.
Change-Id: Id845289081751ff8900e366592745f16d96f07c0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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