coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-12-05	nb/intel/i945: Remove apic 0 from devicetree	Arthur Heymans
2022-12-05	cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm	Arthur Heymans
2022-12-02	sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}	Elyes Haouas
2022-12-01	nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree	Arthur Heymans
2020-07-26	mb///devicetree.cb: Normalize disabled PIRQ values	Angel Pons
2020-05-18	mainboard///*.cb: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-09	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi
2020-03-18	mainboard/[a-f]*: Remove copyright notices	Patrick Georgi
2019-11-12	sb/intel/i82801gx: Add common LPC decode code	Arthur Heymans
2019-07-20	mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode`	Nico Huber
2019-06-06	sb/intel/i82801gx: Detect if the southbridge supports AHCI	Arthur Heymans
2019-06-05	mb/*/devicetree.cb: Remove unavailable PCIe ports	Arthur Heymans
2018-11-12	mb//: Harmonise FD and devicetree on boards featuring ICH7	Arthur Heymans
2017-07-12	mb/asus/p5gc-mx: Implement resume from S3 support	Arthur Heymans
2016-12-28	mb/asus/p5gc-mx: Fix and complete SIO devicetree options	Arthur Heymans
2016-12-22	mb/asus/p5gc-mx: Add mainboard	Arthur Heymans