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2023-02-16mb/amd/birman&mayan: Use relative address as EC FW locationZheng Bao
When the flash size is over 16M, the absolute address could be lager than 16M, which can not be taken by CBFS. For the relative address, it is more flexible. This is one of series of patches to support 32/64M flash. BUG=b:255374782 TEST=binary identical test on birman and mayan when CONFIG_BIRMAN_HAVE_MCHP_FW and CONFIG_MAYAN_HAVE_MCHP_FW are set as y. Change-Id: I65be3039cd3449bfb481ad87281b72e88a58bd45 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-15mb/amd/chausie,mayan: Use common missing APCB warningFred Reitberger
Use the common missing APCB warning when the APCB is missing Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie6303bc3457731bcac322770c4c08712f89fce3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-13soc/amd/phoenix: Expand APOB to 256KFred Reitberger
APOB on Phoenix is larger, so expand the reserved DRAM and MRC_CACHE regions to fit. This requires moving memory addresses around to prevent overlapping memory linker errors. TEST='./util/scripts/testsoc -K PHOENIX -K GLINDA' successfully builds all boards Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I42af7230ca5f09ba66b2b3c4f99ac3feac7feeea Reviewed-on: https://review.coreboot.org/c/coreboot/+/72905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-13mb/amd/mayan/board.fmd: Move MRC cacheFred Reitberger
The EFS must be located at the 128K offset. The combination of EC, MRC_CACHE, and FMAP push the start of the coreboot CBFS region to 128K, leaving no room for the CBFS headers for the EFS. Move the MRC_CACHE region to the end of the image. This matches the chromeos MRC_CACHE layout. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I3919fba40f22ee84b0a3eee1ac7b6e48c076d713 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-08mb/amd/mayan: update EC FW offset in spiromRitul Guru
update EC FW offset location in spirom to 0x81000 For mayan board EC FW is located at offset 0x81000 location, 0th location contains pointer to this EC FW location. Change-Id: I63c797e12ed131e8411c11379f4db9bcc29b49a2 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-04soc/amd/phoenix/chipset.cb: update USB portsFelix Held
Not exactly sure about the usb4_xhci controllers, but for now I assume those will behave like any other XHCI controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22384f58e245a1486793831d29d22e9c618f646c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-04soc/amd/phoenix/chipset.cb: add remaining PCI devicesFelix Held
The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference. Some devices will need to have ops added in future patches. Since the xhci_2 device isn't there any more, also drop it from the mainboard devicetrees. The actual USB port configuration on xhci_0 and xhci_1 is updated in the next patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-04soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2Felix Held
Now that the PCIe ports on device 1 are added, rename the aliases for the PCIe ports on device 2 to have a common naming scheme. For phoenix the device alias names are based on the device and function number the bridge is connected to. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72737 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31mb/amd: Include <gpio.h> instead of <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: I48191064fcee53ca843a537aa36bdbbd57736bf2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-22mb/amd/(birman|mayan): Update chromeos.fmd filesMartin Roth
Because the EFS is now fixed at 0xff020000, the ChromeOS RO region needs to be moved to the bottom of the ROM area to cover that space. The RO Region 6MiB, but you can't actually set 6MiB as RO - it's either 4 or 8MiB, so that's adjusted. To leave some room for the RW_LEGACY region, the two RW regions are adjusted to 3MiB each, which should be plenty. The GBB region had to be moved from the front of the WP_RO region to the end to avoid conflicting with the EFS, which needs to be inside the coreboot cbfs area. Also get rid of AMD_FWM_POSITION_INDEX. The FWM position is no longer needed. Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I683155ec0f4e6a62d862b9e2fa76af45f4cd5493 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-12soc/amd: Change Morgana codename to PhoenixMartin Roth
Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13soc/amd/morgana: Enable GPP clk req disablingFred Reitberger
Enable GPP clk req disabling on morgana after reviewing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13soc/amd/morgana: Update pci int defsFred Reitberger
Update pci int defs per preview of next ppr after rev 1.52, #57396 Update birman and mayan mainboards to remove deleted PIRQs. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I10e13784761f0b9245f0ca10e3cd07d396ec4224 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70379 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06mb/amd/mayan/gpio: Configure mayan GPIOsFred Reitberger
Configure mayan GPIOs per schematic 105-D59700-00A Rev 1.00 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I283afc716487fd8fa6d455194c382d87a3e6860b Reviewed-on: https://review.coreboot.org/c/coreboot/+/70207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-05mb/amd/mayan: Improve naming of EC FWFred Reitberger
Change the EC FW CBFS filename prefix to a more accurate "ec/" Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ic789df11160e3ffe7b7294b11e1fa80e3c3961ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/70206 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-27mb/amd/mayan: Add framework for morgana crb mayanRitul Guru
mayan is the reference board for the morgana SoC. It needs to be updated to match the actual board design as well. amd/mayan is started as a copy of amd/birman. Change-Id: Id6801e6c6e706ae3878ce9e2c3d6452964235148 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70010 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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