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2010-04-14drop quite a lot of dead code that did nothing but produce warnings and makeStefan Reinauer
the rest of the code unreadable. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-09copy_and_run.c is not needed twice, and it is used on non-car too.Stefan Reinauer
So move it to src/arch/i386/lib/cbfs_and_run.c Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-09Copy acpi blobs in two parts to make sure gcc does the right thing.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-08Clean up fidvid files using indent.Myles Watson
Remove some special print statements. In general, make them easier to compare. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-08Replace dual_core and quad_core CMOS (nvram) options with multi_core. Fix ↵Myles Watson
some white space. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-07move amd K8/Fam10 "bus detection" function prototypes to a common place.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5370 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-06No warnings day, next round.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-31This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c andStefan Reinauer
makes include/console/console.h and console/console.c usable both in __PRE_RAM__ and coreboot_ram stages. While debugging this, I removed an indirection from the e7520 ram init code (same as we did on a couple of other chipsets, removes some register pressure from romcc) Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code in cache_as_ram.inc) Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-30- drop unneeded Makefile.incStefan Reinauer
- drop ap_romstage from Fam10 boards, the mechanism was never used on Fam10 Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-30drop USE_INIT from mainboard Kconfig files, it's already set in src/KconfigStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-30unify cmos.layout wrt AMD extended configuration registers.Stefan Reinauer
This removes double preprocessor define warnings from many boards. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5323 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-29This drops the ASSEMBLY define from romstage.c, tooStefan Reinauer
(since it's not assembly code, this was a dirty hack anyways) Also run awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines mv $FILE.nonewlines $FILE on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c cut some holes into the source. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-29__PRE_RAM__ is now correctly specified in the Makefile. No need to hack it intoStefan Reinauer
romstage.c anymore Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-29This patch drops the coreboot CMOS checksum ranges from Kconfig becauseStefan Reinauer
the information is already specified in cmos.layout. coreboot is changed to use that version instead. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmai.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-29dualcore.h and quadcore.h are almost exactly the same. Stefan Reinauer
Only have multicore.h for both of them. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5311 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-28drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is moreStefan Reinauer
appropriate. Also, factor out post_code() for __PRE_RAM__ code and drop it from some mainboards. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-26Remove dead code and make white space more consistent for acpi_tables.cMyles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-261. Remove warnings and multiple blank lines.Zheng Bao
2. Mahogany uses GPIO9 to detect 80-pin IDE cable. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-24Get rid of type-punned pointer errors.Myles Watson
Defining AmlCode differently in different source files is a bit ugly... Creating a void * to do the casting is not exactly beautiful either... Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-23mahogany_fam10: rename apc_auto.c to ap_romstage.c like on all other boardsStefan Reinauer
that have one. Can we get rid of ap_romstage.c completely? It sounds like the wrong thing to do. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22Fix all the format string warnings.Myles Watson
Some other random warnings. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22printk_foo -> printk(BIOS_FOO, ...)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18Remove remaining uses ofPatrick Georgi
HAVE_FAILOVER_BOOT HAVE_FALLBACK_BOOT USE_FAILOVER_IMAGE USE_FALLBACK_IMAGE Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18Rework boolean expression (DeMorgan and all) forPatrick Georgi
better readability. Also remove failover.c files in mainboards, as they're not used anymore (and useless, too) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17Remove failover/fallback/normal handling in mainboards'Patrick Georgi
romstage.c. That's newconfig stuff. 1. In failover_process(), I removed the fallback/normal selection logic and kept the remaining hardware init in. The if-clauses' conditions are reverted to match. Remove #if failover||fallback guard. 2. Change cache_as_ram_main() to first call failover_process, then real_main unconditionally. 3. Move failover_process's code to the beginning of real_main, remove failover_process and its call in cache_as_ram_main. 4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same arguments, so no problem with that) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17trivial warning fixes, mostly for ACPI codeStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16The code can run on the Mahogany board, which is one of sample boardsZheng Bao
made by AMD. Its major features are: CPU: * AMD AM2+ * AMD Athlon 64 x2 * AMD Athlon 64 FX * AMD Athlon 64 * AMD Sempron CPUs System Chipset: * RS780E * SB700 On Board Chipset: * BIOS - SPI * Azalia CODEC - Realtek ALC888 * LPC SuperIO - ITE8718F(GX). * LAN - REALTEK 8111C * TPM - SLB9635TT1.2 Main Memory: * DDR II * 4 (Max 4GB) Expansion Slots: * PCI Express X16 slot*2 (PCI-E X8 Bus) * PCI Express X4 Slot*1 Intersil PWM: * Controller - Intersil 6323 Note: 1. The only difference to mahogany is the CPU is changed to K8 family 10. 2. The main structure of the code is based on serengeti_cheetah_fam10. I am a rookie to fam10. I am still confused about CONFIG_HT_CHAIN_UNITID_BASE and CONFIG_HT_CHAIN_END_UNITID_BASE. I set them as the way dbm690t does. And I have to modify the some fam10 code (see the patch ht_chain_unitid_base.patch). I dont know how to solve this. Please help. Updated findings: In h3finit.c, the code goes the AMD_CB_ManualBUIDSwapList(). The swaplist is {0x00, 0x00, 0xFF, 0x00, 0xFF}. I am trying to find the meaning of the list. The amdht wrapper needs to modify definitely. 3. With fam10 processor, the HT link can work in HT3. 4. The ACPI _PSS table is set staticly. The auto configuaration process doesnt seem to work correctly. 5. Currently the fam10 code in coreboot doesn't support DDR3. If you happen to get a board with DDR3 and you don't have the patience to wait, please find another board with DDR2. 6. It will take "Uncompressing image to RAM" about 1 minute. I know it is a issue for a long time. I disable the compressing currently. When the problem is fixed, we can re-enable it. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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