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2024-04-15mb/amd/*: Increase SMMSTORE size to 256KMatt DeVillier
Anything below 128K will cause SMMSTORE driver in edk2 to fail, since a minimum of (2) 64K blocks are needed. Increase the size to 256K to match other boards in the tree. Change-Id: I04d57ff7f74d79118652cfe227cf223375df6472 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81865 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18mb/51nb to mb/bytedance: Add SPDX license headers to Kconfig filesMartin Roth
Change-Id: I71dc3dd270b9a61c86b59031f898af37f0fea345 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80590 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-27soc/amd: use common ACPI_SCI_IRQ definitionFelix Held
ACPI_SCI_IRQ is defined as 9 for all AMD SoCs, so move the definition to the common amdblocks/acpi.h. Since all but Stoneyridge's soc/acpi.h are now empty, delete those files too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8210c98dc4cf2c6001d5273d132053278ff7fea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80222 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24mb/51nb to mb/gigabyte: Rename Makefiles from .inc to .mkMartin Roth
The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I422cb475723006ca42be93508fb0bf4b1e4e84d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80104 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-12-20treewide: Use show_notices target for warningsMartin Roth
This updates all warnings currently being printed under the files_added and build_complete targets to the show_notices target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01util/amdfwtool: Deal with psp position in flash offset directlyZheng Bao
It is based on work by Arthur Heymans, 69852. Get rid of the confusing "position index" and use the relative flash offset as the Kconfig setting instead. TEST=binary identical on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst (The test should be done with INCLUDE_CONFIG_FILE=n) Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-15mb/amd/chausie: Remove useless break after returnElyes Haouas
Change-Id: Iafc3735b6d903a4496828189db14b09d3c4d2081 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76432 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14mb/amd,google/*/port_descriptors: use dxio_link_hotplug_type enum valuesFelix Held
Use the proper dxio_link_hotplug_type enum values for the link_hotplug field in the DXIO descriptors to replace the magic values in the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb1513737e6022a668287dc80a39d96cda2b18d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76439 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-09soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetreeFelix Held
Instead of adding the new PCI IDs of the XHCI controllers in every new chip generation to the pci_xhci driver, bind the driver to the internal PCI devices of the XHCI controllers via the device ops statement in the chipset devicetree. The PCI device function of the XHCI2 controller in Mendocino can be either a dummy device or the XHCI controller, so the device ops are attached to that device in the mainboard devicetree instead. The Glinda code is right now just a copy of the Mendocino code, so it'll change in the future, but for consistency the equivalent changes to those in Mendocino are applied there too. Since the device ops are now attached to the devices via the static devicetree entry, also remove both the xhci_pci_driver struct and the amd_pci_device_ids array from drivers/usb/pci_xhci/pci_xhci.c. TEST=SSDT entries for the XHCI controllers are still generated on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22soc/amd/mendocino: drop code for non-existing eMMC controllerFelix Held
Mendocino and Rembrandt don't have an eMMC controller and also don't have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC related code from Mendocino. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8ec49a7084bdd62e480baee75a280fde8b13d01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-27mb/amd/birman,chausie: Enable SimNow capabilitiesFred Reitberger
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia7e594ca2b6ea3cd9d6f60e7dcd1ba6ebabf85cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-15mb/amd/chausie,mayan: Use common missing APCB warningFred Reitberger
Use the common missing APCB warning when the APCB is missing Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie6303bc3457731bcac322770c4c08712f89fce3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-31mb/amd: Include <gpio.h> instead of <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: I48191064fcee53ca843a537aa36bdbbd57736bf2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-25mb/amd/chausie/devicetree: enable mp2 deviceFelix Held
The mp2 PCI device is still present when no mp2 firmware is loaded. When this device isn't explicitly enabled in the mainboard's devicetree, the chipset devicetree default of the device being disabled is used. This results in coreboot's resource allocator not allocating resources to the device and since the bridge doesn't have enough MMIO space reserved, the Linux kernel can't assign resources to it. To fix this problem, enable the mp2 device in the mainboard's devicetree so that it gets its resources assigned by coreboot. TEST=Fixes the resource allocation for the mp2 PCI device. dmesg output before the patch: [ 0.210616] pci 0000:04:00.7: [1022:164a] type 00 class 0x118000 [ 0.210631] pci 0000:04:00.7: reg 0x18: [mem 0x00000000-0x000fffff] [ 0.210641] pci 0000:04:00.7: reg 0x24: [mem 0x00000000-0x00001fff] [ 0.210649] pci 0000:04:00.7: enabling Extended Tags [ 0.240570] pci 0000:04:00.7: BAR 2: no space for [mem size 0x00100000] [ 0.240572] pci 0000:04:00.7: BAR 2: failed to assign [mem size 0x00100000] [ 0.240574] pci 0000:04:00.7: BAR 5: assigned [mem 0xd05c6000-0xd05c7fff] dmesg output after the patch: [ 0.210483] pci 0000:04:00.7: [1022:164a] type 00 class 0x118000 [ 0.210501] pci 0000:04:00.7: reg 0x18: [mem 0xd0500000-0xd05fffff] [ 0.210515] pci 0000:04:00.7: reg 0x24: [mem 0xd06c6000-0xd06c7fff] [ 0.210524] pci 0000:04:00.7: enabling Extended Tags Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I680ef9798f2f0e7e0646f0fd30bef58398b7bf19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72197 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-01mb/amd/chausie: change AMD_FWM_POSITION_INDEX for non-chromeos caseFelix Held
Commit 2c102232e8f7 ("mb/amd/chausie,google/skyrim: increase RW_MRC_CACHE size to 120 kByte") increased the MRC cache size, but with the change the default AMD_FWM_POSITION_INDEX which is 5 for the 16MByte flash size, the amdfw part won't be placed on the expected position, since the cbfs header is in that exact location and cbfstool places the amdfw part right after that. Change the AMD_FWM_POSITION_INDEX to 4 for the non-chromeos builds to work around this. TEST=Non-chromeos chausie build now boots and doesn't fail any more before releasing the x86 cores from reset Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I89fe1d0672139e04070f05c6c8fa8955edcfc7ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/70133 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-15soc/amd: commonize generation of the PIC/APIC mapping tablesFelix Held
Now that we have a common init_tables in all mainboards using AMD SoCs, both the population of the fch_pic_routing and fch_apic_routing arrays and the definition of those arrays can be moved to the common AMD SoC code to not have the code duplicated in all mainboards. BUG=b:182782749 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10mb/amd/chausie/ec.c: Enable WLANFred Reitberger
Enable WLAN power and deassert the various radio disables. TEST=boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I2d21905001fa776c0d5c864d83dcd697e3febe0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/69319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-11-10mb/amd/chausie: Correct naming of EC FWFred Reitberger
Change the EC FW CBFS filename prefix to a more accurate "ec/" TEST=build and boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib9ee24ca06b29c74cc0a91f9e4789df00ba1ba53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-29mainboard/amd/chausie: Don't use APCB_FT6_UpdatableNikolai Vyssotski
This APCB binary is not used for coreboot builds. Coreboot does not support RW APCB. Change-Id: I4d317ae31cf226b5481619f1539abb6237033f7c Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-10-26mb/amd/bilby,birman,chausie,majolica: rework FCH IRQ mapping generationFelix Held
This ports the changes to the way the fch_pic_routing and fch_apic_routing arrays get populated from Mandolin to Bilby, Birman, Chausie and Majolica. This is a preparation to move the init_tables implementation to the common AMD SoC code in a later patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia957056b60dafbc52a9809a4563a348ad7443376 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26mb/amd,google: unify fch_irq_routing struct instance nameFelix Held
Use the same fch_irq_map name in all mainboards using the Picasso, Cezanne, Mendocino and Morgana instead of using a mainboard-specific name. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I035cffb9c6c8afd6bd115831e8eed4a395e2a7fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-26soc/amd/mendocino: Enable GPP clk req disabling for disabled devicesRobert Zieba
Enable GPP clk req disabling for disabled PCIe devices. If a clk req line is enabled for a PCIe device that is not actually present and enabled then the L1SS could get confused and cause issues with suspending the SoC. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-26soc/amd/common/include: introduce and use FCH_IRQ_ROUTING_ENTRIESFelix Held
Instead of using magic constants for the fch_pic_routing and fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the common code headers and use this definition. This also allows to drop the static assert for the array sizes. In the Stoneyridge mainboard code the equivalent arrays are named mainboard_picr_data and mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array size there. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-26mb/amd,google: move fch_irq_routing struct definition to soc/amdFelix Held
Define the fch_irq_routing struct once in a common header file instead of in every mainboard's code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I11d9000b6ed7529e4afd7f6e8a7332c390da6dab Reviewed-on: https://review.coreboot.org/c/coreboot/+/68817 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-21mb/google/skyrim/port_descriptors: update DDI for MDN and ChausieJason Nien
Add two new types for MDN DDI descriptor BUG=b:228284940 TEST=Normal boot and S0i3 cycles Signed-off-by: Jason Nien <finaljason@gmail.com> Change-Id: I02793f032f9855dac202a5aca8666c26426d6cb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66847 Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-09-08mb/amd/chausie/ec.c: Clean up definesFred Reitberger
Use the BIT() macro instead of reinventing the wheel. TEST=timeless builds are identical Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I873013feebd30c86290dda692c7b137d5f3c4729 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-31mb/amd/chausie/Kconfig: Re-enable ESPI_RETAIN_PORT80Fred Reitberger
Chausie fails to boot without this option set. Enable in the mainboard rather than the SoC Kconfig to not impact Skyrim. TEST=boot to OS Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9f2a1be9eddb9e17407d00ff50ceb70a2718ce3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-11treewide: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used in references to Skyrim. coreboot has references to sabrina both in directory structure and in files. This will make life difficult for people looking for Mendocino support in the long term. The code name should be replaced with "mendocino". BUG=b:239072117 TEST=Builds Cq-Depend: chromium:3764023 Cq-Depend: chromium:3763392 Cq-Depend: chrome-internal:4876777 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-07mb/amd/chausie: Add Kconfig prompts to EC stringsMarshall Dawson
Make the default Microchip EC firmware path/to/file values overridable by adding prompts to the strings. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I300f78a11960dbe193165fcb379b7190e3de4545 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-06-14mb/amd/chausie/Kconfig: enable PCIe power managementFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia24a502994d24f3341273c5e6f768687ad20baf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65113 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-14mb/amd/chausie/devicetree: add PCIe clock output configurationFelix Held
The general purpose PCIe clock outputs 0, 1 and 3 are used with their corresponding clock request pins, so set the gpp_clk_config to GPP_CLK_REQ for those and disable the unused output 2. This matches the DXIO descriptor in port_descriptors.c. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38ab8d6d824617509fdd18f06d5593889ec50666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65112 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-12mb/amd/chausie,google/skyrim: increase RW_MRC_CACHE size to 120 kByteFelix Held
The APOB data in DRAM is larger than the 96 kBytes of RW_MRC_CACHE, so it won't fit in the flash and makes soc_update_apob_cache return early before writing the APOB data from DRAM into the flash with this warning: [WARN ] RAM APOB data is too large 1db18 > 18000 Increasing the RW_MRC_CACHE size to 120 kByte fixes this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I763d20f504d4f5b7cea68f21f409de9a1035f440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64555 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-10mb/chausie/ec: Set MS bit in SW02Fred Reitberger
Set the MS bit in EC SW02 register to enable s0i3 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I97b6adf48b49635251c70015f1d87fd8ca11d539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-24mb/amd/chausie,majolica: don't select HAVE_ACPI_RESUMEFelix Held
The Chausie and Majolica boards use S0ix which is mutually exclusive with S3, so don't select HAVE_ACPI_RESUME. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d1bf33ad017dfbf908e0a195949998668c8e137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64605 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16mb/amd/chausie/devicetree: add USB PHY configurationFelix Held
Specify the USB PHY settings in the devicetree instead of relying on the FSP defaults. The USB PHY configuration for Chausie are taken from the internal UEFI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cc38e6e26d53802773fe3c405415de15cca98a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-27mb/amd/chausie: Auto-detect DDI typeFred Reitberger
Read the EEPROM to detect the DDI type. BUG=b:225139014 TEST=Boot chausie and correctly detect display card type Change-Id: I3ddd8789e75d5da2ea1e6ce9a81e5ebb2cf3c007 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-27mb/amd/chausie: Add EC supportFred Reitberger
Add support for the chausie EC. Use EC to configure default board GPIO settings. Change-Id: I3e59e17644cddf1a508614f90c20561bde2691fb Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-27md/amd/chausie: call espi_switch_to_spi1_padsFred Reitberger
Chausie uses the spi1 pads for eSPI Change-Id: Iee9b92dd9b4e84764568ec3cc8d1fce731e0d1a7 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63866 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-07ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki
Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-06ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki
The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-01mb/amd/chausie/port_descriptors: clean up variable namesFred Reitberger
Remove "czn" from the variable names since chausie does not use cezanne. TEST=Timeless build Change-Id: I8cc854f4c60707c7fec5cd7fef1c4550883cd45a Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-30mb/amd/chausie/port_descriptors: update DDI descriptorsFelix Held
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I31db6c138a21dc22e7aa473f2215ca2c7594326c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63163 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/amd/chausie/devicetree: update PCI root portsFelix Held
Only enable the PCIe root ports that have corresponding DXIO descriptors and also update the comments to have them match the actual hardware configuration. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I378c620abb6e52de680669b6edd228874153e399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63162 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30mb/amd/chausie/port_descriptors: update DXIO descriptorsFelix Held
Change the DXIO descriptors to match the default PCIe lane mapping on the chausie board. With this configuration and a board-level rework to bypass the EC control of the NVMe SSD power supply rail, this configuration results in the SSD being detected on the root port on bus 0 device 2 function 3 and usable as boot device. This was also validated against the schematics revision B. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63161 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-21mb/amd/chausie: add APCB binaries if availableFelix Held
The APCB files that provide the firmware components running on the PSP some mainboard-specific information like the DRAM interface configuration. Those files aren't yet in the upstream 3rdparty/blobs repository, so only add those files if they are present and print that no APCB was added and the image won't boot if they aren't present. TEST=Both cases behave as expected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-21mb/amd/chausie/chromeos.fmd: increase A/B RW section size to 4MBNikolai Vyssotski
To have enough space in the A/B RW sections, increase those sizes to 4 MByte and decrease the RO section size to 6 MByte to free up the space needed for that. Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-19mb/amd/chausie/devicetree: set PSPP policy to DXIO_PSPP_DISABLEDFelix Held
Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, the PSPP policy will be switched to balanced again. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-14mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devicesFelix Held
GFX HDA is the audio controller that provides audio output via the external display connection, ACP is the audio coporcessor for the on- board audio codec and XHCI2 is the third XHCI controller that provides one USB 2.0 port. All those devices are used, so enable them in the board's devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62571 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-01mb/amd/chausie: Always enable developer modeRaul E Rangel
Chausie doesn't have recovery mode buttons so it's impossible to manually enter recovery mode to enable developer mode. This means we need to force developer mode. BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28mb/amd/chausie/Kconfig: Add EC FW to RO_REGION_ONLYFred Reitberger
Include chausie EC and EFS only in the RO region when building with vboot. Without this, the EC is also added to the FW_MAIN_A and FW_MAIN_B regions. Change-Id: I78de8bd639232b9fb6d775b77ecd892f28514614 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-25mb/amd/chausie/devicetree: add i2c_scl_resetFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I23ec6bcb6a2b3627866165972fd6ba1c75367533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62188 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25mb/amd/chausie/devicetree: enable I2C controllersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97f37c45ffe945e6bb071c8205343943edc524ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61871 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21mb/amd/chausie/chromeos.fmd: resize EC size in FMAP to 4kByteFelix Held
Only the info about the location of the EC firmware will be stored right at the beginning of the flash, so the size can be reduced to 4kByte which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE file itself is smaller than this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21mb/amd/chausie/Kconfig: Move EC firmware image in CBFSFred Reitberger
Move the EC to a location that does not conflict with where the main CBFS is in the chromeos FMAP Change-Id: I28c84cbe2ff10d45383d896ae4f942ee49eb15c0 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62190 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-19mb/amd/chausie: increase RW_MRC_CACHE size in FMAPFelix Held
On Sabrina SoCs the size of the APOB has increased, so the size of the RW_MRC_CACHE FMAP sections needs to be increased in order for the data to still fit in the corresponding FMAP partition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib31b918aba90dd507b47aec9e1f75c138857cd02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62155 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17mb/amd/chausie: Add EC blob into CBFSFred Reitberger
Add chausie EC blob into CBFS at specified location Change-Id: I48de08a18054efbda655e1563a539ff2ba7a38a6 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15mb/amd/chausie: initialize KBRST and EC flash sharing pins in bootblockFelix Held
The SPI ROM REQ/GNT pins are used in systems where the EC and the APU share one flash chip to make sure that not both devices will try to access the flash at the same time. The firmware running before the x86 cores are released from reset has likely already done this, but do it again in bootblock just to be sure. The KBRST_L pin can be used to reset the APU from the EC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5af285ac222ed6625f498d82360f2d1cc522df2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-13mb/amd/chausie: update GPIO for chausieFred Reitberger
Add/update initial GPIO pin descriptions and initialization types for chausie mainboard. Change-Id: I14ea0e1086f626398a867896ee81ce07cf530182 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-12mb/amd/chausie/mainboard: add initial IRQ routingFelix Held
This IRQ routing info is taken from mb/google/guybrush. This should fix these errors: [ 0.655051] i2c_designware AMDI0010:00: IRQ index 0 not found [ 0.659239] i2c_designware AMDI0010:01: IRQ index 0 not found [ 0.663198] i2c_designware AMDI0010:02: IRQ index 0 not found [ 0.667200] i2c_designware AMDI0010:03: IRQ index 0 not found Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8c85c8e4b1c860d6ca25060353355f703a49e1e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-04soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATAFelix Held
Sabrina has no SATA controller, so remove the corresponding PIRQ mapping. This was verified with PPR #57243 Rev 1.53. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I98ffa3675c361e8a74c50ebfc37e79ae63dacc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03mb/amd/chausie/devicetree: update I2C RX levels to match board designFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie5d5f5441132e5b0d8991d07d4dde994fc17ab64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03soc/amd/*/i2c: factor out common I2C pad configurationFelix Held
The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-27soc/amd/sabrina/chipset.cb: update USB portsFelix Held
The corresponding mainboard design guide was used as a reference here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie61af7dab35b560d2eec1ea62058f3a4dad5cb0f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: update PCI devices in devicetree.cbFelix Held
Also update mb/amd/chausie accordingly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idb4dcffa48c3dbdcffb66f1398b99ee96562efb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25mb/amd/chausie: add mainboard as copy of mb/amd/majolicaFelix Held
To have the new AMD Sabrina SoC code tested, add the AMD Chausie mainboard as a copy of Majolica. This patch also changes the name from Majolica to Chausie, selects the Sabrina SoC instead of the Cezanne SoC and comments out the APCB_SOURCES since those aren't available in the 3rdparty/blobs repository yet. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic7b18f7a6ae5b8365234dd1227e0b1f7f37279da Reviewed-on: https://review.coreboot.org/c/coreboot/+/61079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-27 19:28:27 +0000