summaryrefslogtreecommitdiff
path: root/src/include
AgeCommit message (Collapse)Author
2021-07-20lib/cbfs,device/pci_rom: Move cbfs_boot_map_optionrom and modernizeRaul E Rangel
These methods are oprom specific. Move them out of CBFS. I also deleted the tohex methods and replaced them with snprintf. BUG=b:179699789 TEST=Boot guybrush and see oprom still loads Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I03791f19c93fabfe62d9ecd4f9b4fad0e6a6146e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-07-20soc/intel/alderlake: Add support for I2C6 and I2C7Varshit B Pandya
As per the EDS revision 1.3 add support for I2C6 and I2C7. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Id918d55e48b91993af9de8381995917aef55edc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55996 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-19lib/prog_loaders: Add payload_preloadRaul E Rangel
This method will allow the SoC code to start loading the payload before it is required. BUG=b:177909625 TEST=Boot guybrush and see read/decompress drop by 23 ms. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifa8f30a0f4f931ece803c2e8e022e4d33d3fe581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-18lib/thread: Move thread_run and thread_run_until outside of #if guardRaul E Rangel
This will cause a linker error if these methods are used outside ramstage. BUG=b:179699789 TEST=compile guybrush w/ and w/o COOP_MULTITASKING Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If9983fca939c8a15fa570481bfe016a388458830 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56352 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/hardwaremain: Drop boot_state_current_{block,unblock}()Raul E Rangel
There are no more callers. BUG=b:179699789 TEST=Compile guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I522f17c0e450641c0a60496ba07800da7e39889c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56389 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Make thread_run not block the current stateRaul E Rangel
If a thread wants to block a state transition it can use thread_run_until. Otherwise just let the thread run. `thread_join` can be used to block on the thread. Boot states are also a ramstage concept. If we want to use this API in any other stage, we need a way of starting a thread without talking about stages. BUG=b:179699789 TEST=verify thread_run no longer blocks the current state Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3e5b0aed70385ddcd23ffcf7b063f8ccb547fc05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56351 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Add thread_handleRaul E Rangel
The thread_handle can be used to wait for a thread to exit. I also added a return value to the thread function that will be stored on the handle after it completes. This makes it easy for the callers to check if the thread completed successfully or had an error. The thread_join method uses the handle to block until the thread completes. BUG=b:179699789 TEST=See thread_handle state update and see error code set correctly. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie6f64d0c5a5acad4431a605f0b0b5100dc5358ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56229 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Add mutexRaul E Rangel
We need a way to protect shared resources. Since we are using cooperative multitasking the mutex implementation is pretty trivial. BUG=b:179699789 TEST=Verify thread lock and unlock. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ife1ac95ec064ebcdd00fcaacec37a06ac52885ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/56230 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Rename thread_cooperate and thread_prevent_coopRaul E Rangel
Renaming them to thread_coop_disable()/thread_coop_enable() makes them sound like a pair. BUG=b:179699789 TEST=Boot guybrush to OS Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1d70c18965f53e733e871ca03107270612efa4fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/56357 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Allow nesting thread_cooperate and thread_prevent_coopRaul E Rangel
This change allows nesting critical sections, and frees the caller from having to keep track of whether the thread has coop enabled. BUG=b:179699789 TEST=Boot guybrush with SPI DMA Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I325ab6181b17c5c084ca1e2c181b4df235020557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56350 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18lib/thread: Add thread_yield helper methodRaul E Rangel
This helper method is just a shorthand for `thread_yield_microseconds(0)`. I think it makes it clear that we want to yield a thread without delaying. BUG=b:179699789 TEST=build test Suggested-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id8b60c35b183cff6871d7ba70b36eb33b136c735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56349 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17soc/amd/common/block/graphics: add GPU PCI ID for BarceloFelix Held
Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify that that is the one for Cezanne. BUG=b:193888172 Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17cpu/intel: Add dedicated file to grow Intel CPUIDsSubrata Banik
This patch removes all local `CPUID_` macros from SoC directories and creates a common cpu_ids.h inside include/cpu/intel/cpu_ids.h. SoC users are expected to add any new CPUID support into cpu_ids.h and include 'cpu/intel/cpu_ids.h' into respective files that look for `CPUID_` macro. Note: CPUIDs for HSW, BDW and Quark are still inside the respective directory. Change-Id: Id88e038c5d8b1ae077c822554582410de6f4a7ca Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-16include/cpu/amd/msr: don't redefine the IA32_BIOS_SIGN_ID MSRFelix Held
Change-Id: Iff19ae495fb9c0795dae4b2844dc8e0220a57b2c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-15drivers: spi_flash: Add Fast Read Dual I/O supportJulius Werner
The Fast Read Dual Output and Fast Read Dual I/O commands are practically identical, the only difference being how the read address is transferred (saving a whooping 2 bytes which is totally irrelevant for the amounts of data coreboot tends to read). We originally implemented Fast Read Dual Output since it's the older command and some older Winbond chips only supported that one... but it seems that some older Macronix parts for whatever reason chose to only support Fast Read Dual I/O instead. So in order to make this work for as many parts as possible, I guess we'll have to implement both. (Also, the Macronix device ID situation is utter madness with different chips with different capabilities often having the same ID, so we basically have to make a best-effort guess to strike a trade-off between fast speeds and best chance at supporting all chips. If this turns out to be a problem later, we may have to add Kconfig overrides for this or resort to SFDP parsing, although that would defeat the whole point of trying to be fast.) BUG=b:193486682 TEST=Booted CoachZ (with Dual I/O) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia1a20581f251615127f132eadea367b7b66c4709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-14src/device: Remove DEVICE_PATH_ESPI & DEVICE_PATH_LPCMartin Roth
The ESPI & LPC keywords were added for the zork program, but it was found that they weren't needed, so they were never used. The previous patch removes them from sconfig, so now they aren't needed in coreboot. BUG=None TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9ae7817bb63d69ee272103b2d1186f125e188950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56278 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14thread: Add missing static inlineRaul E Rangel
BUG=b:179699789 TEST=Able to compile with the rest of the patch train. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9e3cfb55e48737c378bde53ae0e5d7cbf5e41bc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-14include/cpu/amd/msr: add and use MC_CTL_MASK macroFelix Held
Add this macro to be able to conveniently access the MC_CTL_MASK register for each MCA bank. Also drop the unused definitions for MC1_CTL_MASK and MC4_CTL_MASK. Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msrFelix Held
This MSR isn't an architectural MSR, so it shouldn't be in the common x86 MSR definition header file. From family 17h on this register has moved to a different location. Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14include/cpu/x86/msr: add mca_clear_status functionFelix Held
In multiple locations within the coreboot tree all available IA32_MC_STATUS registers are cleared, so add this to the common code to avoid duplication of code. Change-Id: I04af23c16021b0ce90f7105f7a3856bd26ffa736 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56258 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/intel/alderlake: Add GFx Device ID 0x46a6Maulik V Vaghela
This CL adds support for new ADL graphics Device ID 0x46a6. TEST=Build and boot Adlrvp board Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56026 Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14include/cpu/x86/msr: introduce IA32_MC_*(x) macrosFelix Held
When accessing the MCA MSRs, the MCA bank number gets multiplied by 4 and added to the IA32_MC0_* define to get the MSR number. Add a macro that already does this calculation to avoid open coding this repeatedly. Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56243 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISCFelix Held
Those registers are architectural MSR and this also gets them in line with IA32_MC0_CTL and IA32_MC0_STATUS. Also move them below the definitions for IA32_MC0_STATUS, so that the numbers of the MSRs are ascending. Change-Id: Icef6526c896720248f5b648ddf1a271bdf46917c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56235 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12include/cpu/x86/msr: fix MCG_CTL_P definitionFelix Held
MCG_CTL_P is bit 8 of the IA32_MCG_CAP MSR and not bit 3. Bits 0-7 of that MSR contain the number of MCA banks being present on the CPU. At the moment this definition of MCG_CTL_P is unused. Change-Id: I39a59083daa5c2db11a8074d5c4881bf55688f43 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-12include/cpu/x86/msr: add mca_get_bank_count functionFelix Held
In multiple locations within the coreboot tree the IA32_MCG_CAP MSR gets read and masked with MCA_BANKS_MASK to get the number of available MCA banks on the CPU, so add this to the common code to avoid duplication of code. Change-Id: Id118a900edbe1f67aabcd109d2654c167b6345ea Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-07-12acpi: Add function to simplify If (CondRefOf (..)) sequencesTim Wawrzynczak
The new function is called acpigen_write_if_cond_refof(), and it must be paired with a following acpigen_write_if_end() call. Change-Id: I6e192a569f550ecb77ad264275d52f219eacaca1 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-07-06arch/x86: Use ENV_X86_64 instead of _x86_64_Patrick Rudolph
Tested on Intel Sandybridge x86_64 and x86_32. Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-01device: Clean up resource utility function signaturesKyösti Mälkki
Drop extern declarations from functions. Declare resource arguments as const. Change-Id: I7684cc7813bad805c39a762892636818279ac134 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55475 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01SMBIOS: Drop now-unnecessary unionsAngel Pons
Now that the refactoring is complete, the unions for the table header are no longer needed. Therefore, drop them. Change-Id: I4e170e84a12646386d3fd84ae973dd6c18f25809 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01SMBIOS: Introduce `smbios_full_table_len` functionAngel Pons
Introduce the `smbios_full_table_len` function to consolidate table length calculation. The case where the length of a table equals the length of the structure happens when a table has no strings. Change-Id: Ibc60075e82eb66b5d0b7132b16da000b153413f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01SMBIOS: Introduce `smbios_carve_table` functionAngel Pons
Factor out some boilerplate code into a helper `smbios_carve_table` function, which zeroes out the table memory and fills in the header fields common to all tables. Change-Id: Iece2f64f9151d3c79813f6264dfb3a92d98c2035 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-07-01SMBIOS: Introduce struct for SMBIOS table headerAngel Pons
All SMBIOS `type X` tables start with the same 4-byte header. Add a struct definition for it, and use it where applicable. The union is temporary and allows doing the necessary changes in smaller commits. Change-Id: Ibd9a80010f83fd7ebefc014b981d430f5723808c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-25Asm code: Use NO_EARLY_BOOTBLOCK_POSTCODES to remove Asm port80sMartin Roth
Expand NO_EARLY_BOOTBLOCK_POSTCODES to all of the early assembly code in bootblock. BUG=b:191370340 TEST: Build with & without the option enabled Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Idb4a96820d5c391fc17a0f0dcccd519d4881b78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-22soc/intel/car: Add support for bootguard CARArthur Heymans
Bootguard sets up CAR/NEM on its own so the only thing needed is to find free MTRRs for our own CAR region and clear that area to fill in cache lines. TESTED on prodrive/hermes with bootguard enabled. Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-21soc/intel/common: Add InSMM.STS supportAngel Pons
Tested on HP 280 G2, SMMSTORE v1 and v2 still work. Other tests: - If one does not set BIOS_CONTROL bit WPD, SMMSTORE breaks. - If one does not write the magic MSR `or 1`, SMMSTORE breaks. Change-Id: Ia90c0e3f8ccf895bfb6d46ffe26750393dab95fb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-21soc/intel/alderlake: Add GFx Device ID 0x46b3Meera Ravindranath
List of changes: 1. Add new GFx ID 0x46B3 into device/pci_ids.h 2. Update new GFx ID into common graphics.c 3. Add new GFx ID description into report_platform.c TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I4343c7343875eb40c2955f6f4dd98d6446852dc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-06-21include/pci_def.h: Add some PCI Power Management CSR bitsTim Wawrzynczak
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I84c8470764a4e6e09220044966111ffe72078099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55674 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-19soc/intel/common/block/smm: Add `mainboard_smi_finalize`Aseda Aboagye
This commit adds a method called `mainboard_smi_finalize` which provides a mechanism for a mainboard to execute some code as part of the finalize method in the SMM stage before SoC does its finalization. BUG=b:191189275 BRANCH=None TEST=Implement `mainboard_smi_finalize` on lalala and verify that the code executes in SMM. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: If1ee63431e3c2a5831a4656c3a361229acff3f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-17device: Add helper function devfn_disable()Subrata Banik
devfn_disable() function is used to disable a device based on given bus, device function number. This function checks if the device is at enable state and disables the device. Change-Id: Ia4a8bfec7fc95c729a5bb156f88e9aab3bf5dd41 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-15cpu/intel/msr.h: Sort MSRs in ascending orderAngel Pons
Sort MSR definitions in ascending order to keep things organized. Change-Id: Iadfd28014dc6f41dae7b52b1550c699c89fe8bdc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-06-15cpu/intel/msr.h: Add license headerAngel Pons
This is most likely an oversight. Given that the coreboot project as a whole is licensed as GPLv2, add a GPL-2.0-only SPDX license identifier. Change-Id: I1acaf901e1426bd6747f8a772a498a0005b457fa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-14ACPI: Refactor use of global and device NVSKyösti Mälkki
After ChromeOS NVS was moved to a separate allocation and the use of multiple OperationRegions, maintaining the fixed offsets is not necessary. Use actual structure size for OperationRegions, but align the allocations to 8 bytes or sizeof(uint64_t). Change-Id: I9c73b7c44d234af42c571b23187b924ca2c3894a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-14ChromeOS: Separate NVS from global GNVSKyösti Mälkki
Allocate chromeos_acpi in CBMEM separately from GNVS. Change-Id: Ide55964ed53ea1d5b3c1c4e3ebd67286b7d568e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-14lib/hardwaremain.c: Hide preprocessor guards in headerAngel Pons
The `location` member of `struct boot_state_callback` is conditionally guarded depending on `CONFIG(DEBUG_BOOT_STATE)` using preprocessor. It is probably intended to save some space when the `location` strings do not get printed. However, directly using the `location` member without any guards will cause a compile-time error. Plus, preprocessor-guarded code gets nasty really quickly. In order to minimise preprocessor usage, introduce the `bscb_location` inline helper function, which transforms the compile-time error into a link-time error. It is then possible to substitute preprocessor guards with an ordinary C `if` statement. Change-Id: I40b7f29f96ea96a5977b55760f0fcebf3a0df733 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-11cpu/x86/lapic: Replace LOCAL_APIC_ADDR referencesKyösti Mälkki
Note that there are assumptions about LAPIC MMIO location in both AMD and Intel sources in coreboot proper. Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Drop read/write_around aliasesKyösti Mälkki
Change-Id: Ia3935524e57885ca79586f1f4612020bb05956ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-10cpu/x86/lapic: Separate stop_this_cpu()Kyösti Mälkki
Function is needed with PARALLEL_MP and excluding guard will be added to the source file. The incompatibilities with X2APIC_SUPPORT have been fixed so the exclusion is removed here too. Change-Id: I5696da4dfe98579a3b37a027966b6758f22574aa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-10cpu/x86/lapic: Add lapic_busy() helperArthur Heymans
Change-Id: Ife127d6dc8241cccb9d52236a9152da707f0e261 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55191 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Add lapic_send_ipi() helperArthur Heymans
Change-Id: I7207a9aadd987b4307ce8b3dd8dbfd47d0a5768e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55190 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Do not inline some utility functionsKyösti Mälkki
They are not __always_inline and specially enable_lapic() will become more complex to support X2APIC state changes. Change-Id: Ic180fa8b36e419aba07e1754d4bf48c9dfddb2f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55258 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Add lapic_update32() helperKyösti Mälkki
Change-Id: I57c5d85d3098f9d59f26f427fe16829e4e769194 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55187 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10cpu/x86/lapic: Regroup LAPIC accessorsKyösti Mälkki
Change-Id: I4347fc6542f59f56bd8400181efa30247794cf96 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55186 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10include/limits.h: Add file (read: borrow from Linux)Angel Pons
Copied from Linux file `include/vdso/limits.h` with some adjustments. Change-Id: I427d88b1d630fdc3c3e9c1b0e475adbf448d801a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55319 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-10device/pnp: Always provide `pnp_unset_and_set_config`Angel Pons
The `pnp_unset_and_set_config` function was only available when building with `ENV_PNP_SIMPLE_DEVICE` set. Add the complementary definition using device pointers, for the sake of completeness. Change-Id: I2a21e635f41f3f786057500fa96a2b3116e30d76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Máté Kukri <kukri.mate@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-06-10stddef.h: Use compiler macros for built-in integer typesJacob Garber
ptrdiff_t, wchar_t, and wint_t are all integer types built-in to the C language (as opposed to being library-only types defined in a header). In the past we had to define these typedefs ourselves because of romcc, but now that it's gone we should use the GCC-provided macros to select the types the compiler expects. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I0874eddf780b6e41ce773ad8b4faa595e4bbd8a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-06-09device/dram: Add LPDDR4 utilitiesRob Barnes
Add lpddr4.c utility file with lpddr4_speed_mhz_to_reported_mts. Fill in lpddr4_speeds using JDEC 209-4C table 210. LPDDR4 SPD decoding utilities are not included since there isn't a present need. BUG=b:184124605 TEST=Build and run on guybrush Change-Id: Id8ddfc98fff4255670c50e1ddd4d0a1326265772 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-09device: Add helper function is_devfn_enabled()Subrata Banik
is_devfn_enabled() function helps to check if a device is enabled based on given device function number. This function internally called is_dev_enabled() to check device state. Change-Id: I6aeba0da05b13b70155a991f69a6abf7eb48a78c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-09cpu/x86/lapic: Add Kconfig choice LAPIC_ACCESS_MODEKyösti Mälkki
Allows compile-time optimisation on platforms that do not wish to enable runtime checking of X2APIC. Legacy lapic_cpu_init() is incompatible so there is dependency on PARALLEL_MP. Also stop_this_cpu() is incompatible, so there is dependency on !AP_IN_SIPI_WAIT. Since the code actually lacks enablement of X2APIC (apparently assuming the blob has done it) and the other small flaws pointed out in earlier reviews, X2APIC_RUNTIME is not selected per default on any platform yet. Change-Id: I8269f9639ee3e89a2c2b4178d266ba2dac46db3f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2021-06-08acpi: drop weak implementation of acpi_soc_get_bert_regionFelix Held
acpi_soc_get_bert_region only gets called when a chipset's Kconfig selects the ACPI_BERT option in which case the chipset code needs to implement this function. In the case of acpi_soc_get_bert_region not being implemented, but ACPI_BERT being selected for a chipset this patch changes the behavior from never generating a BERT ACPI table to a build error which is more obvious and easier to catch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id479fce823d8534a7790f39125d1a2b3635fc029 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55277 Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-08acpi: rework BERT ACPI table generation logicFelix Held
Check if the ACPI_BERT Kconfig option is selected and only then try to generate the BERT table. Also remove the acpi_is_boot_error_src_present weak function from the ACPI global compilation unit and use the return value of acpi_soc_get_bert_region to determine if there is a valid BERT region with logged errors. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2a281f5f636010ba3b2e7e097e9cf53683022aea Reviewed-on: https://review.coreboot.org/c/coreboot/+/55054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-08soc/intel: Add Alder Lake's GT device IDSridhar Siricilla
Add Alder Lake specific graphics device ID. The document# 641765 lists the id 0x46a8. TEST=Verify boot on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6f36256505a3e07c6197079ea2013991e841401b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55256 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07cpu/x86/lapic: Declare start_cpu() staticKyösti Mälkki
This is for the !PARALLEL_MP paths. Change-Id: If4b91834a1b6de2a902ab914610ab76c1423f1e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55188 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07acpi: rename acpi_soc_fill_bert and add return valueFelix Held
The return value indicates if the function has found valid BERT data and wrote them to the region and length parameters. This will be used in a follow-up patch to remove the acpi_is_boot_error_src_present function call in the common code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaaa3eed51645e1b3bc904c6279d171e3a10d59be Reviewed-on: https://review.coreboot.org/c/coreboot/+/55053 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07acpi/device: Add ability to generate proper _STA for PowerResourceRaul E Rangel
acpi_device_add_power_res currently generates a `_STA` method hardcoded to ON. This change enables the ability to generate a `_STA` method that queries the status of the GPIOs to determine if the power resource is ON or OFF. BUG=b:184617186 TEST=Dump SSDT table for guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I91410556db002c620fd9aaa99981457808da93a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-01acpi: drop unused parameter from acpi_soc_fill_bertFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic354824468f016a7857c6990024ae87db6fd00bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
2021-05-30lib/rtc: Add sanity check for time and dateWerner Zeh
Add a function to check sanity of a given RTC date and time. Invalid values in terms of overrun ranges of the registers can lead to strange issues in the OS. Change-Id: I0a381d445c894eee4f82b50fe86dad22cc587605 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-28option: Turn CMOS option backend into choiceAngel Pons
In order to add more option backends, transform the current CMOS option backend into a Kconfig choice. Replace the `select` directives, as they cannot be used with choice options. Change-Id: Id3180e9991f0e763b4bae93a92d40668e7fc99bc Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-28cpu/x86/entry16.S: Make Intel CBnT TOCTOU safeArthur Heymans
Intel CBnT (and Boot Guard) makes the chain of trust TOCTOU safe by setting up NEM (non eviction mode) in the ACM. The CBnT IBB (Initial BootBlock) therefore should not disable caching. Sidenote: the MSR macros are taken from the slimbootloader project. TESTED: ocp/Deltalake boot with and without CBnT and also a broken CBnT setup. Change-Id: Id2031e4e406655e14198e45f137ba152f8b6f567 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-05-27cbmem: Introduce "early" init hooks for consoleJulius Werner
Over the last couple of years we have continuously added more and more CBMEM init hooks related to different independent components. One disadvantage of the API is that it can not model any dependencies between the different hooks, and their order is essentially undefined (based on link order). For most hooks this is not a problem, and in fact it's probably not a bad thing to discourage implicit dependencies between unrelated components like this... but one resource the components obviously all share is CBMEM, and since many CBMEM init hooks are used to create new CBMEM areas, the arbitrary order means that the order of these areas becomes unpredictable. Generally code using CBMEM should not care where exactly an area is allocated, but one exception is the persistent CBMEM console which relies (on a best effort basis) on always getting allocated at the same address on every boot. This is, technically, a hack, but it's a pretty harmless hack that has served us reasonably well so far and would be difficult to realize in a more robust way (without adding a lot of new infrastructure). Most of the time, coreboot will allocate the same CBMEM areas in the same order with the same sizes on every boot, and this all kinda works out (and since it's only a debug console, we don't need to be afraid of the odd one-in-a-million edge case breaking it). But one reproducible difference we can have between boots is the vboot boot mode (e.g. normal vs. recovery boot), and we had just kinda gotten lucky in the past that we didn't have differences in CBMEM allocations in different boot modes. With the recent addition of the RW_MCACHE (which does not get allocated in recovery mode), this is no longer true, and as a result CBMEM consoles can no longer persist between normal and recovery modes. The somewhat kludgy but simple solution is to just create a new class of specifically "early" CBMEM init hooks that will always run before all the others. While arbitrarily partitioning hooks into "early" and "not early" without any precise definition of what these things mean may seem a bit haphazard, I think it will be good enough in practice for the very few cases where this matters and beats building anything much more complicated (FWIW Linux has been doing something similar for years with device suspend/resume ordering). Since the current use case only relates to CBMEM allocation ordering and you can only really be "first" if you allocate in romstage, the "early" hook is only available in romstage for now (could be expanded later if we find a use case for it). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If2c849a89f07a87d448ec1edbad4ce404afb0746 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-27lib/hexdump: remove hexdump32 and use hexdump insteadFelix Held
hexdump and hexdump32 do similar things, but hexdump32 is mostly a reimplementation that has additional support to configure the console log level, but has a very unexpected len parameter that isn't in bytes, but in DWORDs. With the move to hexdump() the console log level for the hexdump is changed to BIOS_DEBUG. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6138d17f0ce8e4a14f22d132bf5c64d0c343b80d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54925 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27acpi: add SRAT Generic Initiator Affinity structureJonathan Zhang
Generic Initiator Affinity structure is introdcued in ACPI spec 6.3. This structure is used to define NUMA affinity domain which is established by generic initiator (such as by CXL device). Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic6ef01c59e02f30dc290f27e741027e16f5d8359 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2021-05-26soc/intel/elkhartlake: Update SA & IGD DIDs TableTan, Lean Sheng
Update SA & IGD DIDs table as per latest EDS (Doc no: 601458). Add extra SKUs and fix the mismatched SKU numbers accordingly. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I62fd9e6a7cf0fc6f541f3d6d9edd31d41db7279f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-05-26option: Decouple API from CMOS backendAngel Pons
Prepare to allow using other backends to store options. Change-Id: I3f838d27bf476207c6dc8f2c1f15c3fa9ae47d87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-26option.h: Correct `get_uint_option` return typeAngel Pons
Commit 88dcb3179b4b (src: Retype option API to use unsigned integers) changed the option API to use unsigned integers, but missed this. Change-Id: I5deb17157db41c40cc72078e2af9cf65bdbe0581 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-24device: Consider fw_config probing in `is_dev_enabled()`Furquan Shaikh
With the introduction of fw_config support in coreboot, it is possible for mainboards to control the state of a device (on/off) in ramstage using fw_config probe conditions. However, the device tree in immutable in all other stages and hence `is_dev_enabled()` does not really reflect the true state as in ramstage. This change adds a call to `fw_config_probe_dev()` in `is_dev_enabled()` when device tree is immutable (by checking DEVTREE_EARLY) to first check if device is disabled because of device probe conditions. If so, then it reports device as being disabled. Else, dev->enabled is used to report the device state. This allows early stages (bootblock, romstage) to use `is_dev_enabled()` to get the true state of the device by taking probe conditions into account and eliminates the need for each caller to perform their own separate probing. Change-Id: Ifede6775bda245cba199d3419aebd782dc690f2c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54752 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-24fw_config: Add helper function `fw_config_probe_dev`Furquan Shaikh
This change adds a helper function `fw_config_probe_dev()` that allows the caller to check if any of the probe conditions are true for any given device. If device has no probe conditions or a matching probe condition, then it returns true and provides the matching probe condition back to caller (if provided with a valid pointer). Else, it returns false. When fw_config support is disabled, this function always returns true. Change-Id: Ic2dae338e6fbd7755feb23ca86c50c42103f349b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54751 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21soc/intel/common: Add Alder Lake device IDsSumeet R Pawnikar
Add Alder Lake specific Host and Graphics device IDs. As per latest document number: 619501, these IDs got an update. Change-Id: I548a903714ccc7470f1425ac67c0c66522437365 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54674 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela
Updated CPU ID and IGD ID for Alder Lake as per EDS. TEST=Code compilation works and coreboot is able to boot and identify new device Ids. Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14src/acpi: Add initial support for HMATJonathan Zhang
Add initial HMAT (Heterogeneous Memory Attribute Table) support based on ACPI spec 6.4 section 5.2.27. Add functions to create HMAT table (revision 2) and create HMAT Memory Proximity Domain Attribute (MPDA) Structure. TESTED=Simulated HMAT table creation on OCP DeltaLake server, dumped the HMAT table and exmained the content. HMAT table and one MPDA structure are added. OCP Delatake server is based on Intel CooperLake Scalable Processor which does not support CXL (Compute Express Link). Therefore solution level testing is not done. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14acpi: Add acpigen_write_thermal_zoneRaul E Rangel
BUG=b:186166365 TEST=Compiles Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icf88477143049119036c00276f9a01985dc0b4d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-12include/console: Fix FSP Notify phase postcodes discrepancySubrata Banik
List of changes: 1. Make the FSP notify phases name prior in comments section. 2. Fix discrepancies in FSP notify before and after postcode comments. 3. Add FSP notify postcode macros for after pci enumeration(0xa2) and ready to boot(0xa3) call. Change-Id: Ib4c825d5f1f31f80ad2a03ff5d6006daa7104d23 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52894 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12include/console: Rename and update POST_ENTRY_RAMSTAGE postcodeSubrata Banik
Rename and update POST_ENTRY_RAMSTAGE postcode value from 0x80 to 0x6f to make the ramstage postcodes appear in an incremental order. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I60f4bd8b2e6b2b887dee7c4991a14ce5d644fdba Reviewed-on: https://review.coreboot.org/c/coreboot/+/52947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-12include/console: Fix duplicate entry of postcode 0x79Subrata Banik
Change POST_PRE_HARDWAREMAIN postcode value from 0x79 to 0x6e to avoid duplicate entry. Change-Id: I50cc75cd3097fba3e7faff05188511bba69ef1e7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-10*x86: fix x2apic mode boot issueWonkyu Kim
Fix booting issues on google/kahlee introduced by CB:51723. Update use inital apic id in smm_stub.S to support xapic mode error. Check more bits(LAPIC_BASE_MSR BIT10 and BIT11) for x2apic mode. TEST=Boot to OS and check apicid, debug log for CPUIDs cpuid_ebx(1), cpuid_ext(0xb, 0), cpuid_edx(0xb) etc Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ia28f60a077182c3753f6ba9fbdd141f951d39b37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-10device: Drop unused `uma_memory_{base,size}` globalsAngel Pons
These global variables are not used anywhere. Drop them. Change-Id: I3fe60b970153d913ae7b005257e2b53647d6f343 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53977 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10src: Drop "This file is part of the coreboot project" linesAngel Pons
Commit 6b5bc77c9b22c398262ff3f4dae3e14904c57366 (treewide: Remove "this file is part of" lines) removed most of them, but missed some files. Change-Id: Ib8e7ab26a74b52f86d91faeba77df3331531763f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-06drivers/pc80/rtc/option.c: Constrain API to integer valuesAngel Pons
None of the options accessed within coreboot is a string, and there are no guarantees that the code works as intended with them. Given that the current option API only supports integers for now, do not try to access options whose type is 's' (string). Change-Id: Ib67b126d972c6d55b77ea5ecfb862b4e9c766fe5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-06include/console: Align ramstage Boot State Machine postcodesSubrata Banik
This patch ensures all boot state machine postcodes are in right order. Move POST_ENTRY_RAMSTAGE macro definition after POST_BS_PAYLOAD_BOOT. Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52893 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak
With the recent switch to SMM module loader v2, the size of the SMM for module google/volteer increased to above 64K in size, and thus failed to install the permanent SMM handler. Turns out, the devicetree is all pulled into the SMM build because of elog, which calls `pci_dev_is_wake_source`, and is the only user of `struct device` in SMM. Changing this function to take a pci_devfn_t instead allows the linker to remove almost the entire devicetree from SMM (only usage left is when disabling HECI via SMM). BUG=b:186661594 TEST=Verify loaded program size of `smm.elf` for google/volteer is almost ~50% smaller. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-30mb/google: Move ECFW_RW setting for non-ChromeEC boardsKyösti Mälkki
The boolean is stored in ChromeOS NVS, not GNVS. Change-Id: I5c424a052d484228a456f8f0ad4fb0bed3165e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-30vc/google/chromeos: Refactor GNVS initKyösti Mälkki
Move the support code for filling ChromeOS GNVS from acpi/chromeos-gnvs.c to vc/google/chromeos/gnvs.c. Change-Id: I7e92206561812eb3dc69739df49b6c3a93853858 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50612 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30cpu/x86/msr: introduce helpers msr_read, msr_writeMichael Niewöhner
The existing helpers for reading/writing MSRs (rdmsr, wrmsr) require use of the struct `msr_t`, which splits the MSR value into two 32 bit parts. In many cases, where simple 32 bit or 64 bit values are written, this bloats the code by unnecessarly having to use that struct. Thus, introduce the helpers `msr_read` and `msr_write`, which take or return `uint64_t` values, so the code condenses to a single line or two, without having to deal with `msr_t`. Example 1: ~~~ msr_t msr = { .lo = read32((void *)(uintptr_t)0xfed30880), .hi = 0, }; msr.lo |= 1; wrmsr(0x123, msr); ~~~ becomes ~~~ uint32_t foo = read32((void *)(uintptr_t)0xfed30880); msr_write(0x123, foo | 1) ~~~ Example 2: ~~~ msr_t msr = rdmsr(0xff); uint64_t msr_val = (msr.hi << 32) | msr.lo; ~~~ becomes ~~~ uint64_t msr_val = msr_read(0xff); ~~~ Change-Id: I27333a4bdfe3c8cebfe49a16a4f1a066f558c4ce Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52548 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30src/acpi: Add APEI EINJ supportRocky Phagura
This adds full EINJ support with trigger action tables. The actual error injection functionality is HW specific. Therefore, HW specific code should call acpi_create_einj with an address where action table resides. The default params of the action table are filled out by the common code. Control is then returned back to the caller to modify or override default parameters. If no changes are needed, caller can simply add the acpi table. At runtime, FW is responsible for filling out the action table with the proper entries. The action table memory is shared between FW and OS. This memory should be marked as reserved in E820 table. Tested on Deltalake mainboard. Boot to OS, load the EINJ driver ( modprobe EINJ) and verify EINJ memory entries are in /proc/iomem. Further tested by injecting errors via the APEI file nodes. More information on error injection can be referenced in the latest ACPI spec. Change-Id: I29c6a861c564ec104f2c097f3e49b3e6d38b040e Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rocky Phagura
2021-04-28soc/intel: Add Z370, H310C and B365 device IDsAngel Pons
Intel document 335192-004 contains the PCI device IDs for Z370 and H310C, but lacks the ID for B365. The ID appears on some websites: https://linux-hardware.org/index.php?id=pci:8086-a2cc-1849-a2cc Change-Id: Iea3c435713c46854c5271fbc266f47ba4573db52 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52703 Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Add Kaby Lake PCH-U base device IDAngel Pons
Taken from Intel document 334658-003 (7th Generation Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel Processor Family I/O for U Quad Core Platforms, Datasheet - Volume 1 of 2). Change-Id: I1d48c8868e1e5d453d599ecec835938ce09935d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52702 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28soc/intel: Rename 200-series PCH device IDsAngel Pons
The code name for these PCHs is Union Point, abbreviated as `UPT`. There are some 300-series Union Point PCHs (H310C, B365, Z370) which are meant to be paired with Coffee Lake CPUs instead of Skylake or Kaby Lake CPUs, and referring to them as `KBP` (Kaby Point, I guess) would be confusing. Tested with BUILD_TIMELESS=1, HP 280 G2 remains identical. Change-Id: I1a49115ae7ac37e76ce8d440910fb59926f34fac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52700 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Timofey Komarov <happycorsair@yandex.ru> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23lib/espi_debug: Add espi_show_slave_peripheral_channel_configurationRaul E Rangel
Prints out the following: eSPI Slave Peripheral configuration: Peripheral Channel Maximum Read Request Size: 64 bytes Peripheral Channel Maximum Payload Size Selected: 64 bytes Peripheral Channel Maximum Payload Size Supported: 64 bytes Bus master: disabled Peripheral Channel: ready Peripheral Channel: enabled BUG=none TEST=boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7d598ee4f0f9d8ec0b37767e6a5a70288be2cb86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-23option.h: Drop type-unsafe {get,set}_option() APIAngel Pons
Change-Id: I5a9852b1fb66d609238ab7324f28a5e397c030ae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-22arch/x86/smbios: Let SMBIOS type 9 be able to write slot IDJingleHsuWiwynn
The slot ID can be passed in from the function caller but parsing slot ID from devicetree is not yet supported and would still be 0. Add Slot ID in SMBIOS type 9 for Delta Lake. Tested=Execute "dmidecode -t 9" to verify. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I9bf2e3b1232637a25ee595d08f8fbbc2283fcd5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 10:36:31 +0000