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2024-07-19device/pci_ids: Add new Intel PTL device IDs for CNViSubrata Banik
This patch adds new CNVi PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the CNVi driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused BT PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I7d80403b87537aea41ff48ff6d274180577f1ac6 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83520 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Remove unused Intel UFS device IDsSubrata Banik
This patch removes the PCI device IDs for Intel LNL and PTL UFS devices from `pci_ids.h` as they appear to be unused in the codebase. BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ic795dd2e83c361a2aa04267d4663cf6bb9a755e2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83519 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for XDCISubrata Banik
This patch adds new XDCI PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the XDCI driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused TCSS XDCI PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I51196401904e2402ac7669fa852a541bb7c2d453 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83518 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for CSE0Subrata Banik
This patch adds new CSE0 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the CSE0 driver's `pci_device_ids` list to include these new IDs. Finally, dropped unused CSE1-3 PCI IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5656aeb8c5439c8361aeb3a3d759df1216d84f8b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83517 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for AudioSubrata Banik
This patch adds new Audio (HDA/DSP) PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the Audio driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I3c9e420a6ae19d00fb5510c99d4c219dc43ad3c0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83516 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for SRAMSubrata Banik
This patch adds new SRAM PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SRAM driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ib6d62dad59965258dab453533dface9c359de586 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83515 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for P2SBxSubrata Banik
This patch adds new P2SBx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the P2SBx driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie1c36bc1c014bb1e219afe0cafb6c9941f253b0c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for XHCI/TCSS XHCISubrata Banik
This patch adds new XHCI/TCSS XHCI PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the XHCI driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5ae8f493374087a5e684e0a04486cd64cea6f335 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83513 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for SMBUSSubrata Banik
This patch adds new SMBUS PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SMBUS driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I4b8b59cf4e005f0e17a25d0fbe761404dab432b3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83512 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for Fast-SPI and GSPIxSubrata Banik
This patch adds new Fast-SPI and GSPIx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the SPI driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5c7c0be6f219c93d4520494857d31ce1cf939f36 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83511 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for UARTxSubrata Banik
This patch adds new UARTx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the UART driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I384a753f08ae5a752cef6009d07104e8ff4b4a6e Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for I2CxSubrata Banik
This patch adds new I2Cx PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the I2C driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I79ba0b563146d658521cdd40aabb3ee882f4d187 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83509 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for PMCSubrata Banik
This patch adds new PMC PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the PMC driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Iae468fdace2d9cfd532957e4f3c55b89b96a52a0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83508 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for PCIeSubrata Banik
This patch adds new PCIe Root Port PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the PCIe driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I5913c6ac0a4766c14f23954be1e885d45f69d36a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83507 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for eSPI/LPCSubrata Banik
This patch adds new eSPI/LPC PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the LPC driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie9f0ea9536e2f73c2258e9e12b510d21212248ea Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for ISHSubrata Banik
This patch adds new ISH PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the ISH driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I280cfdb50e8d453e957cb4bccff3a7ee2fb3bd10 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83505 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for DID2Subrata Banik
This patch adds new DID2 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the graphics driver's `pci_device_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Iab499070c87e020e36901b4ea453a1893bd16ea0 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83491 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-19device/pci_ids: Add new Intel PTL device IDs for DID0Subrata Banik
This patch adds new DID0 PCI device IDs for Intel PTL-U and PTL-H. Additionally, updates the System Agent driver's `systemagent_ids` list to include these new IDs. Source: Intel PTL-EDS vol 1. Document Number 815002, Rev 0.51 Chapter 2 BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie4d77eb489e16d18b996fdda3216e1275083d7e7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83490 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-15drivers/wifi: Support Radio Frequency Interference MitigationJeremy Compostella
The 'Radio Frequency Interference Mitigation' DSM function 11 provides the desired status of the RFI mitigation. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:352768410 TEST=ACPI DSM Function 11 reflects the value of the SAR binary Change-Id: I02808b0ce6a0a380845612e774e326c698ad1adc Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-07-15drivers/wifi: Support Energy Detection ThresholdJeremy Compostella
The 'Energy Detection Threshold' DSM function 10 provides the desired status of the EDT optimizations. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:352788465 TEST=ACPI DSM Function 10 reflects the value of the SAR binary Change-Id: I2e2e9d4f5420020bd7540cb36fa8aebfedf62285 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-07-10console: Fix I2C/SMBus console if it's the only slow oneNico Huber
Change-Id: Ie44fdac6904a4467e408882bb8a5e08e6ff73f32 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82761 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-07-10cbmem_top: Change the return value to uintptr_tElyes Haouas
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03drivers/wifi: Support 320Mhz Bandwidth Enablement per MCCPoornima Tom
Add support for the configuration of 320MHz Bandwidth per MCC based on countries. The implementation follows document #559910 Intel Connectivity Platforms BIOS Guidelines revision 8.3. BUG=b:333804562 BRANCH=firmware-rex-15709.B TEST=WBEM method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Ie76794825f1a0104d199c078aa4ffc714aa95b17 Signed-off-by: Poornima Tom <poornima.tom@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81790 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03drivers/wifi: Support Bluetooth Regulator Domain SettingsJeremy Compostella
The 'Bluetooth Increased Power Mode - SAR Limitation' feature provides ability to utilize increased device Transmit power capability for Bluetooth applications in coordination with Wi-Fi adhering to product SAR limit when Bluetooth and Wi-Fi run together. This commit introduces a `bluetooth_companion' field to the generic Wi-Fi drivers chip data. This field can be set in the board design device tree to supply the bluetooth device for which the BRDS function must be created. This feature is required for Meteor Lake rex karis variant. The implementation follows document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.3 specification. BUG=b:348345301 BRANCH=firmware-rex-15709.B TEST=BRDS method is added to the CNVW device and return the data supplied by the SAR binary blob Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e209 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83200 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-03tree: Use <console/console.h> only when usedElyes Haouas
Change-Id: I3cb1f11beba61afdf2be6188bde9ff135f8ace50 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-06-28acpi: Add support for DRHD size reportingShuo Liu
VT-d spec 4.0 supports size definition for DRHD BAR to support DRHD sizes larger than 4KB. If the value in the field is N, the size of the register set is 2^N 4 KB pages. Some latest OS (e.g. Linux kernel 6.5) will have VTd driver trying to use the beyond 4KB part of the DRHD BAR if they exist. They need the DRHD size field to set up page mapping before access those registers. Re-add acpi_create_dmar_drhd with a size parameter to support the needs. TEST=Build and boot on intel/archercity CRB Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c Signed-off-by: Shuo Liu <shuo.liu@intel.com> Signed-off-by: Gang Chen <gang.c.chen@intel.com> Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82429 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-27drivers/wifi: Support Wi-Fi 7 11be EnablementRavi Sarawadi
Add 802.11be (aka. Wi-Fi 7) enable/disable support based on document 559910 Intel Connectivity Platforms BIOS_Guidelines revision 8.3. There are countries where Wi-Fi 7 should be disabled by default. This adds capability for OEM to enable or disable by updating the board specific Specific Absorption Rate (SAR) binary. BUG=b:348345300 BRANCH=firmware-rex-15709.B TEST=SSDT dump shows that the _DSM method returns the value supplied by the SAR binary for function 12 Change-Id: Ifa1482d7511f48f5138d4c68566f07ce79f37a7a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2024-06-27lib/string: change return types to match C standardFelix Held
The return type of strspn and strcspn is supposed to be a size_t and not a signed integer. TEST=Now the openSIL code can be built with the coreboot headers without needing to add '-Wno-builtin-declaration-mismatch' or '-Wno-incompatible-library-redeclaration' to the cflags. Before the build would error out with various 'mismatch in return type of built-in function' errors. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0ff612e2eee4f556f5c572b02cbc600ca411ae20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83223 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-27lib/string: change parameter types to match C standardFelix Held
The third parameter of strncpy and strncmp is supposed to be a size_t and not a signed int. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I485e45e18232a0d1625d4d626f923ec66cfbe4a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83222 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-26acpi: Rename acpi_create_dmar_drhdShuo Liu
For most of SoCs, DRHD is by default with the size of 4KB. However, larger sizes are allowed as well. Rename acpi_create_dmar_drhd to acpi_create_dmar_drhd_4k to support the default case while a later patch will re-add acpi_create_dmar_drhd with a size parameter. TEST=intel/archercity CRB Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-25device/azalia: Separate codec checking and initializationNicholas Sudsgaard
This also changes how debug messages will be printed. I focused on reducing clutter on the screen and made the style of the messages consistent. Before: azalia_audio: Initializing codec #5 codec not ready. azalia_audio: Initializing codec #4 codec not valid. azalia_audio: Initializing codec #3 azalia_audio: viddid: ffffffff azalia_audio: verb_size: 4 azalia_audio: verb loaded. After: azalia_audio: codec #5 not ready azalia_audio: codec #4 not valid azalia_audio: initializing codec #3... azalia_audio: - vendor/device id: 0xffffffff azalia_audio: - verb size: 4 azalia_audio: - verb loaded Change-Id: I92b6d184abccdbe0e1bfce98a2c959a97a618a29 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80332 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-24acpigen_ps2_keybd: Support a Do Not Disturb keyAseda Aboagye
This commit simply adds support for a Do Not Disturb key. HUTRR94 added support for a new usage titled "System Do Not Disturb" which toggles a system-wide Do Not Disturb setting. BUG=b:342467600 TEST=Build and flash a board that generates a scancode for a Do Not Disturb key. Verify that KEY_DO_NOT_DISTURB is generated in the Linux kernel with patches[0] that add this new event code using `evtest`. [0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=22d6d060ac77955291deb43efc2f3f4f9632c6cb Change-Id: I26e719bbde5106305282fe43dd15833a3e48e41e Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82997 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Forest Mittelberg <bmbm@google.com>
2024-06-24acpigen_ps2_keybd: Support an Accessibility keyAseda Aboagye
Add support for an Accessibility key. HUTRR116 added support for a new usage titled "System Accessibility Binding" which toggles a system-wide bound accessibility UI or command. BUG=b:333095388 TEST=Build and flash a board that contains an accessibility key. Verify that KEY_ACCESSIBILITY is generated in the Linux kernel with patches[0] that add this new event code using `evtest`. ``` Testing ... (interrupt to exit) Event: time 1718924048.882841, -------------- SYN_REPORT ------------ Event: time 1718924054.062428, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9 Event: time 1718924054.062428, type 1 (EV_KEY), code 590 (?), value 1 Event: time 1718924054.062428, -------------- SYN_REPORT ------------ Event: time 1718924054.195904, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9 Event: time 1718924054.195904, type 1 (EV_KEY), code 590 (?), value 0 Event: time 1718924054.195904, -------------- SYN_REPORT ------------ ``` [0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=0c7dd00de018ff70b3452c424901816e26366a8a Change-Id: Ifc639b37e89ec251f55859331ab5c2f4b2b45a7d Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82996 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Forest Mittelberg <bmbm@google.com>
2024-06-22treewide: Move device_tree to commonlibMaximilian Brune
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I990d74d9fff06b17ec8a6ee962955e4b0df8b907 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77970 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-21include/input-event-codes.h: Update to latest HID treeAseda Aboagye
This commit simply updates the input-event-codes.h to the HID maintainers' tree at SHA c412e40267dd4ac020c5f8dc8c1cccc04e796ff4. Change-Id: Ic1fb9b18ced37866b84230929cd5c785d0dde9ba Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82993 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-06-11treewide: Move skip_atoi function to commonlibKapil Porwal
BUG=none TEST=Build and verify on Screebo TEST=make unit-tests ``` $ make tests/commonlib/bsd/string-test [==========] tests_commonlib_bsd_string-test(tests): Running 1 test(s). [ RUN ] test_skip_atoi [ OK ] test_skip_atoi [==========] tests_commonlib_bsd_string-test(tests): 1 test(s) run. [ PASSED ] 1 test(s). ``` Change-Id: Ifaaa80d0c696a625592ce301f9e3eefb2b4dcd98 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82910 Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-09sb/intel/lynxpoint/pcie.c: Add 9-series PCH-H device IDsAngel Pons
Looks like PCIe root port device IDs for 9-series PCH-H are missing from commit 434d7d45829e (sb/intel/lynxpoint: Add PCI DIDs for 9 series PCHs) for some reason. Add them, so that coreboot performs PCIe initialisation for 9-series PCH-H. Change-Id: I1589418e5e25daabbf09c66c637e9c4f86aa02a6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82947 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-06arch/io.h: Add port I/O functions to other architecturesAlper Nebi Yasak
The QEMU Bochs display driver and the QEMU Firmware Configuration interface code (in the qemu-i440fx mainboard dir) were written for x86. These devices are available in QEMU VMs of other architectures as well, so we want to port them to be independent from x86. The main problem is that the drivers use x86 port I/O functions to communicate with devices over PCI I/O space. These are currently not available for ARM* and RISC-V, although it is often still possible to access PCI I/O ports over MMIO through a translator. Add implementations of port I/O functions that work with PCI I/O space on these architectures as well, assuming there is such a translator at a known address configured at build-time. Change-Id: If7d9177283e8c692088ba8e30d6dfe52623c8cb9 Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80372 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-03device_tree: Add function to get top of memory from a FDT blobAlper Nebi Yasak
coreboot needs to figure out top of memory to place CBMEM data. On some non-x86 QEMU virtual machines, this is achieved by probing the RAM space to find where the VM starts discarding data since it's not backed by actual RAM. This behaviour seems to have changed on the QEMU side since then, VMs using the "virt" model have started raising exceptions/errors instead of silently discarding data (likely [1] for example) which has previously broken coreboot on these emulation boards. The qemu-aarch64 and qemu-riscv mainboards are intended for the "virt" models and had this issue, which were mostly fixed by using exception handlers in the RAM detection process [2][3]. But on 32-bit RISC-V we fail to initialize CBMEM if we have 2048 MiB or more of RAM, and on 64-bit RISC-V we had to limit probing to 16383 MiB because it can run into MMIO regions otherwise. The qemu-armv7 mainboard code is intended for the "vexpress-a9" model VM which doesn't appear to suffer from this issue. Still, the issue can be observed on the ARMv7 "virt" model via a port based on qemu-aarch64. QEMU docs for ARM and RISC-V "virt" models [4][5] recommend reading the device tree blob it provides for device information (incl. RAM size). Implement functions that parse the device tree blob to find described memory regions and calculate the top of memory in order to use it in mainboard code as an alternative to probing RAM space. ARM64 code initializes CBMEM in romstage where malloc isn't available, so take care to do parsing without unflattening the blob and make the code available in romstage as well. [1] https://lore.kernel.org/qemu-devel/1504626814-23124-1-git-send-email-peter.maydell@linaro.org/T/#u [2] https://review.coreboot.org/c/coreboot/+/34774 [3] https://review.coreboot.org/c/coreboot/+/36486 [4] https://qemu-project.gitlab.io/qemu/system/arm/virt.html [5] https://qemu-project.gitlab.io/qemu/system/riscv/virt.html Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80322 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-01tree: Add some SMBIOS_PROCESSOR_FAMILY macrosElyes Haouas
Change-Id: Ibe551a4c83f416ba30326077aa165818cf79c1fd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82648 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29cpu/x86/pae/pgtbl.c: extract reusable code from memset_pae()Krystian Hebel
Code dealing with PAE can be used outside of memset_pae(). This change extracts creation of identity mapped pagetables to init_pae_pagetables() and mapping of single 2 MiB map to pae_map_2M_page(). Both functions are exported in include/cpu/x86/pae.h to allow use outside of pgtbl.c. MEMSET_PAE_* macros were renamed to PAE_* since they no longer apply only to memset_pae(). Change-Id: I8aa80eb246ff0e77e1f51d71933d3d00ab75aaeb Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82249 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-29tree: Remove unused <string.h>Elyes Haouas
Change-Id: I9ed1a82fcd3fc29124ddc406592bd45dc84d4628 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-05-29tree: Use <stdio.h> for snprintfElyes Haouas
<stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-28tree: Add smbios_processor_typeElyes Haouas
Change-Id: I46f799ad255993ac42dab11b5c1d2608daa52b42 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82645 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-28include/device: Fix IO resource handling covering 0xFFFFShuo Liu
IO resource creation utils taking 'from' and 'to' as parameters use uint16_t for them, where 'to' equals the resource limit plus 1. When a resource is with a limit of 0xFFFF, the value of 'to' will be clipped to 0x0000 by uint16_t. Fix this problem by use uint32_t and checks the effective range to make sure it no larger than UINT16_MAX + 1. TEST=Build and boot on intel/archercity CRB TEST=Build on intel/avenuecity CRB Change-Id: Ie83045683094d6330c1676809f83acf30175cc90 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-28soc/intel/xeon_sp: Add domain resource window creation utilsShuo Liu
It might be benefical to have utils for domain resource window creation so that the correct IORESOURCE flags used could be guaranteed. TEST=Build and boot on intel/archercity CRB TEST=Build on intel/avenuecity CRB Change-Id: I1e90512a48ab002a1c1d5031585ddadaac63673e Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-05-28tree: Remove unused <stdarg.h>Elyes Haouas
<stdarg.h> header is used to define macros for handling variable argument lists in functions like printf. It does not depend on the string or memory manipulation functions provided by <string.h>. So let follow conventions and include only the necessary headers in each header file. Change-Id: I07ffc65b7feefb8ec4ab8dd268113f9ed8d24685 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82664 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-28spd_bin.h: Use same macro for DDR3 and LPDDR3Elyes Haouas
DDR3 and LPDDR3 share the same PART_NUM and PART_LEN. So use the same macro. This is to prepare SPD de-duplication in following patch. Change-Id: Iea824a847b5072b1cbaa38dc38deae1d484d5b16 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-25acpi: add and use defines for LAPIC feature flagsFelix Held
Both the processor local APIC structure and the processor local x2APIC structure use the same flag bit definitions. ACPI spec 6.4 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8101c2ea874c8b12b130dbe9a0a7e0f0d94adffa Reviewed-on: https://review.coreboot.org/c/coreboot/+/82641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-05-25acpi: introduce and use ACPI_MADT_PCAT_COMPAT defineFelix Held
The multiple APIC flags table from the ACPI specification version 6.4 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I36f67ca21465bc8753bb36896ee05669de6de333 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82640 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-25arch/arm64: Implement initial set of SMBIOS tablesBenjamin Doron
Implement the two architectural tables: processor and cache. Note that SoC/board code should override core-thread count and, for spec-compliance, create CBMEM_ID_MEMINFO. Change-Id: Iedae0f26f168bd6d3af866e35d9d39ddb01abc15 Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-05-23device: drop unnecessary CHECK_REV_IN_OPROM_NAME optionFelix Held
The CHECK_REV_IN_OPROM_NAME Kconfig option was introduced to solve the problem of the PCI VID/DID combination of the Picasso iGPU not being sufficient information to know which VGA BIOS file to run, so a new function that additionally checks the PCI revision of that device was introduced. Later it turned out that there might be a case where even that isn't sufficient, so the soc_is_raven2() function is used in the remap function to always use the correct VBIOS file. Picasso is the only SoC that selected the CHECK_REV_IN_OPROM_NAME Kconfig option, so all other SoCs are unaffected by this change. Now that we use the VBIOS images with only the PCI VID and DID in the CBFS file name for Picasso, SeaBIOS will find the VBIOS with the same ID as the iGPU in CBFS and we don't need the workaround to add a third VBIOS image via VGA_BIOS_DGPU_* that has the name that SeaBIOS expects. This will result in SeaBIOS now running the VBIOS that has the same PCI VID/DID as the hardware which will be the wrong one in the RV2 silicon showing the PCO silicon PCI VID/DID, but that was also the case with the VGA_BIOS_DGPU_* workaround where the board's Kconfig just selected one of the two possible images during build time and hoped that it was the correct one for that actual hardware. The only board where this patch might cause a regression compared to the old behavior is the AMD Cereme reference board with Pollock APU, but I'm not even sure if any coreboot developer still has one of those boards, so I'm willing to accept that. To properly solve the problem with SeaBIOS using the correct VBIOS file in all cases, we'd need to generate that info during coreboot runtime and somehow pass it to SeaBIOS, but that's out of scope for this patch. TEST=On Mandolin with PCO silicon, the display output in both SeaBIOS and Ubuntu still works. Booting Windows 10 via the pre-built EDK2 payload that I'm using also resulted in the display output working. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6de533c536044698d85404427719b8f534870fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/82598 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-21lib/device_tree: Add some FDT helper functionsMaximilian Brune
This adds some helper functions for FDT, since more and more mainboards seem to need FDT nowadays. For example our QEMU boards need it in order to know how much RAM is available. Also all RISC-V boards in our tree need FDT. This also adds some tests in order to test said functions. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81081 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-16include/device/pci_ids.h: Update TWL device IDsSaurabh Mishra
Set lowercase hex format for IGD DIDs. BUG=b:326901448 TEST=Build tivviks and verify the IGD IDs. Change-Id: I1299512d1c48eba854fea2ec394cef40d44a87d7 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82414 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-15cpu/x86/pae/pgtbl.c: remove dead paging_identity_map_addr()Krystian Hebel
This function had roughly the same use (except PAT) as part of memset_pae(), however the latter is able to make use of PAE and map physical memory located above 4 GB. Remove paging_identity_map_addr() to avoid semi-duplicated code. The function has been unused since CB:26745. Change-Id: I7a4ebd84a6f5d222c3b2c6c6e3d26d6464cf01b8 Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82248 Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14soc/intel/common: Add RPL tracehub supportAshish Kumar Mishra
Add PCI ID for RPL tracehub and update the PCI ID in the pci_device_ids[] in tracehub.c. Reference: Raptor Lake External Design Specification Volume 1 (640555) BUG=None TEST=Verified on brox Change-Id: I5d5c6c8ff44bcb5a7bbbd3e27a1577c169ecd6a9 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-05-14soc/intel: Add Panther Lake PCIE device IDsSaurabh Mishra
Add Panther Lake specific CPU and PCIE device IDs Reference: Panther Lake External Design Specification Volume 0.51 (815002) BUG=b:329787286 TEST=verified on Panther Lake Simics Platform. Change-Id: I82f47b6077e28a01f34c59b7e7697323b3d5f990 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81849 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-14soc/intel/common: Add Lunar Lake IAA and TBTRP3 device IDsSaurabh Mishra
Reference: Lunar Lake External Design Specification Volume 1 (734362) BUG=b:329787286 TEST=verified on Lunar Lake RVP board (lnlrvp). Change-Id: I92b65c946682387cbb841d558c6f0a7cb0fcd4ac Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81850 Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-13cpu/x86/pae/pgtbl.c: remove dead map_2M_page()Krystian Hebel
This function isn't used anywhere. It probably wouldn't work with current coreboot anyway, as it identity mapped lower 2GB of RAM, while ramstage is run from CBMEM, which is usually just below top of memory. It was last used in K8 code that is long gone. Change-Id: I97e2830f381181d7f21ab5f6d4c544066c15b08c Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
2024-05-12soc/intel/lunarlake: Support stepping A0_2Saurabh Mishra
Details: - Add support for new Lunar Lake MCH ID 0x6410 - Add new CPU id 0xb06d1 Reference: Lunar Lake External Design Specification Volume 1 (734362) TEST=Build, boot the system and verfiy MCH-ID prints in bootblock stage. Below prints verified on Lunar Lake RVP board (lnlrvp). [DEBUG] MCH: device id 6410 (rev 02) is LunarLake M Change-Id: I976d7f269485633d835d204afa224736d71baaa8 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81847 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-05-11include/efi: Override EFIAPI macro for x86_64Subrata Banik
This commit overrides the EFIAPI macro definition when using FSP on x86_64 to ensure the correct calling convention is used. On i386, there is no side-effect since the C calling convention used by coreboot and FSP are the same. However, on x86_64, FSP/UEFI uses the Microsoft x64 calling convention while coreboot uses the System V AMD64 ABI. This change resolves this incompatibility by setting EFIAPI to attribute((ms_abi)) on x86_64 when using FSP. TEST=Able to build google/rex0 in 32-bit and 64-bit mode. Change-Id: Ifae910be66d550af04cce5136d186a7e9dd085b3 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82266 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09include/spd.h: Add SPD_MEMORY_TYPE_LPDDR3_INTEL into spd_memory_typeElyes Haouas
Change-Id: I694af163fb530be49561e74e74d9c08e04986a44 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82223 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-09include/spd.h: Add new spd_memory_type valuesElyes Haouas
This adds LPDDR4X, DDR5,LPDDR5, DDR5_NVDIMM_P and LPDDR5X, according to revision of JESD400-5A.01, January 2023. Change-Id: I15802da03dc748c0e7f6b035fed25371afe3eed4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82217 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07dram/ddr3: Use the same naming convention as DDR4Elyes Haouas
Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07dram/ddr5: Use the same naming convention as DDR{2,3,4}Elyes Haouas
Change-Id: I2cc38926b56315d4a828311917ff58051b34b777 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07spd.h: Move enum ddr4_module_type to ddr4.hElyes Haouas
Move specific enum ddr4_module_type to <device/dram/ddr4.h>. Change-Id: Ia538d2c73affa6560fa1533a40c02b3677588f5a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07device/dram/ddr{3,4}: Rename spd_raw_data for specific DDRElyes Haouas
Rename different spd_raw_data[] for DDR3 and DDR4. This is to solve the conflict when we include both "ddr3.h" and ddr4.h" for example here: src/device/dram/spd.c. Otherwise, it won't compile as DDR3 and DDR4 have different spd_raw_data[] size. Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-05-07device/device_util: Add and use is_pci_bridge()Shuo Liu
TEST=Build and boot on intel/archercity CRB Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81566 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-05-07spd.h: Move enum ddr5_module_type to ddr5.hElyes Haouas
Move specific enum ddr5_module_type to <device/dram/ddr5.h>. Change-Id: Ie38d1e99fa46c278e60ced2d3eef29ca823d4b1d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
2024-05-06acpi: Remove acpigen_write_OSC_pci_domainShuo Liu
For PCI domains, static _OSC will be used for better readability and maintenance. This reverts commit f4a12e1d39a097e17007ef11ccf784c2a42f1924. TEST=Build and boot on intel/archercity CRB Change-Id: I2e2b2f0533a3940caf2806ec1ed048c30e4ba801 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82032 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-29include/device/pci_ids.h, soc/intel/mtl: add new MTL-P iGPU DIDMichał Kopeć
Found in a Clevo V560TU with Intel Core Ultra 155H Change-Id: I0f10808fd0e2d9c122743615fbce656c6d2447cc Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82071 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-23drivers/intel/fsp2_0: Support FSP 2.4 64-bitsJeremy Compostella
FSP 2.4 brings FSP 64-bits support which requires some adjustments in coreboot: FSP/UEFI uses the Microsoft x64 calling convention. Appropriate attribute has to be set to all functions calling or called by the FSP. BUG=b:329034258 TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec99 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2024-04-23soc/intel/alderlake: Add Twinlake graphics device IDsSowmya V
Add the graphics device IDs for Twinlake platform based on Platform External Design Specification. Document ID: 645548 BUG=b:326901448 TEST=Build tivviks and verify the IGD IDs. Change-Id: Ide008d5c5302bd589784bc917a2610c42a0fdee4 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82038 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-04-22drivers/intel/fsp2_0: Introduce fsp print helper macrosAppukuttan V K
This patch introduces fsp print helper macros to print `efi_return_status_t' with the appropriate format. These macros are now used for fsp debug prints with return status efi_return_status_t is defined as UINT64 or UNIT32 based on the selected architecture BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: If6342c4d40c76b702351070e424797c21138a4a9 Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81630 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-22acpigen_ps2_keybd: Add assistant key to linux,keymapAseda Aboagye
If the ChromiumOS EC indicates that the device has an assistant key, we should also add it to the generated linux,keymap binding. This commit simply does so by examining the keyboard capabilities reported by the EC. BUG=b:333088656 TEST=With a device that has an assistant key, flash AP FW and verify that the key is mapped to `KEY_ASSISTANT` in the Linux kernel using `evtest`. Change-Id: I217220e89bce88e3045a4fc3b124954696276442 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81996 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2024-04-19acpi: Make acpi_device_write_dsd_gpio() publicJianeng Ceng
Make sure it can be used for other driver. At present, i2c_generic_write_gpio() is not suitable for being called by other drivers, so delete it, add acpi_device_write_dsd_gpio() to replace it, and make it public. BUG=None TEST= Build BIOS FW pass and it can be use for other driver. Change-Id: Ifb2e60690711b39743afd455c6776c5ace863378 Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-04-18device/device_util: Rename dev_get_pci_domainShuo Liu
In coreboot, domain indicates hardware units that provide/group resource windows, For Xeon-SP, domains are PCIe compatible and further function in many aspects, e.g. PCIe, CXL, IOAT, UBOX. Rename dev_get_pci_domain to dev_get_domain to align with coreboot concept and distinguish from Xeon-SP concept. TEST=Build and boot on intel/archercity CRB Change-Id: I51b18b30fb41038869ea1384b01091da31a895b9 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-04-18device/device_util: Use const qualifierPatrick Rudolph
Allows to use the function in more places that expect the struct device to be readonly. TEST=Build and boot on intel/archercity CRB Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81275 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-15acpigen_ps2_keybd: Add support for dictation keyAseda Aboagye
Some internal keyboards have a dictation key; this commit simply adds support for this key by adding the mapping from the scancode to the Linux keycode for use in the linux,physmap ACPI table. BUG=b:333101631 TEST=Flash DUT that emits a scancode for a dictation key, verify that it is mapped to KEY_DICTATE in the Linux kernel. Change-Id: Iabc56662a9d6b29e84ab81ed93cb46d2e8372de9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-04-15include: Add 'IWYU pragma: export' commentElyes Haouas
This pragma says to IWYU (Include What You Use) that the current file is supposed to provide commented header. Change-Id: I3acb5e6b18443e454d8174b0b1f9d207c0fb78b5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12tree: Drop duplicated <device/{path,resource}.h>Elyes Haouas
<device/device.h> is supposed to provide <device/{path,resource}.h> Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-12include/device/device.h: Drop duplicated <console/console.h>Elyes Haouas
Change-Id: Ib81c81843a5252e2ead9ce175cea2fa42f0e8152 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2024-04-06lib: Refactor bmp_load_logo() implementationSubrata Banik
This refactoring ensures bmp_load_logo() takes logo_size as an argument, returning a valid logo_ptr only if logo_size is non-zero. This prevents potential errors from mismatched size assumption. BUG=b:242829490 TEST=google/rex0 builds successfully. Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81618 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-04-05smmstorev2: Load the communication buffer at SMM setupArthur Heymans
This removes the runtime SMI call to set up the communication buffer for SMMSTORE in favor of setting this buffer up during the installation of the smihandler. The reason is that it's less code in the handler and a time costly SMI is also avoided in ramstage. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I94dce77711f37f87033530f5ae48cb850a39341b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-04-04include/efi: Introduce __efiapi for EFI calling convention flexibilitySubrata Banik
This patch defines __efiapi (based on EFIAPI) for coreboot-compliant EFI calls. This lays the groundwork for future 64-bit EFI calling convention support within coreboot/FSP. BUG=b:242829490 TEST=FSP debug log accessible via coreboot event handler. Change-Id: I21660f8ebeed3b9ef060118928a940a470492bb8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81620 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-04-03cpu/x86/topology: Add node ID parserPatrick Rudolph
Currently the SRAT table only exposes one proximity group as it uses the LAPIC node_id, which is always initialized to 0. Use CPUID leaf 0x1f or 0xb to gather the node ID and fill it to make sure that at least one proximity group for every socket is advertised. For now the SNC config isn't taken into account. Change-Id: Ia3ed1e5923aa18ca7619b32cde491fdb4da0fa0d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-04-02include/device/pci_ids.h: Add DIDs for MTL Touch controllerCliff Huang
When touch controller is configured as THC-SPI mode, DID is 0x7e49 for THC0, and 0x7e4b for THC1. 0x7e48 and 0x7ea4 are the DIDs when ThcMode is 0 (default) for THC0 and THC1 respectively. Refer MTL EDS vol 1: 640228. BUG=b:307775082 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I1b98fdbd8d8588492bcafa0f3998818dc83ff1d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81330 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
2024-04-01acpi: Add acpigen_write_OSC_pci_domainShuo Liu
Add dynamic PCI domain _OSC ASL generation codes, supporting both PCIe and CXL domains. Dynamic SSDT generation is used to generate a list of ASL device objects based on FSP outputs (e.g. the SoC/SKU configurations) and _OSC is a method inside these objects (hence it would be straightforward to be generated altogether, plus some C codes managed boot configs could be referenced as well). This usage is optional. It is helpful for cases where the same code set supports multiple SKUs/SoCs (difficult to be handled by one set of static SSDT), and the CPU performance is good enough to run SSDT generation logics with minimal costs. TEST=intel/archercity CRB Tested with https://review.coreboot.org/c/coreboot/+/81377. Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-03-18symbols: Add __maybe_unused flag to region variable symbolsShuo Liu
In DECLARE_REGION and DECLARE_OPTIONAL_REGION, a set of 3 variables will be defined, that is the region 'base', 'end' and 'size'. However, in many codes, the users will only selectively use 'end' or 'size' instead of both of them, which will trigger compiler errors for unused variables. This patch sets __maybe_unused attributes on 'end' and 'size' so that users do not need to use all of them. TEST=intel/archercity CRB Change-Id: Ia5ed183b2dd7a474ce51de47dbc1f9e3f61e5a41 Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81209 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-15treewide: Move stdlib.h to commonlibMaximilian Brune
This patch moves commonlib/stdlib.h -> commonlib/bsd/stdlib.h, since all code is BSD licensed anyway. It also moves some code from libpayloads stdlib.h to commonlib/bsd/stdlib.h so that it can be shared with coreboot. This is useful for a subsequent commit that adds devicetree.c into commonlib. Also we don't support DMA on arm platforms in coreboot (only libpayload) therefore `dma_malloc()` has been removed and `dma_coherent()` has been moved to architecture specific functions. Any architecture that tries to use `dma_coherent()` now will get a compile time error. In order to not break current platforms like mb/google/herobrine which make use of the commonlib/storage/sdhci.c controller which in turn uses `dma_coherent` a stub has been added to arch/arm64/dma.c. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I3a7ab0d1ddcc7ce9af121a61b4d4eafc9e563a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-03-09soc/intel/alderlake: Add Raptor Lake System Agent Device IDsLean Sheng Tan
Add System Agent IDs for Raptor Lake SKUs based on RPL Datasheet (Doc ID: 743844) & EDS Vol 1 (Doc ID: 640555). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/81115 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-05soc/intel: Add definition of D0 stepping for TigerLake HaloAlicja Michalska
Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29soc/amd: move common pci_domain_fill_ssdt implementation to acpi/Felix Held
Even though it has an 'amd_' prefix, the amd_pci_domain_fill_ssdt implementation doesn't contain any AMD-specific code and can also be used by other SoCs. So factor it out, move the implementation to src/acpi/acpigen_pci_root_resource_producer.c, and rename it to pci_domain_fill_ssdt. When a SoC now assigns pci_domain_fill_ssdt to its domain operation's acpi_fill_ssdt function pointer, the PCI domain resource producer information will be added to the SSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80464 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-29include/device/azalia_device.h: Merge location1 and location2Nicholas Sudsgaard
This changes the location to be expressed as a combination of ORs. This allows aliases for special locations. For example, `AZALIA_REAR_PANEL` is easier to read than `AZALIA_EXTERNAL_PRIMARY_CHASSIS, AZALIA_SPECIAL7`. References: - Intel High Definition Audio Specification, rev. 1.0a, page 180, Table 110. Location. Change-Id: I5a61a37ed70027700f07f1532c500f04d7a16ce1 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29include/device: Merge enums from azalia_device.h and azalia.hNicholas Sudsgaard
We were keeping 2 copies of the same thing (albeit there were some slight differences). As azalia_device.h is used much more in the codebase this was kept as the base and then some of the nice features of azalia.h were incorporated. The significant changes are: - All enum names now use the `AZALIA_` prefix. This also drops the AzaliaPinConfiguration enum as it was never used since added in 2013. Change-Id: Ie874b083a18963679981a9cd2b25d123890d628e Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80695 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2024-02-29include/device/azalia_device.h: Correct location2 shift to 28 bitsNicholas Sudsgaard
The location is specified to be in range of 29:24, which is further divided into upper bits (location2) [5:4] and lower bits (location1) [3:0]. This also corrects the resulting values of clevo/l140mu. References: - Intel High Definition Audio Specification, rev. 1.0a, page 178, Figure 74. Configuration Data Structure. TEST=Timeless build using AZALIA_PIN_DESC() and without now produce the same binary. Change-Id: Ia5a3431b70783cb88e866d0fd8ea5530100f3d52 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80727 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-28cpu/x86/(sipi|smm): Pass on CR3 from ramstageArthur Heymans
To allow for more flexibility like generating page tables at runtime or page tables that are part of the ramstage, add a parameter to sipi_vector.S and smm_stub.S so that APs use the same page tables as the BSP during their initialization. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80335 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-02-26lib: Remove heap from rmodulesArthur Heymans
No rmodule was using heap. Change-Id: I0bc049a5231dabbec1c962a99ef875eddcc4ac6e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-02-24treewide: Move list.h to commonlibMaximilian Brune
It is needed in order to move device_tree.c into commonlib in a subsequent commit. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I16eb7b743fb1d36301f0eda563a62364e7a9cfec Reviewed-on: https://review.coreboot.org/c/coreboot/+/77968 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-20soc/intel/xeon_sp: Use ACPI common flags in SRAT generationShuo Liu
Move the definition of SRAT memory flags (SRAT_ACPI_MEMORY_ENABLED and SRAT_ACPI_MEMORY_NONVOLATILE) from FSP header to ACPI common codes. TEST=intel/archercity CRB Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: I6aa5c20c9556fd5d680406518d19a83801b0852c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 21:54:54 +0000