Age | Commit message (Expand) | Author |
2023-09-12 | arch/x86: Reduce max phys address size for Intel TME capable SoCs | Jeremy Compostella |
2023-08-05 | src/*/post_code.h: Change post code prefix to POSTCODE | Yuchen He |
2023-07-12 | treewide: Drop the suffixes from ADL and RPL CPUID macros and strings | Michał Żygowski |
2023-07-12 | soc/intel/alderlake: Add support for Raptor Lake S CPUs | Max Fritz |
2023-06-29 | soc/intel/meteorlake: Add QS(C0) stepping CPU ID | Musse Abdullahi |
2023-05-26 | treewide: Remove 'extern' from functions declaration | Elyes Haouas |
2023-04-15 | soc/intel/meteorlake: Add B0 stepping CPU ID | Musse Abdullahi |
2023-03-24 | cpu/intel: Remove redefined SAPPHIRERAPIDS_SP CPUID to fix build error | Johnny Lin |
2023-03-23 | soc/intel/xeon_sp: Report platform cpu info | Naresh Solanki |
2023-03-19 | soc/intel/xeon_sp/spr: Add header files and romstage code | Jonathan Zhang |
2023-02-07 | src: Move POST_BOOTBLOCK_CAR to common postcodes and use it | Martin Roth |
2023-01-19 | tree: Drop Intel Ice Lake support | Felix Singer |
2022-12-05 | cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm | Arthur Heymans |
2022-11-23 | cpu/intel/car: Define post codes | Martin Roth |
2022-11-17 | mb/emulation/qemu-q35: Split smm_close() and smm_lock() | Kyösti Mälkki |
2022-11-09 | cpu/*: Drop PARALLEL_MP leftovers | Arthur Heymans |
2022-09-16 | soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU ID | Jeremy Soller |
2022-08-01 | include: Add SPDX-License-Identifiers to files missing them | Martin Roth |
2022-06-28 | soc/intel: Add Raptor Lake device IDs | zhixingma |
2022-06-22 | cpu/intel/microcode: Have API to re-load microcode patch | Subrata Banik |
2022-06-17 | soc/intel/alderlake/report_platform.c: Add ADL-S identification | Michał Żygowski |
2022-06-01 | mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG | Arthur Heymans |
2022-05-16 | soc/intel: Add Raptor Lake device IDs | Bora Guvendik |
2022-04-04 | soc/intel/alderlake: Add new CPU ID | Lean Sheng Tan |
2022-04-04 | soc/intel/alderlake: Update CPU IDs with correct steppings | Lean Sheng Tan |
2022-03-09 | soc/intel/common: Include Meteor Lake device IDs | Wonkyu Kim |
2021-11-29 | soc/intel/common: Include Alder Lake-N device IDs | Usha P |
2021-09-30 | soc/intel/alderlake: Add CPU ID 0x906a4 | Meera Ravindranath |
2021-08-24 | soc/intel: Add TGL-H CPUID | Jeremy Soller |
2021-07-17 | cpu/intel: Add dedicated file to grow Intel CPUIDs | Subrata Banik |
2021-06-22 | soc/intel/car: Add support for bootguard CAR | Arthur Heymans |
2021-06-21 | soc/intel/common: Add InSMM.STS support | Angel Pons |
2021-06-15 | cpu/intel/msr.h: Sort MSRs in ascending order | Angel Pons |
2021-06-15 | cpu/intel/msr.h: Add license header | Angel Pons |
2021-05-28 | cpu/x86/entry16.S: Make Intel CBnT TOCTOU safe | Arthur Heymans |
2021-03-12 | cpu/intel/microcode: Fix caching logic in intel_microcode_find | Furquan Shaikh |
2021-02-11 | cpu/intel/microcode: Fix typo in function parameter | Elyes HAOUAS |
2021-01-28 | cpu/intel/microcode: Add caching layer in intel_microcode_find | Patrick Rudolph |
2021-01-07 | cpu/intel: add PC10 residency counter MSR | Michael Niewöhner |
2020-10-31 | cpu/intel/common: correct MSR for the Nominal Performance in CPPC | Michael Niewöhner |
2020-10-24 | cpu/intel/common: rework code previously moved to common cpu code | Michael Niewöhner |
2020-10-24 | {cpu,soc}/intel: deduplicate cpu code | Michael Niewöhner |
2020-10-21 | {cpu,soc}/intel: replace AES-NI locking by common implemenation call | Michael Niewöhner |
2020-10-19 | cpu/intel/common: rework AES-NI locking | Michael Niewöhner |
2020-10-19 | soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code | Michael Niewöhner |
2020-09-14 | src/include: Drop unneeded empty lines | Elyes HAOUAS |
2020-07-26 | src/include: Add missing includes | Elyes HAOUAS |
2020-06-16 | sb,soc/intel: Replace smm_southbridge_enable_smi() | Kyösti Mälkki |
2020-06-16 | soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS) | Kyösti Mälkki |
2020-05-11 | treewide: Remove "this file is part of" lines | Patrick Georgi |
2020-05-06 | treewide: replace GPLv2 long form headers with SPDX header | Patrick Georgi |
2020-05-06 | treewide: Move "is part of the coreboot project" line in its own comment | Patrick Georgi |
2020-04-05 | src/include: Use SPDX for GPL-2.0-only files | Angel Pons |
2020-03-17 | src (minus soc and mainboard): Remove copyright notices | Patrick Georgi |
2020-03-15 | treewide: Replace uses of "Nehalem" | Angel Pons |
2019-11-22 | cpu/intel/smm: Drop em64t save state | Arthur Heymans |
2019-11-22 | intel/smm: Provide common smm_relocation_params | Kyösti Mälkki |
2019-11-04 | cpu/intel/em64t101: Add Nehalem to compatibility list | Arthur Heymans |
2019-10-01 | cpu/intel/common: Move intel_ht_sibling() to common folder | Patrick Rudolph |
2019-09-19 | cpu/x86/lapic: Refactor timer_fsb() | Kyösti Mälkki |
2019-08-28 | intel/smm/gen1: Use smm_subregion() | Kyösti Mälkki |
2019-08-26 | soc/intel: Use common romstage code | Kyösti Mälkki |
2019-08-22 | arch/x86: Add <arch/romstage.h> | Kyösti Mälkki |
2019-08-18 | cpu/intel: Enter romstage without BIST | Kyösti Mälkki |
2019-08-15 | intel/smm: Define struct ied_header just once | Kyösti Mälkki |
2019-08-15 | soc/intel: Rename some SMM support functions | Kyösti Mälkki |
2019-08-15 | intel/smm/gen1: Rename header file | Kyösti Mälkki |
2019-08-15 | cpu/intel: Refactor platform_enter_postcar() | Kyösti Mälkki |
2019-08-13 | cpu/x86: Separate save_state struct headers | Kyösti Mälkki |
2019-01-27 | src/cpu/intel: Set get_ia32_fsb function common | Elyes HAOUAS |
2019-01-08 | cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK | Kyösti Mälkki |
2018-12-30 | cpu/intel/car: Drop remains of setup_stack_and_mtrrs() | Kyösti Mälkki |
2018-12-28 | soc/intel: Drop romstage_after_car() | Kyösti Mälkki |
2018-12-18 | Fix typos involving "the the" | Jonathan Neuschäfer |
2018-10-22 | intel: Use CF9 reset (part 2) | Patrick Rudolph |
2018-10-11 | src: Move common IA-32 MSRs to <cpu/x86/msr.h> | Elyes HAOUAS |
2018-10-05 | src: Fix MSR_PKG_CST_CONFIG_CONTROL register name | Elyes HAOUAS |
2018-07-30 | cpu/intel/microcode: Add helper functions to get microcode info | Rizwan Qureshi |
2018-06-02 | cpu/intel/car: Prepare for some POSTCAR_STAGE support | Kyösti Mälkki |
2017-12-11 | intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c | Elyes HAOUAS |
2017-11-30 | intel: Replace msr(0x198) with msr(IA32_PERF_STATUS) | Elyes HAOUAS |
2017-09-08 | soc/intel/common/block: Common ACPI | Shaunak Saha |
2017-05-16 | cpu/intel/turbo: Add option to disable turbo | Subrata Banik |
2017-03-13 | src/include: Wrap lines at 80 columns | Lee Leahy |
2017-03-13 | src/include: Move storage class to beginning of declaration | Lee Leahy |
2017-03-13 | src/include: Fix space between type, * and variable name | Lee Leahy |
2016-11-11 | intel post-car: Separate files for setup_stack_and_mtrrs() | Kyösti Mälkki |
2016-11-09 | cpu/intel: Add MSR to support enabling turbo frequency | Shaunak Saha |
2016-11-02 | soc/intel/apollolake: Disable Monitor and Mwait feature | Venkateswarlu Vinjamuri |
2016-06-22 | intel: Drop old romstage main() without asmlinkage | Kyösti Mälkki |
2016-06-18 | intel: Fix romstage main() with asmlinkage | Kyösti Mälkki |
2016-02-10 | cpu/intel/microcode: allow microcode to be loaded in romstage | Aaron Durbin |
2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
2015-07-29 | Add SoC specific microcode update check in ramstage | Rizwan Qureshi |
2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
2015-02-16 | acpi: Generate valid ACPI processor objects | Timothy Pearson |
2014-08-15 | intel/cpu: rename car.h to romstage.h | Aaron Durbin |
2014-08-14 | Intel: Add common header file for CAR setup | Edward O'Callaghan |
2014-01-16 | cpu/intel: Make all Intel CPUs load microcode from CBFS | Alexandru Gagniuc |
2013-12-13 | cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS | Alexandru Gagniuc |