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Change-Id: Iadc813bc8208278996b2b1aa20cfb156ec06fac9
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3755
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1]
made romcc not choke on function prototypes anymore. This
allows us to get rid of a lot of ifdefs guarding __ROMCC__ .
[1] http://review.coreboot.org/2424
Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3216
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
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http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html
It's about time we follow this advice.
Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and
drop unused CPP define
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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the v3 way.
This resolves problems with terminated DRAM modules.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Roland G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* integrate vsm init into normal x86.c code (so it can run above 1M)
* call void main(unsigned long bist) except void cache_as_ram_main(void)
on Geode LX (as we do on almost all other platforms now)
* Unify Geode LX MSR setup (will bring most non-working LX targets back
to life)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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code is changed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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The following original authors agreed to the license:
- Ronald G. Minnich <rminnich@gmail.com>
- Indrek Kruusa <indrek.kruusa@artecdesign.ee>
- Stefan Reinauer <stepan@coresystems.de>
- Andrei Birjukov <andrei.birjukov@artecdesign.ee>
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Signed-off-by: Indrek Kruusa
Approved-by: Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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* src/cpu/amd/model_lx/model_lx_init.c
L2 cache initialization removed (moved to northbridge.c)
* src/include/cpu/amd/lxdef.h
more checked values
* src/northbridge/amd/lx/northbridge.c
L2 cache initialization added
cpubug() commented out
* src/northbridge/amd/lx/raminit.c
empty function sdram_set_registers() is in use, don't remove
* src/mainboard/artecgroup/dbe61/Config.lb
irqmap changes
* src/mainboard/artecgroup/dbe61/irq_tables.c
tentative changes to irq table (currently not in use)
* src/mainboard/artecgroup/dbe61/mainboard.c
irq assigned manually to NIC
* src/mainboard/artecgroup/dbe61/Options.lb
gcc 4.0 is OK
* targets/artecgroup/dbe61/Config.lb
64K for VSA is OK at moment
Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
Signed-off-by: Andrei Birjukov <andrei.birjukov@artecdesign.ee>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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for L2 cache and fixes wrong P2D defines.
This also patch adds L2 cache initialization for Geode LX CPU.
Signed-off-by: Indrek Kruusa <indrek.kruusa@artecdesign.ee>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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There is one global change to pci_ids.h. The rest are changes for LX. I
ran abuild and it is ok. Not all artec design changes are included as
some of them would adversely affect other mainboards. Indrek will need
to test.
Signed-off-by: Ron Minnich
Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec
design.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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