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2021-01-24ec/google/wilco: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ie5c88f8acee16ff77f9707d7ed56436bf0d521b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-06-17ec/google/wilco: Suppress UCSI events in S0ixDuncan Laurie
If a UCSI event comes in when the EC is in S0ix mode then the kernel driver attempts a transaction but fails and this can leave the system in an unexpected state where the only wake source is the power button. This change will not notify the UCSI driver if the EC is in S0ix mode and instead keep track of the event and send it on resume. BUG=b:157923800 TEST=tested on drallion system: 1. Put drallion system into suspend 2. Attach power supply 3. Ensure the system can wake with keypress Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I43acb089385d9b41ac955f053e409daad67423f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-06ec/google/wilco: Always use current value of battery status bitMathew King
According to the Wilco EC spec the BTSC bit of PWSR is always cleared when PWSR is read so that battery status change events are only triggered one time. Testing of the Wilco EC has verified this behavior. This changes the way in which the battery status change bit is used from checking the bit state against the previous value to always issuing a battery event when the BTSC bit is set. The other bits in PWSR indicate state directly and do not behave like the BTSC bit. BUG=b:157113138 TEST=Deploy on Drallion and verify that battery events are generated BRANCH=drallion, sarien Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I8fbf2ee1158ddd790b04a20b1eb27a6cce4f5c81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05src/ec: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I422d072a9ab3350e364004ba34911cd183fc6612 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15ec/google/wilco: Store LID status into LIDS and change device nameEric Lai
Store LID status into LIDS and change device name to LID0. Then Intel driver can reference it. BUG=b:151134069 TEST=check LID status by evtest Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifdac938730eac034b626aa8ad9d52462f65137ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/39497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-12-17src: Conditionally include TEVTFrans Hendriks
ACPI method TEVT is reported as unused by iASL (20190509) when ChromeEC support is not enabled. The message is “Method Argument is never used (Arg0)” on Method (TEVT, 1, NotSerialized), which indicates the TEVT method is empty. The solution is to only enable the TEVT code in mainboard or SoC when an EC is used that uses this event. The TEVT code in the EC is only enabled if the mainboard or SoC code implements TEVT. The TEVT method will be removed from the ASL code when the EC does not support TEVT. BUG=N/A TEST=Tested on facebook monolith. Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-02ec/google/wilco: Add EC ACPI methods for privacy screenMathew King
Add ACPI methods to the Wilco EC for controlling a privacy screen on the device. BUG=b:142237145, b:142656363 TEST=none Change-Id: Ic3c136f9d2de90eeb3c9e468e4c7430ccf6dcc42 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36044 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25ec/{compal,google,quanta}: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Change-Id: If3ee38f3eaa8e6d1c1b0393d0ba289f708e0ae5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36293 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-24(acpi) superio.asl: Drop wrong _ADR objectsElyes HAOUAS
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Found-by: ACPICA 20191018 Change-Id: Ic0bcaa37ac017ab61e1fb4e78d3c7dfbbcc0899d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-06-13ec/google/wilco: Read back from EC RAM after S0ix entryDuncan Laurie
We are seeing an EC interrupt after setting the EC RAM offset that indicates that the EC should transition to S0ix mode and this is preventing the kernel from going into S0ix on the first try. As a workaround if we read back from the EC RAM while still in the _DSM handler it seems to prevent this problem. BUG=b:130644677 BRANCH=sarien TEST=ensure s0ix entry works on the first try with sarien Change-Id: Id607c4c2b14b79d0cd1bcea0c2032be2f2c0c141 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33455 Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-07ec/google/wilco: Add UCSI supportDuncan Laurie
This change adds support for the UCSI specification in order to provide information about the Type-C port and an interface to perform power and data role swap. This change is split across the DSDT and SSDT, with the shared memory and operation region declared in the SSDT after being allocated in CBMEM. The OS will fill in the registers in the system memory region and then call the _DSM method wtih a read or write argument. The DSM method will copy the required registers to/from the system memory and the EC and perform the write or read action. Responses from the EC will generate a new SCI with event code 0x79 which will notify this UCSI ACPI device and the OS driver will take action to read status from the EC. BUG=b:131083691 Change-Id: I438a2bdfaf6720acd8354e0339dcef2844b63a4e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-28ec/google/wilco: Add ACPI _BIX method for batteryDuncan Laurie
I added a method to fill out the _BIX package structure but never hooked it up to the expected _BIX method that the OS uses. This change adds _BIX method and uses the existing method to fill it out. It also adds ^ before the _UID in _BIF to match _BIX as the _UID is one level above the method. Change-Id: I0de91369b6780fd9432990732c1078a73f6a3419 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-21ec/google/wilco: Add function to indicate if EC uses signed FWDuncan Laurie
This will be used to distinguish the mainboard SKU so that the correct EC firmware can be bundled with the board. This is read from EC RAM so it can be used by an ACPI method in the future. BUG=b:119490232 Change-Id: I71b8017fc4b88e793dfe709e1cb1ab0f0bcdc4fa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-15ec/google/wilco: coalesce tent mode to tablet modeJett Rink
Both tent mode (0x01) and tablet mode (0x02) should be considered tablet mode by ChromeOS. BRANCH=none BUG=b:122052438 TEST=ChromeOS enters tablet mode when lid angle exceeds 180 Change-Id: I89ba8141350fc628c8cff89d5f33aa47c6ae6afe Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-25ec/google/wilco: Fix ACPI power status eventsDuncan Laurie
This change fixes the power status events for AC and battery events from the EC. The register that was being used is not returning the expected information. BUG=b:125472740 TEST=enable ACPI debug in the kernel and verify that AC and battery insert/remove are detected properly. Change-Id: I15f71fcf0ca6aa9438e951865787c9fc273792d8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05ec/google/wilco: Add virtual button supportDuncan Laurie
Add an ACPI device that is compatible with the Intel Virtual Button kernel driver for reporting tablet mode state and various virtual button events that may come from the EC. This driver is used in Windows and in the Linux kernel at drivers/platform/x86/intel-vbtn.c Because of a check in the kernel driver it expects the board to define the SMBIOS enclosure type as convertible for the check at driver load time for tablet/laptop and dock/undock to work. The virtual tablet mode button will proxy the tablet mode state sent from the Sensor Hub to a SW_TABLET_MODE event in the kernel. The virtual power button is used during S0ix for the EC to wake the system with an SCI. There are separate press and release events which are sent for completeness, although the kernel driver will ignore the release event. BUG=b:73137291 TEST=Test that the power button can wake the system from S0ix. Also verify that the device is reported as laptop mode at boot. Change-Id: I0d5dc985a3cfb1d01ff164c4e67f17e6b1cdd619 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31208 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-04ec/google/wilco: Add ACPI device for event interfaceDuncan Laurie
Add a separate ACPI device for the Wilco EC event interface so that the OS drivers can bind to it separately. Since the event handling is all done with ACPI and not mailbox calls this will be implemented as a standard acpi_driver in the kernel. BUG=b:119046283 TEST=veriy device exists in DSDT Change-Id: I5259a926fb6d5faea835bcdefa12f0184c5adf4a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-04ec/google/wilco: Add S0ix support handlersDuncan Laurie
1) In the EC _REG method set the flag indicating S0ix support in the OS. 2) Add a function that can be called by the LPI _DSM method to indicate to the EC that the OS is entering or exiting S0ix. BUG=b:73137291 Change-Id: Iddc33a08542a6657694c47a9fda1b02dd39d89f7 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31094 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04ec/google/wilco: Guard DTPF with ifdefDuncan Laurie
There is a dependency issue with the EC DPTF code accessing methods that are external, but once the mainboard includes the relevant code they become internal and the current version of IASL used by jenkins will fail to compile it. Until the new IASL is deployed everywhere wrap the EC DPTF code and expect that the mainboard will explicitly enable it. Change-Id: I612ad8f86d424060ca0303d267d7c2915c760173 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04ec/google/wilco/acpi: Add DPTF supportDuncan Laurie
Add the support needed for DPTF. This includes the methods to write trip point values, read temperatures, and handle events. This was tested on a sarien board by inspecting AML debug output with the kernel while monitoring temperatures and trip points in sysfs and controlling temperatures with a fan to ensure that when a trip point is crossed an SCI is generated and the event is handled properly. Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29761 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04ec/google/wilco/acpi: Fix issues and clean upDuncan Laurie
- Disable debug output from read/write methods by default - Use argument to _REG to disable SCI when EC is unregistered - Change read/write macros to sync level 2 so they can be called when a mutex is already held - Define some missing events Change-Id: Ic65ebbb6a6151444c47b4aeff7429e186856c49a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29760 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04ec/google/wilco: Fix extended event handlingDuncan Laurie
Extended events will be handled by the OS kernel driver, but that driver needs a method exposed by ACPI to read the event data from the EC and into a buffer. Tested by generating a hotkey event and reading the buffer from the Linux kernel driver with acpi_evaluate_object(). Change-Id: Ic8510e38d777a5dd31a5237867313efefeb2b48e Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29674 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04ec/google/wilco: Enable COM1 ACPI deviceDuncan Laurie
Enable the COM1 ACPI device based on the existing Kconfig option CONFIG_DRIVERS_UART_8250IO instead of expecting the mainboard to also define another value for ACPI. Change-Id: I69361cc2c245cfcad3e4f57567bf56d5a26f0b06 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29672 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02ec/google/wilco: Add wake pin configurationDuncan Laurie
Add a way for the mainboard to provide a wake pin that the EC will use to wake the system. This defines a _PRW object. Change-Id: I94954104bbb8226683c37abc8c0465fe3c62a693 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29408 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31ec/google/wilco: Add ACPI SuperIO devicesDuncan Laurie
Add ACPI devices for the basic SuperIO functionality provided by the EC for PS/2 keyboard, PS/2 mouse (trackpad emulation), and legacy UART. The specific defines to enable these devices should be declared by the mainboard before including this ASL, the same as the Chrome EC behavior. Change-Id: I910940ebf26b8758ab12d695e1eba9c668c640c6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-31ec/google/wilco: Add ACPI EC event handlersDuncan Laurie
Add methods to handle ACPI EC events at runtime. Currently only some common events are handled like lid switch and battery info, and the event status is printed for debug on other events. Change-Id: Ic0bd070940c8a2dfa6a251f3464301418bdb69c1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-31ec/google/wilco: Add ACPI battery and AC objectsDuncan Laurie
Add the expected objects (_BST, _BIF, _BIX) for reading battery information and status from the embedded controller, and the expected objects for reporting AC power status. The battery was tested by booting with a battery attached and checking that it is present in /sys/class/power_supply/BAT0 and that the values are consistent and within expected ranges. The AC device was tested by checking the AC status in sysfs when AC is inserted or removed while the system is running. Change-Id: Ie996891c383c9e990736690aef9795512ad6d35a Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-31ec/google/wilco: Add ACPI EC infrastructureDuncan Laurie
Add the base ACPI support for the Wilco embedded controller, using ASL 2.0 syntax throughout. This includes the EC device and its resources, as well as the layout for the EC RAM and the functions needed to read and write to the EC RAM. The EC RAM address space is typically read/write, and so the ACPI EC device expects that a defined Field can be read and/or written. With this EC the read and write address spaces are different. For example, a read from address zero will return data that is unrelated to what a write to address zero expects. This makes using a typical OperationRegion to describe the EC RAM address space somewhat impracticle, since field definitions would overlap. Instead, methods are provided for reading and writing to an EC RAM offset, and the EC RAM layout is defined as a Package that describes offset+mask for read or write fields within the EC RAM. Change-Id: If8cfdf2633db1ccad4306fe877180ba197ee7414 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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