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Users are getting build error due to duplicate macro definitions
of same resource type between fsp driver code and UEFI headers.
Hence this patch ensures to refer a single source location for
macro definitions to avoid compilation error.
Change-Id: If022eb29550a9310b095bff6130b02fb0a25ef7a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Now SOC code can select the require UDK support package for any
platform going forward with FSP2.0 model.
Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change adds the required device node in SSDT for defining
gpio-keys/gpio-keys-polled. Currently, it supports only one gpio-key
per device node.
BUG=b:71329519
TEST=Verified by adding details to devicetree that device node is
added to SSDT:
Device (PENH)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionInputOnly,
"\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x002B
}
})
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"compatible",
"gpio-keys"
}
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package (0x01)
{
Package (0x02)
{
"button-0",
"EJCT"
}
}
})
Name (EJCT, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x04)
{
Package (0x02)
{
"linux,code",
0x0F
},
Package (0x02)
{
"linux,input-type",
0x05
},
Package (0x02)
{
"label",
"pen_eject"
},
Package (0x02)
{
"gpios",
Package (0x04)
{
\_SB.PCI0.I2C0.PENH,
Zero,
Zero,
One
}
}
}
})
}
Change-Id: I6f11397b17d9de1c87d56f6a61669ef4052ec27b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23236
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Grunt (a amd-stoneyridge based platform) uses a GPIO to interface with
the tpm. This change allows devicetree entries to use a irq_gpio entry
to describe the interface with the TPM.
BUG=b:72655090
Change-Id: I08289891408d7176f68eb9c67f7a417a2448c2de
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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spi_crop_chunk() currently supports deducting the command length
when determining maximum payload size in a transaction. Add support
for deducting just the opcode part of the command by replacing
deduct_cmd_len field to generic flags field. The two enums supported
drive the logic within spi_crop_chunk():
SPI_CNTRLR_DEDUCT_CMD_LEN
SPI_CNTRLR_DEDUCT_OPCODE_LEN
All existing users of deduct_cmd_len were converted to using the
flags field.
BUG=b:65485690
Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23491
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I12ebed30de4df9814ccb62341c7715fc62c7f5b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/23431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The spi_flash_cmd_read_fast() and spi_flash_cmd_read_slow() were just
passing full size buffers to the spi controller ops. However, the
code wasn't honoring what the spi controller can actually perform.
This would cause failures to read on controllers when large requests
were sent in. Fix this by introducing a
spi_flash_cmd_read_array_wrapped() function that calls
spi_flash_cmd_read_array() in a loop once the maximum transfer size is
calculated based on the spi controller's settings.
BUG=b:65485690
Change-Id: I442d6e77a93fda411cb289b606189e490a4e464e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement
that callback for obtaining the bus config. However, we're currently
forcing another parameter of struct device so one can do the lookup.
This works for Intel-based systems since the struct device was needed
to program the BAR, etc. However, from an API standpoint, it just
complicates matters by needing to obtain the struct device. The SoC
already has knowlege of its own devices so it can get the config
itself by bus number. Therefore, remove that contraint from the API.
BUG=b:70232394
Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23420
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In ramstage the device_operations are needed for the i2c designware
host controller. Move the intel/common/block/i2c implementation
into the generic driver so other platforms can take advantage of it.
BUG=b:72121803
Change-Id: Id249933fadcc016bfba00e7a6d65f56dfc220724
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Rename the following functions to ensure it's clear that the designware
i2c host controller driver is the one that these functions are
associated with:
i2c_get_soc_cfg() -> dw_i2c_get_soc_cfg()
i2c_get_soc_early_base() -> dw_i2c_get_soc_early_base()
i2c_soc_devfn_to_bus() -> dw_i2c_soc_devfn_to_bus()
i2c_soc_bus_to_devfn() -> dw_i2c_soc_bus_to_devfn()
BUG=b:72121803
Change-Id: Idb7633b45a0bb7cb7433ef5f6b154e28474a7b6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23371
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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If one wants to implement both i2c_bus.h and i2c_simple.h APIs
the compilation unit needs to be guarded or coordinated carefully
with different compilation units. Instead, name the i2c_bus
functions with _dev such that it indicates that they operate on
struct device. One other change to allow i2c_bus.h to be built in
non-ramstage environments is to ensure DEVTREE_CONST is used for
the dev field in struct bus.
BUG=b:72121803
Change-Id: I267e27e62c95013e8ff8b0728dbe9e7b523de453
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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With no boards left using AGESA_LEGACY, wipe out remains
of that everywhere in the tree.
Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add a device driver to generate the device and required properties
into the SSDT for max98373.
TEST=verified SSDT contained relevant params
BUG=None
Change-Id: Id45f74e52855f4b19276e1d3d673d5448207ef4b
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: N, Harshapriya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/22673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch adds a member device_index to r8168 chip information which
allows driver to identify which NIC card requests MAC address.
In this implementation, only 10 NIC cards are supported, the device
index is in the range of 0 to 10. Regarding to MAC address mapping,
when there is only one NIC on DUT, it is treated as a special case
mapping to "ethernet_mac" in VPD for backward compatibility. When
there are multiple NICs on DUT, they are mapping to "ethernet_macN"
where N is [0-9].
Device tree configuration:
For single NIC: .device_index = "0", maps to "ethernet_mac"
For multiple NICs: .device_index = "[1-10]", maps to
"ethernet_mac[device_index - 1]"
BUG=b:69950854
BRANCH=None
TEST=Added device_index = [0-10] under /drivers/net in device tree &&
Programmed the mac address to VPD in shell
vpd -s ethernet_mac=<mac address> or
vpd -s ethernet-mac[0-9]=<mac address> && reboot the system.
Ensure the MAC address was fetched correctly by ifconfig command.
Change-Id: I108b9bfba39370c8906a2fa4d2b39b106e884e0c
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This automatically generates an FMAP region for the MRC_CACHE driver
which is easier to handle than a cbfsfile.
Adds some spaces and more comments to Makefile.inc to improve
readability.
Tested on Thinkpad x200 with some proof of concept patches.
Change-Id: Iaaca36b1123b094ec1bbe5df4fb25660919173ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The default time for writing MRC data to flash is at the exit of
BS_DEV_ENUMERATE but this is too early for some implementations.
Add an option to Kconfig for allowing a late option to be selected.
The timing of the late option is at the entry of BS_OS_RESUME_CHECK.
TEST=Select option and inspect console log on Kahlee
BUG=b:69614064
Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22937
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Ported from commit e6033ce1
soc/amd/common/block/pi: Fix AGESA heap deallocator
The deallocation was always subtracting the header, even when it
shouldn't. This caused problems for the allocator where buffer
sizes were incorrect and freed and used buffers could collide.
Fix the deallocation size.
Clear deallocated concatinated buffer header memory.
Fix the initial calculation of the total buffer size
available to be allocated.
Original-Change-Id: I2789ddf72d662f24709dc5d9873741169cc4ef36
Change-Id: Ibac916fcd964adca97a72617428e3d53012e13a1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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* Rename tlcl* to tss* as tpm software stack layer.
* Fix inconsistent naming.
Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Currently bootmode default is set to FSP_BOOT_WITH_FULL_CONFIGURATION
and bootmode UPD is updated in fsp_fill_mrc_cache based on mrc cache data
validity. With current implementation in S3 resume path, if mrc cache
data is invalid, the bootmode is not updated further and remains set
at FSP_BOOT_WITH_FULL_CONFIGURATION. This results in fsp-m to get
incorrect boot mode context and reinitialize memory in S3 resume
path. In correct flow fspm should have correct bootmode context
i.e. S3 resume and return error in case mrc cache data is invalid
or not found.
BUG=b:70973961
BRANCH=None
TEST=Verify correct bootmode is set on S3 resume, even when
mrc cache data is invalid.
Change-Id: Idc0da6ffbfe5ce616d852908a9b0074dc8ce7cbe
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/23156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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In S3 resume, for cases if valid mrc cache data is not found or
RECOVERY_MRC_CACHE hash verification fails, the S3 data pointer
would be null and bootmode is set to BOOT_WITH_FULL_CONFIGURATION.
This gets memory to be retrained in S3 flow. Data context including
that of imdr root pointer would be lost, invoking a hard reset in
romstage post memory init. Issuing hard reset before memory init,
saves fsp memory initialization and training overhead.
BUG=b:70973961
BRANCH=None
TEST=Verify S3 resume flows on soraka.
Change-Id: Ibd6d66793ed57c2596d9628c826f6ad198aad58b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Don't allow the user to select this manually, since it doesn't build
on platforms that don't use it.
Don't set the bool value so that it doesn't show as not selected in
the .config file of platforms that don't use this.
Change-Id: Icf026a297204868d485be270ccee7e0bec0ac73b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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BUG=b:70232394
BRANCH=none
TEST=emerge-reef coreboot
emerge-glados
Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/22822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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While the older boards use a GPIO that has no state, the newer boards'
PMH7 does have a state, that even remains after reboot.
Don't assume default values in PMH7 and instead always program it.
Fixes dGPU doesn't show up when switching from integrated to discrete
GPU. The workaround of removing all power is no longer necessary.
Change-Id: I30ec19e13269cb254e51ad1fab3b10ad1a49e86e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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In commit decd0628 (drivers/mrc_cache: move mrc_cache support to
drivers) mrc.cache is always added, but CONFIG_MRC_SETTINGS_CACHE_SIZE
is not used in Sandy Bridge, which makes mrc.cache have zero size and
the machine will fail to boot after the first boot.
Change-Id: Iab3ac87e43408ef51f0158f319eb1c8ccfce8a55
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/22925
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Seeing some instances were cr50 spi driver is starting a new
transaction without getting a ready interrupt from cr50, which means
that there are pending interrupts. Clearing these to be sure there
are not any stale irqs for the next transaction.
BUG=b:69567837
BRANCH=None
TEST=run FAFT and see if any 0x2b recovery boots occur
Change-Id: Ie099da9f2b3c4da417648ae10a5ba356b7a093ff
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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There's nothing intel-specific about the current mrc_cache support.
It's logic manages saving non-volatile areas into the boot media.
Therefore, expose it to the rest of the system for any and all to
use.
BUG=b:69614064
Change-Id: I3b331c82a102f88912a3e10507a70207fb20aecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Provide a spi controller specific protection callback to take
advantage of special spi flash controllers that have internal
protection registers built into the implementation. It's an
optional callback for spi controllers.
BUG=b:69614064
Change-Id: Ie50a6ce3bbda32620a25dd26fda1af944940bf28
Signed-off-by: Aaron Durbn <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable the flashconsole driver in verstage so it can be used
with VBOOT enabled. This was tested on a VBOOT enabled system
using flashconsole to store the boot log.
Change-Id: Icd8a82dc962ece85b9fb3d2f5654369e821922eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The opregion and fields are left over from when ACPI ASL code was
reading registers to determine the current setup. Now that the
ACPI device is generated with the correct information already this
code is not used at all and can be removed from the tree.
Change-Id: If89d90cc7105ed21e2134ac99224f6f8214cc8ad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22854
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This is required at least on Skylake to be able to configure text mode.
3rdparty/libgfxinit is also updated by the single commit:
42fb2d065d gma: Add procedure to power up legacy VGA block
Change-Id: I2fe144765e2b2acd9f6b76db375cae5b8feb5489
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Merge the different coreboot table strapping ID structures into one
because they're really just all the same, and I want to add more. Make
the signature of the board_id() function return a uint32_t because
that's also what goes in the coreboot table. Add a printk to the generic
code handling strapping IDs in ramstage so that not every individual
mainboard implementation needs its own print. (In turn, remove one such
print from fsp1_1 code because it's in the way of my next patch.)
Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Cr50 secure chip implementation is guaranteed not to fall asleep
for 1 second after any SPI slave activity.
Let's not waste time on the wake up ping when it is not necessary.
BRANCH=cr50
BUG=b:68012381
TEST=using a protocol analyzer verified that the wake pulses are
generated only when the new coreboot stage or depthcharge start,
not on every SPI slave transaction.
Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch adds SSDT ACPI generator and declares _UID, _HID, _DDN and
also _PRW for WOL feature. Besides, adds a wake variable in chip
information.
BUG=b:69290148
BRANCH=None
TEST=Add register "wake" = "GPE0_PCI_EXP" in devicetree under r8168
chip driver && dump SSDT to make sure _UID, _HID, _DDN and _PRW
are filled correctly && put system into S3 && sudo etherwake -i
eth0 $MAC to make sure the system could be woken up by WOL package.
Change-Id: Ibc9115e8a08ba2bfcb3ee1e34c73cf1976a6ba2d
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The Cr50 i2c driver provides separate entry points for probing and
initialization, but probing function does not really do much.
It also claims and releases locality on every coreboot stage, but
there is no need for this - locality should be definitely claimed
after reset and then it could be retained through the boot process.
On top of that the driver does not properly account for long time it
could take the Cr50 chip to come around to reset processing if TPM
reset request was posted during a lengthy TPM operation.
This patch addresses the issues as follows:
- tpm_vendor_probe() and tpm_vendor_cleanup() become noops, kept
around to conform to the expected driver API.
- tpm_vendor_init() invokes a function to process TPM reset only in
the first stage using TPM (typically verstage), the function
checks if locality is claimed and if so - waits for it to be
released, which indicates that TPM reset processing is over.
- before claiming locality check if it is already taken, and if so -
just proceed.
BRANCH=none
BUG=b:65867313, b:68729265
TEST=Verified that reef no longer hangs during EC reboot and
firmware_Cr50ClearTPMOwner (not yet merged) tests.
Change-Id: Iba8445caf1342e3a5fefcb2664b0759a1a8e84e3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
All coreboot stages using TPM start with the same sequence: check if
locality is claimed, if so, release it by writing 'active locality'
bit, then try claiming it.
This is actually not a proper procedure: section "5.5.2.3.1 Command
Aborts" of "TCG PC Client Platform TPM Profile (PTP) Specification
Level 00 Revision 00.430 Family 2" lists overwriting active locality
status bit as a means of triggering TPM command abort.
On top of that, none of the coreboot stages releases locality, it is
enough to claim it once when device starts booting.
In fact, locality being active when the device is in verstage is most
likely due to delayed TPM reset processing by the Cr50 TPM: reset is
an asynchronous event, and is processed once current command
processing completes.
The proper procedure is to wait if locality is active until it is
released (which will happen when Cr50 processes reset) and then
proceed to claim it. This needs to happen only during verstage, other
stages using TPM are guaranteed has been claimed earlier.
BRANCH=gru
BUG=b:65867313
TEST=the new autotest triggering EC reset during key generation
process does not cause boot failures on Fizz device any more.
Below are times verstage had to wait:
TPM ready after 3132 ms
TPM ready after 22120 ms
TPM ready after 4936 ms
TPM ready after 6445 ms
TPM ready after 11798 ms
TPM ready after 27421 ms
TPM ready after 4582 ms
TPM ready after 7532 ms
TPM ready after 27920 ms
TPM ready after 3539 ms
TPM ready after 12557 ms
TPM ready after 6773 ms
TPM ready after 1631 ms
TPM ready after 197 ms
TPM ready after 24330 ms
TPM ready after 3241 ms
Change-Id: Iaee04f009bcde03712483e5e03de4a3441ea32b1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
In case the TPM is doing a long crypto operation the initial probe
could be very delayed. Rather than end up in recovery make the delay
long enough to accommodate the (current) long crypto times. This would
add a maximum of 30 seconds to boot time.
Mirroring changes done on i2c side in CL:756918
BUG=b:65867313, b:68729265
BRANCH=None
TEST=Make sure fizz boots up
Change-Id: Ie944bfb6fe33d6e9ee794439165716ab624be491
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
In case the TPM is doing a long crypto operation the initial probe
could be very delayed. Rather than end up in recovery make the delay
long enough to accommodate the (current) long crypto times.
BUG=b:65867313, b:68729265
TEST=Verified that Soraka no longer hangs during EC reboot test.
Change-Id: I3bccff70e001dfc065c24be8ad34ef239a144db1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Some Siemens copyright entries incorrectly contain a dot at the end of
the line. This is fixed with this patch.
Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Once coreboot is ready and payload has been loaded a bit inside the NC
FPGA needs to be set to notify this event. As there are NC FPGAs with
different PCI device IDs save the BAR0 address in a global variable once
the driver evaluates this address. It can then be used to access the
register from the boot state machine callback without the need of searching
for all possible PCI devices again.
As this driver is only used at ramstage there is no need of using
CAR_GLOBAL for the global variable. Use a Kconfig switch to make this
feature selectable from mainboard as not every mainboard may have a FPGA
with that capability.
Change-Id: I9cd09e7051edde30d144a7e020b84bb549e9e8b9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use the correct conversion specifier for `size_t` to fix the error
below.
```
src/drivers/intel/fsp2_0/hob_verify.c:31:4: error: format '%lx' expects \
argument of type 'long unsigned int', but argument 4 has type \
'size_t {aka unsigned int}' [-Werror=format=]
"FSP_BOOTLOADER_TOLUM_SIZE: 0x%08llx < 0x%08lx\n",
^
range_entry_size(&tolum), cbmem_overhead_size());
~~~~~~~~~~~~~~~~~~~~~
```
Found-by: gcc (Debian 7.2.0-8) 7.2.0
Change-Id: I4631672211095f9934925e9bd230ccbf63c736af
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
When Cr50 TPM is being reset, it continues replying to the SPI bus
requests, sends wrong register values in response to read requests.
This patch makes sure that the TPM driver does not proceed unless
proper value is read from the TPM device identification register.
If the read value is still wrong after 10 retries taken with 10 ms
intervals, the driver gives up and declares TPM broken/unavailable.
BRANCH=cr50
BUG=b:68012381
TEST=ran a script resetting the Fizz device as soon as the "index
0x1007 return code 0" string shows up in the AP console output.
The script keeps rebooting the Fizz indefinitely, before this
script Fizz would fail to read TPM properly and fall into
recovery after no more than four reboots.
Change-Id: I7e67ec62c2bf31077b9ae558e09214d07eccf96b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch adds a function to program a customized LED setting
for Realtek 81xx family. It reads the settings from devicetree under
target board and programs the setting to offset 0x18 and 0x19.
BUG=b:65437780
TEST=Add customized_leds register in devicetree.cb under target board,
enable RT8168_SET_LED_MODE flag. Make sure the setting is
programmed correctly to offset 0x18 and 0x19. Observed the
LEDs were behaving as expected. Executed suspend/resume and
the LEDs were still working as expected.
Change-Id: Ib3d4f2cd98ac391e1661a891d604bdd1974d07f6
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Simplifies our C interface function gma_gfxinit(), due to the following
changes:
* *libgfxinit* knows about the underlying PCI device now and can
probe MMIO addresses by itself.
* The framebuffer mapping is now completely handled inside the
library where we validate that we neither overflow
- the stolen memory,
- the GTT address space, the GTT itself nor
- the aperture window (i.e. resource2 of the PCI device)
that we use to access the framebuffer.
Other changes:
* Fixes and a quirk for DP training.
* Fix for DP-VGA adapters that report an analog display in EDID.
* Fixes for Skylake support with coreboot.
* DDI Buffer drive-strength configuration for Haswell, Broadwell and
Skylake.
* `gfx_test` can now be run from X windows (with glitches).
* Compatibility with GCC 7 and SPARK GPL 2017.
TEST=Booted lenovo/t420 and verified that everything works as usual.
Change-Id: I001ba973d864811503410579fd7ad55ab8612759
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
The current header `i915.h` is too invasive to be used everywhere where
we want to use *libgfxinit*.
Change-Id: Iba57256d536e301e598d98182448d2daa1bf9a89
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Although Intel's current spec[1] shows the OpRegion structure version
as being the top 16 bits of the field, Intel's Windows drivers
require the OpRegion structure version to be in the top 8 bits of
the field when not using a VGA BIOS (eg, NGI or GOP driver).
As the Linux i915 driver only checks that the version is >= 2,
there is no change in functionality there.
This change effectively matches Intel's implementation in TianoCore,
where the version is set to 0x0200 << 16.
[1] https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
TEST: Boot Windows [8.1,10] in UEFI mode w/GOP graphics init and
Legacy mode with libgfxinit, observe Intel GPU driver functional.
Change-Id: Ic2903ee4829689ec4117aec93dce0b87cec6f313
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
There are still Ethernet drivers out there in the wild which expect
that the master enable bit was set by firmware. A missing master
enable bit will lead to a non-functional driver. Though it is clear the
task of the driver to set this bit it is too late now. So work around
this issue on firmware level...again!
Change-Id: I677b22c643b73634b1a2129d948b991446e1f8fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
|
|
1. Add support for new GSMI commands to log S0ix entry/exit
information in elog.
2. In case of resume, provide callbacks to allow platform and
mainboard to log any wake source information.
BUG=b:67874513
Change-Id: I593e8a9e31cad720ac1f77aab447a0dbdbe9a28b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add hexdump.c to Makefile.inc and change an elog_debug format to
use %z for size_t arguments. This corrects build errors when ELOG_DEBUG
is used.
Change-Id: I3d5547eed8ada7c4bdcbbb8bb9d6965ade73beda
Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com>
Reviewed-on: https://review.coreboot.org/21769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
If FSP 2.0 is used, then postcar stage is used and the flashconsole
as well as spi drivers needed to be added.
Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Before adding a new UART to the coreboot/lb table, verify that it
has a non-zero base address. This is consistent with all other
functions that use the uart_platform_base() function.
This was tested on google/kahlee by using an invalid UART number
and forcing the base address to 0. Execution was able to complete
through depthcharge and into the OS.
Change-Id: I6d8183a461f0fedc254bf88de5ec96629a2a80ef
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21996
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add a new common method to initialize ACPI OpRegion.
* Try to locate vbt.bin in CBFS.
* Try to locate VBIOS in CBFS.
* Keep existing code to probe at 0xc0000.
Tested on Lenovo T430 (sandybridge) using vbt.bin, tested using buggy
VBIOS with wrong vbt_offset, tested with fake vbt written by NGI at
0xc0000.
Tested with https://review.coreboot.org/#/c/21766/ on i945 (using fake
vbt at 0xc0000), x4x (using vbt.bin) and gm45 (using vendor VBIOS).
In all cases linux was successfully provided with VBT from ACPI
opregion.
Change-Id: I8ee50ea9900537bd9e3ca5ab0cd3f48d2acec970
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: I65c423660ab1778f5dd9243e428a4d005bd1699a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Instead of having all callers provide a region_device just for the
purpose of reading vbt.bin, let locate_vbt handle its entire life cycle,
simplifying the VBT access API.
Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
All callers of locate_vbt just care about the file content and
immediately map the rdev for its content.
Instead of repeating this in all call sites, move that code to
locate_vbt.
Change-Id: I5b518e6c959437bd8f393269db7955358a786719
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
No need for having two of everything in the coreboot codebase.
Change-Id: Ie1cdd1783dd5dababd1e97436a4ce1a4f068d5b3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch removes checks that ensure EC to be in RO for recovery
boot. We do not need these checks because when recovery is requested
automatically (as opposed to manually), we show 'broken' screen where
users can only reboot the device or request recovery manually.
If recovery is requested, Depthcharge will check whether EC is in RO
or not and recovery switch was pressed or not. If it's a legitimate
manual recovery, EC should be in RO. Thus, we can trust the recovery
button state it reports.
This patch removes all calls to google_chromeec_check_ec_image,
which is called to avoid duplicate memory training when recovery
is requested but EC is in RW.
BUG=b:66516882
BRANCH=none
CQ-DEPEND=CL:693008
TEST=Boot Fizz.
Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
For general use of this driver it is necessary to move some parameters
from init_fan_ctrl() to init_temp_mon(). This shift does not lead to any
functional change.
Change-Id: I6b8f770c768f3dacf96087eb0194cc99f0d11e17
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Remove the USBDEBUG_DONGLE_BEAGLEBONE_BLACK option that does the same as
USBDEBUG_DONGLE_STD and update the description of USBDEBUG_DONGLE_STD that it
also should be selected for the BeagleBone Black.
Change-Id: I3093a6d2c39e7b5e81785028e436109090d9e6dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/21486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I4d6c6810b91294a7e401a4a1a446218c04c98e55
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
|
|
New AGESA support files will be used for binaryPI
platforms as well. Furthermore, some of those should
move from split nb/ sb/ directories to soc/, so move
support files for the API under drivers/.
Change-Id: I549788091de91f61de8b9adc223d52ffb5732235
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Instead of having each potential caller deal with the differences
of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the
correct logic within the callee, cmos_init(), for handling the
vbnv in CMOS. The internal __cmos_init() routine returns when the
CMOS area was cleared.
BUG=b:63054105
Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21549
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There's no reason to mutate the struct device when determining
the ACPI name for a device. Adjust the function pointer
signature and the respective implementations to use const
struct device.
Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
It was originally designed such that if usbdebug_init() was called
before cbmem_initialize(), it would fetch the already-initialized
state from CBMEM. This changed when cbmem_find() behaviour changed
to require cbmem_initialize() to be called first. As a result,
ramstage had to reinitialize all of the EHCI controller and USB
endpoints on entry. This was slow, specially with AMD hardware
where one can scan USB ports to probe for the debug dongle.
For postcar and ramstage, move usbdebug entry such that it is
triggered from CBMEM_INIT_HOOK instead of console_init().
Side-effect of this is usbdebug console shows 'coreboot-xxx ...
starting...' line only for romstage.
Initialisation for usbdebug is never done in postcar. If you have
USBDEBUG_IN_ROMSTAGE=n, postcar will not have console output on
usb either.
While at it, fix also some other __PRE_RAM__ cases to ENV_ROMSTAGE
and alike.
Change-Id: If8ab973321a801abc5529f3ff68c5dccae9512ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
To avoid error with symbol redefinition (using clang):
src/drivers/intel/fsp1_0/fsp_util.c:111:22: error: invalid symbol redefinition
".global find_fsp\n\t"
Rename the asm global symbol to find_fsp_bypass_prologue and fix jmp.
Change-Id: I84c152f9a580fdfc40e9f6e998d2d6484b7f47df
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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With FSP 1.1, all FSP blobs are forward-compatible with newer FSP 1.1
header files, so adjust the header revision check to ensure that the
FSP blob isn't newer than the header, rather than an exact version match.
This resolves a version mismatch issue with Braswell ChromeOS devices,
which ship with FSP blobs newer than the publicly-released blob (1.1.2.0),
but older than the current Braswell FSP 1.1 header (1.1.7.0).
TEST: build/boot google/cyan and edgar boards, observe no adverse
effects from using current FSP header (1.1.7.0) with the factory-
shipped FSP blobs (1.1.4.0/1.1.4.2).
Change-Id: I8934675a2deed260886a83fa34512904c40af8e1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change list adds imon and vmon slot numbers as params for
Maxim 98927 driver. These values are looked up in the kernel driver
to confiure IV feedback for audio playback on speakers.
BUG=b:36724448
TEST=After boot, the register dump for Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.
Change-Id: I21d72ba91af83782587f11018b2d1d1c8d4f676c
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Move ADD_VBT_DATA_FILE to "Devices" menu and rename it to
INTEL_GMA_ADD_VBT_DATA_FILE.
Depend on Intel platforms to avoid confusing users of non-Intel platforms.
The Intel GMA driver will use the vbt.bin, if present, to fill the
ACPI OpRegion.
Change-Id: I688bac339c32e9c856642a0f4bd5929beef06409
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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There is at least one I2C device (being used by Soraka) that has 3
controls -- enable, reset and stop. If the stop gpio is not put into
the right state when turning off the device in suspend mode, then it
causes leakage. Thus, we need control in power resource to be able to
stop the device when entering suspend state.
BUG=b:64987428
TEST=Verified on soraka that touchscreen stop is correctly configured
on suspend.
Change-Id: Iae5ec7eb3972c5c7f80956d60d0d3c321bbefb0f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21249
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replaces the ics/954309 driver with a more generic version to
accommodate clockgens with a different amount of registers.
It also features a mask to only touch certain bits of the clockgen.
TODO: set appropriate mask for X60/T60 since the datasheets for their
clockgens can be found.
Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Add support for providing additional free form device properties via
devicetree in order to make this driver suitable for kernel drivers
that need additional board-specific device properties.
This currently allows adding up to 10 additional properties to a device.
BUG=b:63413023
TEST=manual testing to ensure that newly added properties are in SSDT
Change-Id: I2b8ceb208f4aba01053746547def6d07c8f8f3a2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/21270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch to ensure that coreboot is able to store memory
training data into SPI and perform platform lockdown after
PCI enumeration is done before handing over control to
NotifyPhase() - Post PCI enumeration.
Modified coreboot bootstate execution order below:
BS_DEV_ENUMERATE - BS_ON_EXIT - Store Memory training data into SPI
BS_DEV_RESOURCES - BS_ON_EXIT - Platform Lock Down after PCI enumeration
BS_DEV_ENABLE - BS_ON_ENTRY - NotifyPhase() post PCI enumeration
TEST=Please find test case and results for Chrome Devices as Apollolake- Reef,
Kabylake-Eve and Poppy and Non Chrome Devices with Yocto OS.
1.
Without patches
Cold Boot
MRC: no data in 'RW_MRC_CACHE'
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Warm Reboot from Chrome CMD Line: $ reboot
MRC cache found, size 18c8 bootmode:2
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state
MRC cache found, size 18c8 bootmode:17
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
2.
With patches
Cold Boot
MRC: no data in 'RW_MRC_CACHE'
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Warm Reboot from Yocto CMD Line: $ reboot
MRC cache found, size 18c8 bootmode:2
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state
MRC cache found, size 18c8 bootmode:17
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Tested the patches more thoroughly, from the S5->S0, S3->S0 bootlog there
is no noticeable difference.
On a reboot, suspend resume from Chrome console, the mrc cache is found,
and utilized.
Change-Id: I4cb4eac5256c1ce98f51adad0be6e69f7d05d8e1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: Ib31e77eec639c231520198c0b978d6c3c1eadaed
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Move the FSP-specific call for tearing down cache-as-RAM out of
postcar.c and replace it with an empty weak function.
This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)). The
temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built
when CONFIG_FSP_CAR is true.
Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20965
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Initialize postcar frame once finish FSP memoryinit
This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534
Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Our current struct for I2C segments `i2c_seg` was close to being compa-
tible to the Linux version `i2c_msg`, close to being compatible to SMBus
and close to being readable (e.g. what was `chip` supposed to mean?) but
turned out to be hard to fix.
Instead of extending it in a backwards compatible way (and not touching
current controller drivers), replace it with a Linux source compatible
`struct i2c_msg` and patch all the drivers and users with Coccinelle.
The new `struct i2c_msg` should ease porting drivers from Linux and help
to write SMBus compatible controller drivers.
Beside integer type changes, the field `read` is replaced with a generic
field `flags` and `chip` is renamed to `slave`.
Patched with Coccinelle using the clumsy spatch below and some manual
changes:
* Nested struct initializers and one field access skipped by Coccinelle.
* Removed assumption in the code that I2C_M_RD is 1.
* In `i2c.h`, changed all occurences of `chip` to `slave`.
@@ @@
-struct i2c_seg
+struct i2c_msg
@@ identifier msg; expression e; @@
(
struct i2c_msg msg = {
- .read = 0,
+ .flags = 0,
};
|
struct i2c_msg msg = {
- .read = 1,
+ .flags = I2C_M_RD,
};
|
struct i2c_msg msg = {
- .chip = e,
+ .slave = e,
};
)
@@ struct i2c_msg msg; statement S1, S2; @@
(
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1 else S2
|
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1
)
@@ struct i2c_msg *msg; statement S1, S2; @@
(
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1 else S2
|
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1
)
@@ struct i2c_msg msg; expression e; @@
(
-msg.read = 0;
+msg.flags = 0;
|
-msg.read = 1;
+msg.flags = I2C_M_RD;
|
-msg.read = e;
+msg.flags = e ? I2C_M_RD : 0;
|
-!!(msg.read)
+(msg.flags & I2C_M_RD)
|
-(msg.read)
+(msg.flags & I2C_M_RD)
)
@@ struct i2c_msg *msg; expression e; @@
(
-msg->read = 0;
+msg->flags = 0;
|
-msg->read = 1;
+msg->flags = I2C_M_RD;
|
-msg->read = e;
+msg->flags = e ? I2C_M_RD : 0;
|
-!!(msg->read)
+(msg->flags & I2C_M_RD)
|
-(msg->read)
+(msg->flags & I2C_M_RD)
)
@@ struct i2c_msg msg; @@
-msg.chip
+msg.slave
@@ struct i2c_msg *msg; expression e; @@
-msg[e].chip
+msg[e].slave
@ slave disable ptr_to_array @ struct i2c_msg *msg; @@
-msg->chip
+msg->slave
Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
These Kconfig options can be reused for the same purpose of selecting
the correct i2c pins for probing the analog output EDID in C native
graphic init. For this purpose this patch makes those options
independent of GFX_GMA and MAINBOARD_HAS_LIBGFXINIT.
Change-Id: If29c541d414e12b95d96ae9c249a7a20e863fe06
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Migrate opregion code from northbridge/intel/common to
drivers/intel/gma in preparation for consolidation with
soc/intel/common opregion code. Rename init_igd_opregion()
for clarity and disambiguation with other implementations.
Change-Id: I2d0bae98f04dbe7e896ca34e15f24d29b6aa2ed6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
EvLoader is FSP module which loads and runs MMA tests.
With Change-Id Id31ddd4595e36c91ba7c888688114c4dbe4db86a, EvLoader
needs to be enabled with UPD param from coreboot.
Change-Id: Ifb860b98d6e6f21c116473a962f647e491e8546f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Get rid of old hybrid graphics driver and use the new one.
1. Disable IGD and PEG in early romstage.
The PEG port will get disabled on devices that do not have a
discrete GPU. The power savings are around ~1Watt.
The disabled IGD does no longer waste GFX stolen memory.
2. Get rid of PCI driver
The Nvidia GPU can be handled by the generic PCI driver and allows
to use the ACPI _ROM generator for Switchable graphics.
3. Settings are stored in devicetree.
One driver for all Lenovo hybrid graphics capable devices.
4. Add support for Thinker1 GPU power handling.
Only boards that do use reference design 2012 are known to be
supported. Needs test on boards that do you use reference design 2013.
Should reduce idle power consumption when using IGD by ~5Watt.
Tested on Lenovo T430 without DGPU. PEG port is disabled.
Needs test on all devices.
Change-Id: Ibf18b75e8afe2568de8498b39a608dac8db3ba73
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Use new hybrid graphics driver to get device state.
Move remaining code to romstage.c.
Tested on Lenovo T500:
* Linux 4.11.4 on Fedora 25
* Integrated (using NGI)
* Discrete (using VGA OpROM)
* Switchable (using NGI and VGA OpROM), tested with DRI_PRIME
No regressions found.
Change-Id: Iad2eccaab19c71f11308853ba9326d8186e67c93
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Introduce a chip_driver that uses devicetree instead of Kconfig.
The new driver has the following advantages:
* No more wasted IGD GFX stolen memory
* Can be used by T500 series
* Is even run on devices that do not have a dGPU installed
* Can disable unused PEG port on devices without dGPU (and save power)
* Use devicetree instead of Kconfig options
* Support for multiple hybrid GPIO active levels
* Support for backlight control GPIO
* Support for _ROM on Optimus capable devices
The driver is split into romstage part and ramstage part.
Every mainboard has to call the driver in romstage to get the requested
GPU state. The mainboard code then has to toggle GPU power or disable
the IGD or PEG port.
The ramstage part does handle the hygrid graphics GPIO, including
optional backlight mux GPIO. Every GPIO can have it's own active level,
as defined in devicetree. Devices are no longer disabled in ramstage.
The existing hybrid graphics driver does the same configuration and
should not interfere with this commit until it has been removed.
Change-Id: Ie467f9a18b35ab3b8a523dbf51c5575db5b374a5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
If all strings in SMBIOS table are empty, smbios_string_table_len
function should return 2, cause every table must end with "\0\0".
Also replace "eos" field type in smbios structures
from char to u8.
Change-Id: Ia3178b0030aa71e1ff11a3fd3d102942f0027eb1
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-on: https://review.coreboot.org/20840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
This commit adds a new driver for the RT5663 codec to use instead
of the generic i2c driver. Since the kernel needs additional
driver-specific device properties we need a BIOS driver that can
provide those properties.
The kernel driver devicetree properties for this codec are at:
linux/Documentation/devicetree/bindings/sound/rt5663.txt
This was tested by booting and verifying the generated SSDT
contains the expected device properties in _DSD.
Scope (\_SB.PCI0.I2C4)
{
Device (RT53)
{
Name (_HID, "10EC5663")
Name (_UID, Zero)
Name (_DDN, "Realtek RT5663 Codec")
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate ()
{
I2cSerialBus (0x0013, ControllerInitiated, 0x00061A80,
AddressingMode7Bit, "\\_SB.PCI0.I2C4",
0x00, ResourceConsumer)
GpioInt (Edge, ActiveBoth, Exclusive, PullDefault, 0x0000,
"\\_SB.PCI0.GPIO", 0x00, ResourceConsumer)
{
0x0051
}
})
Name (_DSD, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
Package (0x05)
{
Package (0x02)
{
"irq-gpios",
Package (0x04)
{
\_SB.PCI0.I2C4.RT53,
Zero,
Zero,
Zero
}
},
Package (0x02)
{
"realtek,dc_offset_l_manual",
0x00FFD160
},
Package (0x02)
{
"realtek,dc_offset_r_manual",
0x00FFD1C0
},
Package (0x02)
{
"realtek,dc_offset_l_manual_mic",
0x00FF8A10
},
Package (0x02)
{
"realtek,dc_offset_r_manual_mic",
0x00FF8AB0
}
}
})
}
}
Change-Id: I3425fcbe13c9a5987fc91086d283a86db55c0819
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Ensure that the VLF bit will be cleared after a power loss event even if
the stopwatch has expired before the code to clear the bit is reached.
Change-Id: Ib2cfdabf4cd4df834395d6a102c6ae70568e71db
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
|
|
When resuming from ACPI S3 suspend, EHCI controller
may be in D3 power-management state. Bring it to D0
early so it is functional for console.
NOTE: D3hot->D0 transition was observed to reset
previous programming of PCI_COMMAND register.
Change-Id: Id177ce61926beb057fe67ba42a306d8e565d2657
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Always sanity check for EHCI class device and move
PCI function power enablement up.
Change-Id: I1eebe813fbb420738af2d572178213fc660f392a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
There is assumption of static EHCI_BAR_INDEX, try to
clean it up by bringing BAR programming at one spot.
Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
If TTYS0_BAUD is not configured, then by default use baudrate of 115200.
BUG=b:64030366
Change-Id: Ida4c7ae77aba5dfd4ec331e22a54ce43a91bde00
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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In S3 resume, wifi is one of the wake sources.
If elog is enabled in config, then log wifi wakes in elog.
BUG=b:36992859
TEST= Build for Soraka. Do WoWlan during S3. Verify elog having update
on wake due to Wifi.
Change-Id: I7d42c5c81e0a3f7a3f94c3f6b7d2ebdf029d1aff
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This excludes files which are mostly spaces, which I felt should be
handled separately.
Change-Id: I33043a3090e2fc6e9d2fd81e8a5e46fb6cb0aa35
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The functionality of the FAN controller is extended to provide a
lowest startup speed of the FAN. Add the parameter "fanmin" to
the fan_ctrl_t structure and initialize the value.
Change-Id: Ib2e093ed6f5fc29bbea879779eb4777eb371b937
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Gather related code in the new file drivers/pc80/rtc/mc146818rtc_boot.c,
call sanitize_cmos() from C environment bootblock.
Change-Id: Ia5c64de208a5986299c0508d0e11eeb8473deef1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fixes builds with BOOTBLOCK_CONSOLE && USE_OPTION_TABLE.
Change-Id: I1c7e9baa60f33c2c3651e2def0335454f7e20451
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Assert incase unable to locate hob list pointer due to cbmem
is not available.
Change-Id: I17f54b07ab149ae06d09226ed9063189d829efe2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This reverts commit 399c022a8c6cba7ad6d75fdf377a690395877611.
This was merged too early. I'll repost it.
Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20686
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialize postcar frame once finish FSP memoryinit
Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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