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This patch adds config to let SoC users (config) to choose if EISA HID
is supported. All SoC config would like to support EISA HID need to
select `HAVE_DPTF_EISA_HID` config.
Prior to Tiger Lake, all DPTF devices used 7-character EISA
IDs. If selected, the 7-character _HIDs will be emitted,
otherwise, it will use the "new" style, which are regular
8-character _HIDs.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6bf64f74c447b28665d31a64181c33df882d5d06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71108
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817) add
support for TBAT device under \_SB.DPTF
BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TBAT device
Device (TBAT)
{
Name (_HID, "INTC1061") // _HID: Hardware ID
Name (_UID, "TBAT") // _UID: Unique ID
Name (_STR, "Battery Participant") // _STR: Description String
Name (PTYP, 0xC)
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I9104318fd838f30253ab1eeac4e212b3b917f516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817)
Add support for TPWR device under \_SB.DPTF
BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TPWR device
Device (TPWR)
{
Name (_HID, "INTC1060") // _HID: Hardware ID
Name (_UID, "TPWR") // _UID: Unique ID
Name (_STR, "Power Participant") // _STR: Description String
Name (PTYP, 0x11)
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62944
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new thermal control mechanism for pch device under dptf driver.
This provides support of different control knobs for FIVR.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I035d2844b9ba6a9532ae006fc1c43e34cb94328a
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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DPTF HIDs are different per-platform going forward, so refactor these
into SoC-specific structures which the DPTF driver can query at runtime
for platform-specific information.
Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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The prompts for the DPTF Kconfig options were not necessary, they should
be selected based on what DPTF implementation is being used, ASL files
or generated at runtime. It's not really meant to be fiddled with at
build-time. Also rewrite the help text for the _HID selection, to try
and make it more clear when to use y or n.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6edcabd28426916d9586d501b95b510dfc163fc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43830
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In this DPTF implementation, the participant device objects are written
into the DSDT with only minimal Names attached (_HID/_ADR, _STA, _UID,
PTYP, and _STR). All other Methods & Names will be written into the
SSDT. If a device is not used in any policy, then its _STA is set to
return 0 ("off").
BUG=b:143539650
TEST=Compiles.
Change-Id: Ief69a57adce9ee0b19056ce6a11ed8a5b51b3f87
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Currently, configuring and reviewing DPTF parameters is difficult
because DPTF tables and methods are defined in static ASL files, and are
littered with #ifdefs which both define parameters and influence
behavior (e.g., whether a method is included or not). This patch train
is an effort to bring DPTF support to our ACPI DSDT/SSDT generation
framework.
This first patch is very minimal, and includes only creation of the
DPTF device (in the DSDT).
BUG=b:143539650
TEST=compiles (later tests get more comprehensive).
Change-Id: I14df9f422c911677aeea25552ac1822a9462c58a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41883
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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