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2004-11-04tell people that the segment descriptors are different for ROMCC andLi-Ta Lo
GCC code. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04- Update abuild.sh so it will rebuild successfull buildsEric Biederman
- Move pci_set_method out of hardwaremain.c - Re-add debugging name field but only include the CONFIG_CHIP_NAME is enabled. All instances are now wrapped in CHIP_NAME - Many minor cleanups so most ports build. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-03This hurts more than it helps. byebyeStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02*** empty log message ***Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-31fix soloStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-30- To reduce confuse rename the parts of linuxbios bios that run fromEric Biederman
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload... - Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86 - ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB. - Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work. - Start using romcc's built in preprocessor (This will simplify header compiler checks) - Add helper functions for examining all of the resources - Remove debug strings from chip.h - Add llshell to src/arch/i386/llshell (Sometime later I can try it...) - Add the ability to catch exceptions on x86 - Add gdb_stub support to x86 - Removed old cpu options - Added an option so we can detect movnti support - Remove some duplicate definitions from pci_ids.h - Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic - Minor romcc bug fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-29Changes to allow Via/Epia code to be compiled after recent code changes.Mark Wilkinson
New Files :- src/cpu/via/model_centaur/Config.lb src/cpu/via/model_centaur/model_centaur_init.c Updated Files :- src/arch/i386/include/arch/smp/mpspec.h - make write_smp_table a define for non smp systems src/cpu/x86/lapic/lapic_cpu_init.c - change possible typo src/mainboard/via/epia/Config.lb src/mainboard/via/epia/Options.lb src/mainboard/via/epia/auto.c src/mainboard/via/epia/chip.h src/mainboard/via/epia/failover.c - updated after recent code changes src/northbridge/via/vt8601/chip.h src/northbridge/via/vt8601/northbridge.c src/northbridge/via/vt8601/raminit.c - corrections after recent code changes to allow compiling src/southbridge/via/vt8231/chip.h src/southbridge/via/vt8231/vt8231.c - initial pass to allow compiling after recent code changes. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27sizeram removal/conversion.Eric Biederman
- mem.h and sizeram.h and all includes killed because the are no longer needed. - linuxbios_table.c updated to directly look at the device tree for occupied memory areas. - first very incomplete stab a converting the ppc code to work with the dynamic device tree - Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources). - First stab at Pentium-M support - add part/init_timer.h making init_timer conditional until there is a better way of handling it. - Converted all of the x86 sizeram to northbridge set_resources functions. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27- Actually enable the Pentium-M cpusEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27- Bug fixes to the P-III supportEric Biederman
- Initial Pentium-M support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25ops and tscYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23- With Xeon cpus it seems best to use the tsc calibrated with timer2 asEric Biederman
the time source. The apic timer also has a variable time base. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22for S2735 supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22s2735 half updateYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22- Better memory I/O space distinguishing in amd_mtrr.cEric Biederman
This is way to much code duplication but for now things work. - Fix the typo in amd8111_lpc.c - Remove an unused macro, use continue instead of break in mtrr.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- Bump the LinuxBIOS major versionEric Biederman
- Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- Explicitly disable the fixed dram extensions bits.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- We already know the cache is disabled so don't bother disabling it.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19- add support for socket 754Stefan Reinauer
- fix configuration creation for amd solo (doesn't compile yet) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19- Fix bug with > 4GB of memory where PAE was left enabled.Eric Biederman
Why didn't this show up until I had > 4GB on one cpu? git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- HDAMA boots!Eric Biederman
- Set the bootstrap processor flag in the mptable. - Implement 64bit support in our print statements - Fix the reporting of how many cpus we are waiting to stop. It is the 1 less than the actual number of cpus running. - Actually enable cpu_initialization. - Fix firstsiblingdevice in config.g - Add IORESOURCE_FIXED to all of the resources set by config.g - Fix the apic_cluster rule to add an apic_cluster path not an apic path. - Add a div64.h to assist in the 64bit printf. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- First stab at running linuxbios without the old static device tree.Eric Biederman
Things are close but not quite there yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- First pass through with with device tree enhancement merge. Most of the ↵Eric Biederman
mechanisms should be in place but don't expect anything to quite work yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- remove deprecated directoriesEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- Add new cvs code to cvsEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06epia-m supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-01Intel E7501 P64H2 ICH5R supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-05Add extra phase before memory init.Greg Watson
Rename sdram_init to memory_init NOTE: need to test sandpoint and ep boards! git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03Make names more sensible.Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-06-03Clock (not timer) routines are board specific. Moved to appropriateGreg Watson
mainboard dir. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-26cleanupStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-24added AGP support for AMD K8Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-14refactored k8_cpufixup, added IORR support for AGP apertureLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-13code reformatLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-06replace up,across,down with ltd0,ldt1, ldt2Li-Ta Lo
Although it is not used currently, misuse of terminolog is still a misuse. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-21moved to crt0.S.lbGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-21i like ori betterGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1520 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-21include cache codeGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1519 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-26speed up ecc clear by enable MTRR/Cache first.Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1483 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-23Doxidization, reformatLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-23tighten up option exportingGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-11- Moved hlt() to it's own header.Eric Biederman
- Reworked pnp superio device support. Now complete superio support is less than 100 lines. - Added support for hard coding resource assignments in Config.lb - Minor bug fixes to romcc - Initial support for catching the x86 processor BIST error codes. I've only seen this trigger once in production during a very suspcious reset but... - added raminit_test to test the code paths in raminit.c for the Opteron - Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED so we can tell what we have really done. - Added generic AGP/IOMMU setting code to x86 - Added an implementation of memmove and removed reserved identifiers from memcpy - Added minimal support for booting on pre b3 stepping K8 cores - Moved the checksum on amd8111 boards because our default location was on top of extended RTC registers - On the Hdama added support for enabling i2c hub so we can get at the temperature sensors. Not that i2c bus was implemented well enough to make that useful. - Redid the Opteron port so we should only need one reset and most of memory initialization is done in cpu_fixup. This is much, much faster. - Attempted to make the VGA IO region assigment work. The code seems to work now... - Redid the error handling in amdk8/raminit.c to distinguish between a bad value and a smbus error, and moved memory clearing out to cpufixup. - Removed CONFIG_KEYBOARD as it was useless. See pc87360/superio.c for how to setup a legacy keyboard properly. - Reworked the register values for standard hardware, moving the defintions from chip.h into the headers of the initialization routines. This is much saner and is actually implemented. - Made the hdama port an under clockers BIOS. I debuged so many interesting problems. - On amd8111_lpc added setup of architectural/legacy hardware - Enabled PCI error reporting as much as possible. - Enhanded build_opt_tbl to generate a header of the cmos option locations so that romcc compiled code can query the cmos options. - In romcc gracefully handle function names that degenerate into function pointers - Bumped the version to 1.1.6 as we are getting closer to 2.0 TODO finish optimizing the HT links of non dual boards TODO make all Opteron board work again TODO convert all superio devices to use the new helpers TODO convert the via/epia to freebios2 conventions TODO cpu fixup/setup by cpu type git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-07*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-07fix caching problemGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-02-17removed unused set_var_mtrr() (use intel_set_var_mtrr() instead).Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1377 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-01-22cache.cGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-01-22clear IR & DR and enable FPGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-01-14*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-01-13*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-12-17clock.c need in startupGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-15setup and initialize cache correctlyGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-15cache is 32KbGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-09*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-09updated for v2Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-02*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-02Do sdram setup for fixed memory sizes. This really only works onGreg Watson
embedded boards that have fixed memory configuration. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-02trashing stackGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-02get cache setup rightGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-23fixes from SONERonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-22fixes for EPIA.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-20early mtrr for the p6Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-12naughty, naughtyGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-12first cutGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-12get_bus_freq()Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-12memory turn-onGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-11 - O2, enums, and switch statements work in romccEric Biederman
- Support for compiling romcc on non x86 platforms - new romc options -msse and -mmmx for specifying extra registers to use - Bug fixes to device the device disable/enable framework and an amd8111 implementation - Move the link specification to the chip specification instead of the path - Allow specifying devices with internal bridges. - Initial via epia support - Opteron errata fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-05size memoryGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-05use standard nameGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-05pci.S moved into arch/ppc/lib/pci_ops.cGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1190 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-26It builds!Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-26add cpufixup.oRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-26cpu fixup for p6Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-03moved init_timer() to static initializationGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-05missing file chip.hRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-04patches from Yh Lu. Tested and working on HDAMARonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-04Commits for the new config static device design, to allow more than one staticRonald G. Minnich
cpu of a certain type and to eliminate the cpu p5 cpu p6 cpu k7 nonsense in the old config files. Next step is to hook into Eric's pci device stuff. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-01- Update cpufixup so we support more than 4GB of memoryEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-30updates from YhLu, plus fixes for PPC/K8 issues.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28PPC 4XX supportGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-28corrected cpu path, added clock.oGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-24*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-23getting HDAMA to build.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-21- First pass at s2880 support.Eric Biederman
- SMP cleanups (remove SMP only use CONFIG_SMP) - Minor tweaks to romcc to keep it from taking forever compiling - failover fixes - Get a good implementation of k8_cpufixup and sizeram for the opteron git-svn-id: svn://svn.coreboot.org/coreboot/trunk@998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-19- Major cleanup of the bootpathEric Biederman
- Changes to allow more code to be compiled both ways - Working SMP support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-16- Commit a binutils safe version of reset16.incEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-14- Compile fixesEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12- Remove all of the annoying $Id stringsEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-12- Remove use of useless EXT macroEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-07-01- Code to enable and disable use of the sse and mmx registersEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-24Fixes to various config files.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-17added config and other test files.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-06-17- Minor mod to reset16.inc to work with newer binutils hopefully this works ↵Eric Biederman
with older ones... - Update apic.h to include the APIC_TASK_PRI register definition - Update mptable.c to have a reasonable board OEM and productid - Additional testfiles for romcc. - Split out auto.c and early failover.c moving their generic bits elsewere - Enable cache of the rom - Fixes to amd8111_lpc.c so that we successfully setup virtual wire mode on the ioapic git-svn-id: svn://svn.coreboot.org/coreboot/trunk@880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-05-19- Cleanups on the romcc side including a pci interface that usesEric Biederman
fewer registers, and is easier to hardcode. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-04-22- Initial checkin of the freebios2 treeEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 20:30:24 +0000