Age | Commit message (Expand) | Author |
2012-07-03 | AGESA F15 wrapper for Trinity | zbao |
2012-05-08 | Some more #if cleanup | Patrick Georgi |
2012-05-08 | Clean up #ifs | Patrick Georgi |
2012-05-01 | Move VSA support from x86 to Geode | Patrick Georgi |
2012-05-01 | Make geode_lx use the vsa from blobs repository | Patrick Georgi |
2012-04-30 | Rework ACPI CST table generation | Stefan Reinauer |
2012-04-27 | Move top level pc80 directory to drivers/ | Stefan Reinauer |
2012-04-25 | Replace cache control magic numbers with symbols | Patrick Georgi |
2012-04-22 | amd: Fix unused variable warning | Vikram Narayanan |
2012-04-16 | S3 code in coreboot public folder. | zbao |
2012-04-12 | S3 code in vendorcode folder. | zbao |
2012-04-02 | S3 code whitespaces changes. | zbao |
2012-03-16 | Rename AMD_AGESA to CPU_AMD_AGESA | Kyösti Mälkki |
2012-03-16 | Fix AMD Agesa leaking Kconfig | Kyösti Mälkki |
2012-02-20 | Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. | Marc Jones |
2012-02-17 | Remove whitespace. | Patrick Georgi |
2012-02-16 | AGESA F15: AGESA family15 model 00-0fh cpu wrapper | Kerry Sheh |
2012-02-13 | AMD Geode cpus: apply un-written naming rules | Kyösti Mälkki |
2012-01-09 | Fix Geode GX2 + LX caching for tiny bootblock. | Nils Jacobs |
2011-12-26 | Fix Fam10 MMCONF_SUPPORT_DEFAULT setting. | Marc Jones |
2011-12-13 | Use MMCONF for all AMD family 10 CPUs. | Marc Jones |
2011-11-22 | k8 raminit: add workaround for erratum #181 on non-fam-f | Florian Zumbiehl |
2011-11-01 | remove trailing whitespace | Stefan Reinauer |
2011-11-01 | Remove XIP_ROM_BASE | Patrick Georgi |
2011-10-30 | Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9 | Rudolf Marek |
2011-10-28 | Get rid of AUTO_XIP_ROM_BASE | Patrick Georgi |
2011-10-17 | Fixes several issues with amd k8 SSDT P-state generation | Oskar Enoksson |
2011-10-11 | Fixed broken MTRR for >4GB memory on AMD K8 fam 0fh rev <=E | Oskar Enoksson |
2011-09-24 | Add AMD Family 10h PH-E0 support | QingPei Wang |
2011-09-07 | AMD F14 Rev C0 update | Kerry She |
2011-08-06 | Update AMD F14 Agesa to support Rev C0 cpus | efdesign98 |
2011-07-22 | Update AMD SR5650 and SB700 | efdesign98 |
2011-07-18 | Add AMD Family 10 support to cpu folder | efdesign98 |
2011-07-13 | Make AMD SMM SMP aware | Rudolf Marek |
2011-06-28 | Addition of Family12/SB900 wrapper code | efdesign98 |
2011-06-22 | Move existing AMD Ffamily14 code to f14 folder | efdesign98 |
2011-06-22 | Rename {CPU|NB|SB}/amd/*_wrapper folders | efdesign98 |
2011-05-15 | Cosmetic cleanup. | Scott Duplichan |
2011-05-15 | Correct the number of MCA error reporting banks cleared. | Scott Duplichan |
2011-05-15 | 1) Initialize BSP fixed MTRRs to match AP fixed MTRR initialization. | Scott Duplichan |
2011-05-10 | Change read_option() to a macro that wraps some API uglyness | Patrick Georgi |
2011-04-21 | more ifdef -> if fixes. | Stefan Reinauer |
2011-04-21 | more ifdef -> if fixes | Stefan Reinauer |
2011-04-14 | Use symbolic names for some MTRR bits instead of numbers in CAR code | Stefan Reinauer |
2011-04-11 | Unify use of post_code | Alexandru Gagniuc |
2011-03-28 | Add AMD C32 support. | Zheng Bao |
2011-03-17 | Fix breaking the build after removing files in tthe previous checkin. | Marc Jones |
2011-03-04 | Add P-states for select Socket 754 processors. | Jonathan Kollasch |
2011-03-03 | Correct off-by-one problem in AMD pre-rev-F model-F PowerNow code. | Jonathan Kollasch |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-28 | Prepare for next patches (Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-27 | Prepare for next patches (Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-27 | Prepare for next patches (Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-27 | Prepare for next patches (Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-27 | Prepare for next patches (Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-27 | Prepare for next patches (Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-27 | Prepare for next patches (Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-27 | Prepare for next patches (Improving BKDG implementation of P-states, | Xavi Drudis Ferran |
2011-02-26 | Make AMD Fam10h CPU microcode updates optional in Expert mode | Xavi Drudis Ferran |
2011-02-26 | It adds support for automatic PSS object generation for AMD pre fam Fh CPU. T... | Rudolf Marek |
2011-02-24 | Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS | Josef Kellermann |
2011-02-14 | Add AMD cpu wrapper code. Patch 4 of 8. | Frank Vibrans |
2011-02-10 | According to AMD documentation, cache type WP should be used for | Scott Duplichan |
2011-02-10 | Implemented workaround for erratum 169, obsoleting erratum 131. | Alexandru Gagniuc |
2011-02-10 | Fix a potential system hang by handling AMD Model F Erratum 89 | Josef Kellermann |
2011-01-19 | Revert r5902 to make code more readable again. At least three people like to | Stefan Reinauer |
2011-01-12 | drop unused files | Stefan Reinauer |
2011-01-01 | Add AMD SB800 southbridge CIMx code. | Kerry She |
2010-12-30 | Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code | Nils Jacobs |
2010-12-26 | Remove dead and unused Geode GX2 code | Nils Jacobs |
2010-12-26 | Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names | Nils Jacobs |
2010-12-26 | Clean up Geode GX2 comments, whitespace and coding style. Trivial. | Nils Jacobs |
2010-12-18 | SMM on AMD K8 Part 2/2 | Rudolf Marek |
2010-12-18 | SMM for AMD K8 Part 1/2 | Stefan Reinauer |
2010-12-08 | Move "select CACHE_AS_RAM" lines from boards into CPU socket. | Uwe Hermann |
2010-11-22 | 1) wraps the s3 parts of chipset code/memory init code with if CONFIG_HAVE_AC... | Rudolf Marek |
2010-11-18 | Eliminate SET_NB_CFG_54 option. There was no board that | Patrick Georgi |
2010-11-16 | Move the SET_FIDVID* family of configuration options to Kconfig and | Patrick Georgi |
2010-11-13 | MTRR related improvements for AMD family 10h and family 0Fh systems | Scott Duplichan |
2010-11-09 | This fixes a FIXME in src/cpu/amd/mtrr/amd_mtrr.c and shuts up the | Tobias Diedrich |
2010-11-03 | Clean up some more comments and white space in model_gx2/cpureginit.c. | Nils Jacobs |
2010-10-31 | Fix AMD family 10h engineering sample is reported as 'thermal test kit'. | Scott Duplichan |
2010-10-26 | reg is only used inside the #if clause, so declare it there. trivial. | Patrick Georgi |
2010-10-19 | For AMD family 10h processors, msr c0010058 is always programmed | Scott Duplichan |
2010-10-19 | Modernize socket_754 Kconfig with CAR and address bits information. | Jonathan Kollasch |
2010-10-19 | Revision 5966 changed the end of line style of the 3 modified files. This cha... | Scott Duplichan |