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AgeCommit message (Collapse)Author
2006-05-06Use a real variable to configure rom base for vsa ...Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04fix the treeStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04core range and set_init_ram_accessYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04rm unused fileYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-04merge zrom to rom_stream and print olen ilenYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-03oops! Slap me on the head for this one. Quick fix for ward untilStefan Reinauer
YhLu's suggestions are all there.. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-02add automatic payload compression method to LinuxBIOSStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-02Fall back to pre-broken settings and setup for GX2. Ronald G. Minnich
We lost a few things, but this is still worth it. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-27code cleanup, comments addedLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-20boot to kernelLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-13add SystemPreInit() and supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-13minor modificationLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-10add cpureginit to romcc code.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-10clean up gx2def.h a bit. Ronald G. Minnich
Add cpureginit.c added called to cpureginit to model_gx2_init.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-06add bug support for 2.1Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-06reformat Li-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-06more fix for vsm, not working yetLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03did I commit the last change?Li-Ta Lo
try to fix 0x10000026 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03new cache_as_ram support Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-22added this fileRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-21add vsm supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-21cpubug is fine. Ronald G. Minnich
adding vsm support now. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-20added definitions. added cpubug support. added object. Commented out Ronald G. Minnich
msr set in northbridge that conflicted with the cpubug support. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-19small cleanup attempt in sc520 code. there needs to be some major springStefan Reinauer
cleaning git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-17- sc520 updates. move PAR setup to mainboard auto.cStefan Reinauer
- some ts5300 code. Let's push this upstream for now. - fix a typo in device.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-17fix mmcrval, small cosmetics to raminitStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-02-28remove unused GX1 asm codeLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-02-27more GX2 commitLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-28renameRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-01-27adding preliminary, and almost certainly wrong, rumba support. Ronald G. Minnich
This is just a skeleton, basically, and will most likely not even compile yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-14indirect jmp with *Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-14from issue 53: don't set TOM2 if 4G less mem installed, opt for init_eccYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-14support HDT disassembly when cache as ram auto stageYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-14issue 51 and 52: set mtrr for ap before stop it, and _RAMBASE above 1MYinghai Lu
support and pgtbl after 1M support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-09make clear_1m_ram.c to support gcc 3 and gcc4Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2141 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-07use CONFIG_LB_MEM_TOPK instead 1M hardcode from issue 50Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-021201_ht_bus0_dev0_fidvid_core.diffStefan Reinauer
https://openbios.org/roundup/linuxbios/issue41 Lord have mercy upon us. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-01Applying YhLu's patch from issue 37.Stefan Reinauer
a. apic id liftting to way that kernel like and let bsp to stay with 0 b. hw memhole: solve if hole_startk == some node basek This, together with the previous one will break most of the tree, but Yinghai Lu is really good at fixing things, so... git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-01Applying 11_26_car_tyan.diff from Yinghai Lu.Stefan Reinauer
NOTE: This will break the tree so it can be fixed up later git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-26- Apply 11_24_a_s1_core.diff fromStefan Reinauer
https://openbios.org/roundup/linuxbios/issue24 - fix up for via epia-m git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-23remove rev f ifdefRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-23CAR patch from YH LURonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-23Split out microcode updates.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-23missed these.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-23issue 25, various AMD patchesRonald G. Minnich
Signed-off-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-21This was posted on issue tracker and approve by ron minnichRonald G. Minnich
Signed-off-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-25- See Issue Tracker id-4 "lnxi-patch-4" Jason Schildt
- In addition: modified apic_id lifting to always lift all CPUs. This may cause problems with older kernels. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-19adding support for dell 1850Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-26comments mods. THings are working better, so I'm less unhappy withRonald G. Minnich
this part :-) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2049 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-23sc520 support -- ethernet worksRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12sc520 now builds fine. On to testing.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12moved to include/cpu/amd/sc520.hRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12updated to new svn repoRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-08-10Undoing all HDAMA commits from LNXI from r2005->2003Jason Schildt
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-08-09- Merge from linuxbios-lnxi (Linux Networx repository) up to public tree.Jason Schildt
- Special version for HDAMA rev G with 33Mhz test and reboot out. - Support for CPU rev E, dual core, memory hoisting, - corrected an SST flashing problem. Kernel bug work around (NUMA) - added a Kernel bug work around for assigning CPU's to memory. r2@gog: svnadmin | 2005-08-03 08:47:54 -0600 Create local LNXI branch r1110@gog: jschildt | 2005-08-09 10:35:51 -0600 - Merge from Tom Zimmerman's additions to the hdama code for dual core and 33Mhz fix. r1111@gog: jschildt | 2005-08-09 11:07:11 -0600 Stable Release tag for HDAMA-1.1.8.10 and HDAMA-1.1.8.10LANL r1112@gog: jschildt | 2005-08-09 15:09:32 -0600 - temporarily removing hdama tag to update to public repository. Will reset tag after update. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08eric patchYinghai Lu
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-54arch import user (historical)
Creator: Ronald G. Minnich <rminnich@lanl.gov> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-50arch import user (historical)
Creator: Ronald G. Minnich <rminnich@lanl.gov> This now boots to the point of passing the memory test in auto.c. But: we still don't have it working after the "Jumping to LinuxBIOS" step git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-49arch import user (historical)
Creator: Ronald G. Minnich <rminnich@lanl.gov> this is a version that does not fail, but memory is still not up git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-48arch import user (historical)
Creator: Ronald G. Minnich <rminnich@lanl.gov> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-47arch import user (historical)
Creator: Ronald G. Minnich <rminnich@lanl.gov> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-46arch import user (historical)
Creator: Ronald G. Minnich <rminnich@lanl.gov> sc520 fails after NOP git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-45arch import user (historical)
Creator: Ronald G. Minnich <rminnich@lanl.gov> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-43arch import user (historical)
Creator: Li-Ta Lo <ollie@lanl.gov> Cosmetic Cosmetic code reformatting and message output git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-38arch import user (historical)
Creator: Li-Ta Lo <ollie@lanl.gov> emulator update x96emu update from Paulo git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-36arch import user (historical)
Creator: Li-Ta Lo <ollie@lanl.gov> emulator update Correction to the reduce emulator from Paulo git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-29arch import user (historical)
Creator: Hamish Guthrie <hamish@prodigi.ch> Added NSC pc97317 super-io and added fill character option to config/Options.lb to speed up flash programming git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-27arch import user (historical)
Creator: Hamish Guthrie <hamish@prodigi.ch> Added GX1 cpu files git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-23arch import user (historical)
Creator: Ronald G. Minnich <rminnich@lanl.gov> add in stepan's raminit code for the sc520 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-19arch import user (historical)
Creator: Ronald G. Minnich <rminnich@lanl.gov> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1935 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-16arch import user (historical)
Creator: Ronald G. Minnich <rminnich@lanl.gov> add cpu directory and files for sc520 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1934 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-19minor reformatLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-17fix reboot brokenYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-15can not enable cache for ram in auto.cYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1877 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-14amd version mtrr earlyYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1873 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-13lift apic id fixYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-10added PCI expansion ROM support,Li-Ta Lo
works for some ATI and Nvidia AGP cards now. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1851 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-05enable apic ext idYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-11mpspec.h: Tweak the write_smp_table macro so that it is safe if passed a ↵Eric Biederman
complex expression. crt0.S.lb: Modified so that it is safe to include console.inc console.c: Added print_debug_ and frieds which are non inline variants of the normal console functions div64.h: Only include limits.h if ULONG_MAX is not defined and define ULONG_MAX on ppc socket_754/Config.lb Conditionally set config chip.h socket_940.c We don't need and #if CONFIG_CHIP_NAME we won't be linked in if there are no references. slot_2/chip.h: The operations struct need to be spelled cpu_intelt_slot_2_ops slot_2/slot2.c: The same spelling fix socket_mPGA603/chip.h: again socket_mPGA603/socket_mPGA603_400Mhz.c: and again socket_mPGA604_533Mhz/Config.lb: Conditionally defing CONFIG_CHIP_NAME socket_mPGA604_800Mhz/chip.h: Another spelling fix socket_mPGA604_800Mhz.c and again via/model_centaur/model_centaur_init.c: It's not an intel CPU so don't worry about Intel microcode uptdates earlymtrr.c: Remove work around for older versions of romcc pci_ids.h: More ids. malloc.c: We don't need string.h any longer uart8250.c: Be consistent when delcaring functions static inline arima/hdama/mptable.c: Cleanup to be a little more consistent amdk8/coherent_ht.c: - Talk about nodes not cpus (In preparation for dual cores) - Remove clear_temp_row (as it is no longer needed) - Demoted the failure messages to spew. - Modified to gracefully handle failure (It should work now if cpus are removed) - Handle the non-SMP case in verify_mp_capabilities - Add clear_dead_routes which replaces clear_temp_row and does more - Reorganize setup_coherent_ht_domain to cleanly handle failure. - incoherent_ht.c: Clean up the indenation a little. i8259.c: remove blank lines at the start of the file. keyboard.c: Make pc_keyboard_init static ramtest.c: Add a print out limiter, and cleanup the printout a little. amd8111/Config.lb: Mention amd8111_smbus.c amd8111_usb.c: Call the structure usb_ops not smbus_ops. NSC/pc97307/chip.h: Fix spelling issue pc97307/superio.c: Use &ops no &pnp_ops. w83627hf/suerio.c: ditto w83627thf/suerio.c: ditto buildrom.c: Use braces around the body of a for loop. It's more maintainable. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05CONFIG_CHIP_NAME to control config chip.h without .nameYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04- Update abuild.sh so it will rebuild successfull buildsEric Biederman
- Move pci_set_method out of hardwaremain.c - Re-add debugging name field but only include the CONFIG_CHIP_NAME is enabled. All instances are now wrapped in CHIP_NAME - Many minor cleanups so most ports build. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-31fix soloStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-30- To reduce confuse rename the parts of linuxbios bios that run fromEric Biederman
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload... - Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86 - ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB. - Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work. - Start using romcc's built in preprocessor (This will simplify header compiler checks) - Add helper functions for examining all of the resources - Remove debug strings from chip.h - Add llshell to src/arch/i386/llshell (Sometime later I can try it...) - Add the ability to catch exceptions on x86 - Add gdb_stub support to x86 - Removed old cpu options - Added an option so we can detect movnti support - Remove some duplicate definitions from pci_ids.h - Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic - Minor romcc bug fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27sizeram removal/conversion.Eric Biederman
- mem.h and sizeram.h and all includes killed because the are no longer needed. - linuxbios_table.c updated to directly look at the device tree for occupied memory areas. - first very incomplete stab a converting the ppc code to work with the dynamic device tree - Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources). - First stab at Pentium-M support - add part/init_timer.h making init_timer conditional until there is a better way of handling it. - Converted all of the x86 sizeram to northbridge set_resources functions. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22- Better memory I/O space distinguishing in amd_mtrr.cEric Biederman
This is way to much code duplication but for now things work. - Fix the typo in amd8111_lpc.c - Remove an unused macro, use continue instead of break in mtrr.c git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- Explicitly disable the fixed dram extensions bits.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- We already know the cache is disabled so don't bother disabling it.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19- add support for socket 754Stefan Reinauer
- fix configuration creation for amd solo (doesn't compile yet) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- First stab at running linuxbios without the old static device tree.Eric Biederman
Things are close but not quite there yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- Add new cvs code to cvsEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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