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path: root/src/config/Options.lb
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2009-04-23This patch hooks up git mirrored svn revisions and adds someCarl-Daniel Hailfinger
error checking to the svnrevision call. If a .svn directory exists in the top level directory and the svnversion utility is available, we use svnversion. Otherwise, if a .git directory exists in the top level directory and the git utility is available, we use git log. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22Sometimes when we debug the code, we need to know which version we areZheng Bao
working on. Add the svn revision to the coreboot version string. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4191 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-14v2/src romfs->cbfs renamePeter Stuge
This also has the config tool changes in v2/util. Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13Following patch adds necessary hooks and as well the compile time checks forRudolf Marek
ACPI suspend/resume. The memory cleared now is just the coreboot memory not the low memory. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01Drop CONFIG_CHIP_NAME. Those config statements in Config.lb shouldStefan Reinauer
be used unconditionally, and the names don't hurt. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-31Add the CONFIG_ROMS config variable. Ronald G. Minnich
Tested under abuild, causes no trouble. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-19fix the following warning on all boards that don't have PIRQ_ROUTE enabledStefan Reinauer
In file included from coreboot-v2-4017//src/arch/i386/boot/pirq_routing.c:2: coreboot-v2-4017/src/arch/i386/include/arch/pirq_routing.h:45:5: warning: "PIRQ_ROUTE" is not defined coreboot-v2-4017//src/arch/i386/boot/pirq_routing.c:103:6: warning: "PIRQ_ROUTE" is not defined Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4019 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-18add YABEL flag to options to decide wether access to devices other than the ↵Pattrick Hueper
one yabel is running for is possible Signed-off-by: Pattrick Hueper <phueper@hueper.net> Tested and Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-14add YABEL Debug Flags to OptionsPattrick Hueper
Signed-off-by: Pattrick Hueper <phueper@hueper.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13This, ladies and gentlement, is commit #4000.Stefan Reinauer
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few include files and missing prototypes. Also, fix up the Config-abuild.lb files to properly work for cross compiling. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06Fix mmconf (PCIe memory mapped config space access) support in v2. It wasStefan Reinauer
horribly broken and thus never used by any platform. This needs to get straightened out so current chipsets drivers can use the full feature set. Create wrapper functions similar to the io pci config space ones. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3981 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-01Some changes required to get yabel working on v2 (and they generally makeStefan Reinauer
sense, too). Have one u64 instead of three. In order to use the old bios emulator, you have to do nothing. (Default, if CONFIG_PCI_ROM_RUN is enabled) In order to use yabel in your target, you need to add the following lines to your config: uses CONFIG_PCI_OPTION_ROM_RUN_YABEL default CONFIG_PCI_OPTION_ROM_RUN_YABEL=1 In order to use vm86 in your target, you need to add the following lines to your config: uses CONFIG_PCI_OPTION_ROM_RUN_VM86 default CONFIG_PCI_OPTION_ROM_RUN_VM86=1 Note: vm86 only works on platforms with _RAMBASE in the lower megabyte. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-27Generic approach of putting BIOS tables at the end of memoryStefan Reinauer
(in addition to their low locations) This adds the kontron 986LCD-M and the i945 as a sample. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-21Now that x86emu debugging is actually working, it should be switched off perStefan Reinauer
default because it adds quite noticably to the image size. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20some brown paperbag please. fix build.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20This patch makes the recently added assembler debug optional, as it mayStefan Reinauer
cause problems with certain toolchains. This patch will also safe some hard disk space for those of us working on laptops or netbooks with always too small disks. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-19ouch. never do last minute changes. :-(Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-13Move mainboard specific changes to the coreboot memory table into theStefan Reinauer
mainboard specific code. (And add a hook to allow other mainboards do a similar thing if required) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11[PATCH] coreboot-v2: Add multiboot supportRobert Millan
Signed-off-by: Robert Millan <rmh@aybabtu.com> Acked-by: Jordan Crouse <jordan@cosmicpneguin.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for the Intel ICH7 southbridge.Stefan Reinauer
This includes an early SMI handler. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Changes required to the device allocator:Stefan Reinauer
- leave a hole for mmapped PCIe config space if CONFIG_PCIE_CONFIGSPACE_HOLE is set. - Mask moving bits to 32bit when resources are not supposed above 4G. Linux does not like this, even though the resource is disabled. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-22Patch for AMD RS690 chipset.Michael Xie
All the PCIe slots are enabled in this patch except power management. Signed-off-by: Michael Xie <Michael.Xie@amd.com> Reviewed-by: Marc Jones <marc.jones@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-02Go back to SIPI WAIT state for those CPUS defining the newly introducedStefan Reinauer
CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with multiple cores. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23Fix r3434 check-in. Added missing end to Options.lb. Not entirely sure how itMarc Jones
went missing.... Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23Update to the latest AMD Fam10 microcode patches.Marc Jones
Add platform option for patch file name. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-29Now coreboot performs IRQ routing for some boards.Nikolay Petukhov
You can see this by executing commands like this: grep -r pci_assign_irqs coreboot/src/* This basically AMD/LX based boards: pcengines/alix1c, digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800. Also for AMD/GX1 based boards need a patch [http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch] for the right IRQ setup. AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320, bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p. I have two ideas. 1. Delete duplicate code from AMD/LX based boards. 2. Add IRQ routing for AMD/GX1 boards in coreboot. The pirq.patch for IRQ routing logically consist from of two parts: First part of pirq.patch independent from type chipsets and assign IRQ for ever PCI device. It part based on AMD/LX write_pirq_routing_table() function. Second part of pirq.patch depends of type chipset and set PIRQx lines in interrupt router. This part supports only CS5530/5536 interrupt routers. IRQ routing functionality is included through PIRQ_ROUTE in Config.lb. Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on TeleVideo TC7020, see http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html. Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-02-25This patch adds automatic fan control for the CPU fan on the m57sliRonald Hoogenboom
board. This is done via the ec_init routine in a source file in the mainboard/gigabyte/m57sli directory. A Config variable 'HAVE_FANCTL' has been added to notify superio.c to get the ec_init externally. I (Ward) have tested this on the PLCC and the SOIC/SPI version of this board. It works. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Rename almost all occurences of LinuxBIOS to coreboot. Stefan Reinauer
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-06Since a VGA console and the need to run any option ROMs areTorsten Duwe
rather independent, lift the implicit (broken) assumption that CONSOLE_VGA would also run the ROMs, and transfer it to a new config option VGA_ROM_RUN. This change is minimally intrusive, because all board configs that previously assumed CONSOLE_VGA would also run the ROMs didn't compile, they had to also specify PCI_ROM_RUN. Based on patches by Ron Minnich (fix the compile) and Luc Verhaegen (separate ROM_RUN from VGA console). Signed-off-by: Torsten Duwe <duwe@lst.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Luc Verhaegen <libv@skynet.be> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-12-19Initial AMD Barcelona support for rev Bx.Marc Jones
These are the core files for HyperTransport, DDR2 Memory, and multi-core initialization. Signed-off-by: Marc Jones <marc.jones@amd.com> Reviewed-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <myles@pel.cs.byu.edu> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-07Fix some issues with spaces in the code and Doxygen style documentation.Juergen Beisert
Painting the splash graphic is now ifdef'ed. Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-05This patch will add support for the Geode GX1/CS5530 VGA feature. It's ableJuergen Beisert
to set up one of five screen resolutions (sorry no autodetection at runtime, resolution is selected at buildtime) and displays a graphic in the right bottom corner (splash screen). Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-02-28This is (most of) the usb2 debug console code ripped out of Yinghai Lu
Uwe's version of yh_rest_of_patch.patch (13.02.07 - [PATCH] Rest of huge MCP55 patch). I dropped a lot of stuff, like broken indenting, removed copyright messages, and this printk_ram_* stuff (what the heck is this supposed to be) This codebase is really a mess. Further tarball contributions without a _CLEANED UP_ patch will be denied, especially if they are not from an up to date svn tree. Signed-off-by: Yinghai Lu <yinghai.lu@amd.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15Apply linuxbios-rename-other-payload-options.patchEd Swierk
(Patch 2, refs #14) Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-15Apply linuxbios-rename-compressed-payload-options.patch, refs #14Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-07Add serial stream payload support from Ed Swierk <eswierk@arastra.com>Stefan Reinauer
X-Signed-Off-By: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2447 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04CONFIG_USE_PRINTK_IN_CAR and ht chain id for HTX support inYinghai Lu
serengeti_cheeatah git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-04AMD Rev F supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-20Lots of lx fixes. CLeanup mainly. THings now buildRonald G. Minnich
Signed-off-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-14additions and mods for lzma. Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger Signed-off-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-09-08hurry hurry before we might start 3.0 ;-)Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-03slightly changed C.D. Hailfinger's precompressed rom stream patchStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-18add option to decide to use onboard vga or addon card.Yinghai Lu
CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-02add automatic payload compression method to LinuxBIOSStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-23Adds a CONFIG_MAX_PCI_BUSES to pci_locate_device()Richard Smith
Default is 255. This allows mainboard configs for working across various groups of boards that differ a device that may not loaded. If you search for a device that is not loaded and max buses is 255 then there can be up to a 8 second delay to search the entire PCI space. Board configs that know thier max bus can limit this search space. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-04-03new cache_as_ram support Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-03-19small cleanup attempt in sc520 code. there needs to be some major springStefan Reinauer
cleaning git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-02-19gcc 4.1 fixes.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2177 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-06use hcdn to simplify the mptable.c and irqtable.c --- patch fro issueYinghai Lu
48 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-04implement io based udelay function for all mainboards that lack an apicStefan Reinauer
timer (or just failed otherwise due to missing udelay) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2131 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-021201_ht_bus0_dev0_fidvid_core.diffStefan Reinauer
https://openbios.org/roundup/linuxbios/issue41 Lord have mercy upon us. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-12-01Applying YhLu's patch from issue 37.Stefan Reinauer
a. apic id liftting to way that kernel like and let bsp to stay with 0 b. hw memhole: solve if hole_startk == some node basek This, together with the previous one will break most of the tree, but Yinghai Lu is really good at fixing things, so... git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-11-26- Apply 11_24_a_s1_core.diff fromStefan Reinauer
https://openbios.org/roundup/linuxbios/issue24 - fix up for via epia-m git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-12Attempt to make comments more descriptive.Steven J. Magnani
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-08-10remove obsolete VGA support for EPIALi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08eric patchYinghai Lu
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-30arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> Nvidia Ck804 support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-29arch import user (historical)
Creator: Hamish Guthrie <hamish@prodigi.ch> Added NSC pc97317 super-io and added fill character option to config/Options.lb to speed up flash programming git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-2arch import user (historical)
Creator: Eric Biederman <ebiederman@lnxi.com> Bump the version number with the switch to arch I need an arch test case so bumped the version number. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-14CONFIG_PCI_ROM_RUNYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04- Update abuild.sh so it will rebuild successfull buildsEric Biederman
- Move pci_set_method out of hardwaremain.c - Re-add debugging name field but only include the CONFIG_CHIP_NAME is enabled. All instances are now wrapped in CHIP_NAME - Many minor cleanups so most ports build. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-30- To reduce confuse rename the parts of linuxbios bios that run fromEric Biederman
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload... - Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86 - ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB. - Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work. - Start using romcc's built in preprocessor (This will simplify header compiler checks) - Add helper functions for examining all of the resources - Remove debug strings from chip.h - Add llshell to src/arch/i386/llshell (Sometime later I can try it...) - Add the ability to catch exceptions on x86 - Add gdb_stub support to x86 - Removed old cpu options - Added an option so we can detect movnti support - Remove some duplicate definitions from pci_ids.h - Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic - Minor romcc bug fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27sizeram removal/conversion.Eric Biederman
- mem.h and sizeram.h and all includes killed because the are no longer needed. - linuxbios_table.c updated to directly look at the device tree for occupied memory areas. - first very incomplete stab a converting the ppc code to work with the dynamic device tree - Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources). - First stab at Pentium-M support - add part/init_timer.h making init_timer conditional until there is a better way of handling it. - Converted all of the x86 sizeram to northbridge set_resources functions. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- Bump the LinuxBIOS major versionEric Biederman
- Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14- First pass through with with device tree enhancement merge. Most of the ↵Eric Biederman
mechanisms should be in place but don't expect anything to quite work yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06epia-m supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-27fix build. :( sorry, forgot to commit this one.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-05-10fixed minor bug in APG bridge code. Use AGP_APERTURE_SIZE instead of ↵Li-Ta Lo
IOMMU_APERTURE_SIZE git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-04-24Add btext console (from YhLu)Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-25breaks PPCGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-24Further trimming freebios2 towards code reuse.Stefan Reinauer
Unified AMD K8 reset function that can be customized via mainboard Config.lb git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-23Doxidization, reformatLi-Ta Lo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-23tighten up option exportingGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-19serial post returns!Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-13added fat supportGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-13ide supportGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-13filesystem supportGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-03-11- Moved hlt() to it's own header.Eric Biederman
- Reworked pnp superio device support. Now complete superio support is less than 100 lines. - Added support for hard coding resource assignments in Config.lb - Minor bug fixes to romcc - Initial support for catching the x86 processor BIST error codes. I've only seen this trigger once in production during a very suspcious reset but... - added raminit_test to test the code paths in raminit.c for the Opteron - Removed the IORESOURCE_SET bit and added IORESOURCE_ASSIGNED and IORESOURCE_STORED so we can tell what we have really done. - Added generic AGP/IOMMU setting code to x86 - Added an implementation of memmove and removed reserved identifiers from memcpy - Added minimal support for booting on pre b3 stepping K8 cores - Moved the checksum on amd8111 boards because our default location was on top of extended RTC registers - On the Hdama added support for enabling i2c hub so we can get at the temperature sensors. Not that i2c bus was implemented well enough to make that useful. - Redid the Opteron port so we should only need one reset and most of memory initialization is done in cpu_fixup. This is much, much faster. - Attempted to make the VGA IO region assigment work. The code seems to work now... - Redid the error handling in amdk8/raminit.c to distinguish between a bad value and a smbus error, and moved memory clearing out to cpufixup. - Removed CONFIG_KEYBOARD as it was useless. See pc87360/superio.c for how to setup a legacy keyboard properly. - Reworked the register values for standard hardware, moving the defintions from chip.h into the headers of the initialization routines. This is much saner and is actually implemented. - Made the hdama port an under clockers BIOS. I debuged so many interesting problems. - On amd8111_lpc added setup of architectural/legacy hardware - Enabled PCI error reporting as much as possible. - Enhanded build_opt_tbl to generate a header of the cmos option locations so that romcc compiled code can query the cmos options. - In romcc gracefully handle function names that degenerate into function pointers - Bumped the version to 1.1.6 as we are getting closer to 2.0 TODO finish optimizing the HT links of non dual boards TODO make all Opteron board work again TODO convert all superio devices to use the new helpers TODO convert the via/epia to freebios2 conventions TODO cpu fixup/setup by cpu type git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-01-28please forgive me... ;)Stefan Reinauer
* initial acpi support code * fix header git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1358 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-01-22memory mapped I/OGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-01-14allow TTYS0_DIV to be set explicitlyGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-01-13Options for briQGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-19add FAKE_SPDROM option to fake spd on machines that don't have one.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-15options for better control of rom layoutGreg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-09*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-11-05*** empty log message ***Greg Watson
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-11 - O2, enums, and switch statements work in romccEric Biederman
- Support for compiling romcc on non x86 platforms - new romc options -msse and -mmmx for specifying extra registers to use - Bug fixes to device the device disable/enable framework and an amd8111 implementation - Move the link specification to the chip specification instead of the path - Allow specifying devices with internal bridges. - Initial via epia support - Opteron errata fixes git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-07remove SMBUS_MEM_DEVICE_[START|END] traces from code.Stefan Reinauer
add 8mbit example config for amd solo. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-01default USE_FALLBACK_IMAGE to 0Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-10-01vga supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-26added CONFIG_KEYBOARD, default 0Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1145 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-25ROM_SIZE has no default now.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-02- 1.1.4Eric Biederman
Major restructuring of hypertransport handling. Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically Updates to hard_reset handling when resetting because of the need to change hypertransport link speeds and widths. (a) No longer assume the boot is good just because we get to a hard reset point. (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the boot counter. Updates to arima/hdama mptable so it tracks the new bus numbers git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-02- Major update of the dynamic device tree so it can handleEric Biederman
* subtractive resources * merging with the static device tree * more device types than just pci - The piece to watch out for is the new enable_resources method that was needed in all of the drivers git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-01- Update the version number to 1.1.2 and update the NEWS fileEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-09-01- Updates to config.g so that it works more reliably and has initial supportEric Biederman
for paths - Renamed some configuration variables SMP -> CONFIG_SMP MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS - Removed some dead configuration variables MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS SMP -> CONFIG_SMP FINAL_MAINBOARD_FIXUP SIO_BASE SIO_SYSTEM_CLK_INPUT NO_KEYBOARD USE_NORMAL_IMAGE SERIAL_CONSOLE USE_ELF_BOOT ENABLE_FIXED_AND_VARIABLE_MTRRS START_CPU_SEG DISABLE_WATCHDOG ENABLE_IOMMU AMD8111_DEV - Removed some assembly files that are no longer needed killed src/southbridge/amd/amd8111/smbus.inc killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc killed src/ram/ramtest.inc - Updates to config.g so that it works more reliably and has initial support for paths - Renamed some configuration variables SMP -> CONFIG_SMP MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS - Removed some dead configuration variables MAX_CPUS -> CONFIG_MAX_CPUS MAX_PHYSICAL_CPUS -> CONFIG_MAX_PHYSICAL_CPUS SMP -> CONFIG_SMP FINAL_MAINBOARD_FIXUP SIO_BASE SIO_SYSTEM_CLK_INPUT NO_KEYBOARD USE_NORMAL_IMAGE SERIAL_CONSOLE USE_ELF_BOOT ENABLE_FIXED_AND_VARIABLE_MTRRS START_CPU_SEG DISABLE_WATCHDOG ENABLE_IOMMU AMD8111_DEV - Removed some assembly files that are no longer needed killed src/southbridge/amd/amd8111/smbus.inc killed src/southbrideg/amd/amd8111/cmos_boot_failover.inc killed src/ram/ramtest.inc killed src/sdram/generic_dump_spd.inc killed src/sdram/generic_dump_spd.inc - Updated the arima/hdama to build with the new configuration system - Updated config.g to list all of the variables with make echo git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-28cleaning out motherboard specific changes from the generic directories.Stefan Reinauer
Moving tyan resource map to tyan directory. Making IOMMU for hammer choosable via ENABLE_IOMMU git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2003-08-06add XIP_ROM_[BASE|SIZE] to newconfig for quicker bootupStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 23:11:07 +0000