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Since PSCI dynamically determines which EL to transition
to based on SCR_EL3 there's no need to provide that
information.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted into kernel with MP.
Change-Id: Ia59bc8116ec4ae9bde2e6cad1861f76c14f7d495
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8bc5f7c8a114568ede98478c2fbea2f8b7d97f0c
Original-Change-Id: I8783b6315dca01464e14c9d2b20d009cf0beeb67
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218924
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9098
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The PSCI functionality initially includes CPU_ON and CPU_OFF
functions. Upon entering secmon if the parameters are non-NULL
then a PSCI CPU_ON action is done for the current CPU.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Booted kernel with PSCI support. Brought up all CPUs in kernel
using PSCI. Turned CPUs on and off.
Change-Id: I256fa45a1c9889ff9d7990eb1898df1ec241c117
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 689ba03e313e7e52e9b74aa774897b55cbd52748
Original-Change-Id: I943826b7dbcc8e3f6c8c4b66344af8fac12ba94e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218923
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9097
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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If an exception is taken that the secmon won't return
to, there needs to be way to reset that cpu's state
w.r.t. stack usage. Therefore, provide secmon_trampoline
which will reinitialize the exception stack and SP_EL0
and start executing with SP_EL0 like the initial state
of the secmon entry.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel. Also tested when PSCI
is employed in the kernel.
Change-Id: Ie9f5bbe715dcbcf8b67ea40f9a3a5088ac7aa2ad
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1f546ee3e9eca93baaa1ae0437351205bf548a5
Original-Change-Id: Ia3da75e1fa0251c8ea30eb0b0523c8a51c03b917
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218922
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9096
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Two things:
1. Not returning once setting the return state.
2. mempcy(x, y, ARRAY_SIZE(x)) is not memcpy(x, y, sizeof(x))
With these 2 changes arguments and results are being processed
correctly.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Built and brought up SMP using PSCI.
Change-Id: If76a207e1a434a4c08faaa535f069d7386481e9e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42d540afd4e6ea2b34cf3632ad2c683fcaa063c8
Original-Change-Id: I656b9c11e3bc07cc1664789a600eb88afd639f93
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218847
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9094
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to process PSCI commands SMC instructions need to be
serviced. Provide a simple way for users of SMC to register their
handlers by function.
The SMC layer hooks into the exception processing, however it only
processes AARCH64 SMC calls. All others are ignored.
BUG=chrome-os-partner:32112
BRANCH=None
TEST=Added nop smc call to depthcharge. SMC handled and continue booting
to kernel.
Change-Id: I378f13c29220ff9f37040f094bf9cfb69259af0c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 76d2febc50397348b68d38532b8f37e2b3cf6a30
Original-Change-Id: Ieaa29fa883b9f9d55fc62ba92a1d45452296efa4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218846
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9092
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The exception vectors were not reinitialized in secmon yet.
Add that as well as the split BSP vs non-BSP path. In doing
so bring in the cpu.c semantics for determining bsp at runtime.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel. Also noted only one CPU
printing messages.
Change-Id: I26a7f9446f4422d2203b1d520e69f8dee9450b59
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 67f79c61c902ee614f029047255b4be35112cd32
Original-Change-Id: Ide66f13c24f5798d5983c481ce616ae2800d558c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218845
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9091
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It's helpful to differentiate the startup paths for
the BSP and the non-BSP. Therefore have c_entry
be an 2 element array of function pointers. The
non-BSP paths have an entry point one instruction after
stage/module entry.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: I40bb40462906f1b1eaf2db8584985095e8ac0bae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce10f954041b3fd581ad8a3d82dee567b68637fe
Original-Change-Id: Ia573b1095dca5f69e371bf1ddf6b6df72fa3b52e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218844
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9090
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The cpu.c contains some helpful construts as well as ramstage
devicetree handling. Split the 2 pieces so that cpu.c can be
reused in secmon.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted.
Change-Id: Iec0f8462411897a255f7aa289191ce6761e08bb0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4f30f1186950424b65df6858965a09ca51637e4f
Original-Change-Id: Ie87bd35bf1ccd777331250dcdaae07dab82d3d18
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218842
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9089
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to build upon the arm64 exception handlers need
to be registered. This provides very basic support to
register a handler for a specific exception vector.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Built and booted into kernel.
Change-Id: If046f0736765a2efeb23201c1d2d1f7f7db47dd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a82e5e8d5900ebef16abdb68701be6beeb9ca13a
Original-Change-Id: I0f68a48101ff48d582f5422871b9e7e5164357e4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218650
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9088
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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There was a hacky and one-off spin table support in tegra132.
Make this support generic for all arm64 chips.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Ran with and without secure monitor booting smp into the kernel.
Change-Id: I3425ab0c30983d4c74d0aa465dda38bb2c91c83b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 024dc3f3e5262433a56ed14934db837b5feb1748
Original-Change-Id: If12083a9afc3b2be663d36cfeed10f9b74bae3c8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218654
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9084
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It's helpful to know if the current running CPU
is the BSP. Therefore, provide that semantic.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: I18cb8ab5149c3337e22b1f6046b1af266be7e47c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b390dc70b658c207cd3b64408713ec4cddab3172
Original-Change-Id: I3d5518d1f6d6a78b14f25bb7ef79727605064561
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218653
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9083
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to provide richer semantics for running code
on all CPUs add an all-but-self construct.
BUG=chrome-os-partner:32082
BRANCH=None
TEST=Built and booted to kernel.
Change-Id: If8dd28ff7f34d93592ab2025a65a2fd665e4e608
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9a4622f63a065f620f0c92ef92eeb2aa5c2b441d
Original-Change-Id: Id18dc0423bcb0016ed36ace659b3f858e824c46c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218652
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9082
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Secure monitor runs at EL3 and is responsible for jumping to the payload at
specified EL and also to manage features like PSCI.
Adding basic implementation of secure monitor as a rmodule. Currently, it just
jumps to the the payload at current EL. Support for switching el and PSCI will
be added as separate patches.
CQ-DEPEND=CL:218300
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles succesfully and secure monitor loads and runs payload on ryu
Change-Id: If0f22299a9bad4e93311154e5546f5bae3f3395c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5e40a21115aeac1cc3c73922bdc3e42d4cdb7d34
Original-Change-Id: I86d5e93583afac141ff61475bd05c8c82d17d926
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214371
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9080
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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stage_entry is the best place to enter for secmon, since it sets up all the
stacks right. The only need we need to take care is losing out on the parameter
passed to secmon. This patch adds an entry point for secmon rmodule and moves
the argument from x0 to x25, which is restored just before the jump to c_entry
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I9638e9716b3bd5bff272e88fe9d965528d71e394
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ffedb03208bafab6d5886db0259ec205dd20588f
Original-Change-Id: I74a7a609fbc08692d68708abe132cd219c89b456
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217570
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9079
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Provide SCR_EL3 initialization on all CPUs. This settings were
chosen in such a way that nothing would need to be done if EL3
is abandoned after transitioning to EL2 or EL1. If persistent
EL3 program is used those SCR policies can be updated within
that program.
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Built and booted through kernel. Printed out SCR setting for
each CPU.
Change-Id: Ib44acd8ae40dbca590740340632f5b72998e9dd8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f77b903afbafad7d439ec50fc48f1eaa37827d90
Original-Change-Id: Id659f0a98360fe8bbc80e5a623eba1526e81b400
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218300
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9078
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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For every CPU that comes online initialize the GIC for
that CPU. This allows the per-cpu register state to
be initialized for every CPU that comes online.
BUG=chrome-os-partner:31945
BRANCH=None
TEST=Built and booted to kernel on ryu.
Change-Id: I467ca38d51ac67ffc19b1b4fc6fafa9394a876c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b2faf33fad80fd7ecb884d3ad40917f5a629a5b2
Original-Change-Id: I58d0ffcfe65cffc6a4dd2678c041219e1e698aaf
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217513
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9076
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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CQ-DEPEND=CL:216826,CL:218300
BUG=chrome-os-partner:31634
BRANCH=None
TEST=Compiles successfully and we are able to start execution of libpayload in
EL2 and reach kernel login prompt
Change-Id: I233f9867470a4723f320dc0dcaa670a56dcf0f5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 169948a2afeeb7848daeb37600963bd503527f1a
Original-Change-Id: I336d73085f08ca03e533555a10b88f20d74b4347
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217826
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9074
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Transition library acts as a common interface for handling exceptions. The only
thing that needs to be implemented by exception.c is the exc_dispatch routine to
handle the exceptions as required.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and exceptions are tested using test_exc
Change-Id: I90b4861909189adfe8449b9d4590965e6b743c00
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b83c9404407dd4dd2dda4e4eaed0b443f0f58425
Original-Change-Id: Ibb643d7ea2f9aabbc66439549ea2168fd66ced5e
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217143
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9071
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Transition library provides the following functionalities:
1) Setup the environment for switching to any particular EL and jump to the
loaded program at that EL. In short "Execute program X at exception level Y
using the state Z"
2) Provides routines for exception entry and exception exit that can be used by
any program to implement exception handling. The only routine required by the
program would be exc_dispatch which handles the exception in its own required
way and returns by making a call to exc_exit. On exc_exit, the transition
library unwinds the whole stack by popping out the saved state of xregs
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and exceptions are tested for ramstage on ryu
Change-Id: I8116556109665e61a53e4b3987d649e3cfed64a1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ab888e8cae0c5f1e79b0e16ca292869f16f1cca
Original-Change-Id: I90f664ac657258724dc0c79bd9f6ceef70064f90
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216375
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9070
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=chrome-os-partner:30785
BRANCH=None
TEST=Coreboot compiles successfully
Change-Id: I1fba44974314effa1065e3637aaa5430584a4cc6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a4791232de764ebe40d9b3de5c63479dec7da003
Original-Change-Id: I95fdff5d1580faf4cb4f85d6acae7a834b8ff0bf
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/218031
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9069
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If mmu_init is called more than once then, free_idx should be reset to
1. Here, the assumption would be that mmu_init will not be called more than
once. However, this is not necessarily true. Thus, free_idx should be reset to 1
every time we are initializing ttb from scratch.
BUG=None
BRANCH=None
TEST=Compiles sucessfully and boots to kernel
Change-Id: I5ac0af43346a492583380b0f15101390fc98d182
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 398a68c3b08d82cfa521d235af2c1922629bdf56
Original-Change-Id: Idb7424df7dd577f263f12d1527dbd7fb89216d40
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216906
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9068
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If there are no devices underneath a device in a devicetree the
bus pointer in a struct device is NULL. Check for this condition
before proceeding in walking through the children devices.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Ran through coreboot w/o any devices under the cpu_cluster device.
No more exceptions.
Change-Id: I9aedbc0dffc638b878bd0ffacfa318b6eb30d504
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d21e181077eba3c5ee03afca1738a24c21a8fc19
Original-Change-Id: I891aeb36319dce67ce9e431156c85c74177c7ab7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217511
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9066
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Instead of relying on config variables to determine the current el, use
{read/write}_current macros for accessing registers.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and boots to kernel login prompt
Change-Id: I6c27571fa65e06e28b71fee3e21d6ca93542e66b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 96aed53b2879310f6f979d5aa78b8d1df7f04564
Original-Change-Id: If4a5d1e9aa50ab180c8012862e2a6c37384f7f91
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217148
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9065
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: Id9367b1fc836b7b8c8fd15b372673853493f67d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 561e9c4ec2b0657846d50bbc893ef7541230f932
Original-Change-Id: Ie950e893b01456c23af14304bd4dd8f61af9f244
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216905
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9064
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Allow read/write to registers at a given el. Also, make read/write registers at
current el call this newly added function.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I98f35b8d3eb5e292ac895102ad91b675325c08c7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 11d90df1fd92e03c25bfc463429a5f6a8d9d411d
Original-Change-Id: I17de4c4f3bc1ee804422efe5f4703b4dd65b51f2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216904
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9063
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to ease the process of reading and writing any register at current EL,
provide read_current and write_current assembly macros. These are included in
arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow
the same header file to be included by .c and .S files.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I51749b6e4ae7b1ffbaae28d915cd100a28959f26
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c11c7287f507fa398cbbee75abc2bd11140ef19b
Original-Change-Id: I1258850438624abfe3b1ed7240df0db0e7905be6
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216373
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9062
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add smbios type 17 which can optionally be implemented
at the platform or mainboard level
In order to create SMBIOS type17, you will need to fill
memory_info data
BUG=None
BRANCH=None
TEST=Compile successfully on rambi and samus
Boot to chromeOS on samus and rambi
Original-Change-Id: Ie4da89135c879d7a687305d423103fcfcbb96e3f
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210005
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 634b899ba41242caa800d7b570f3a339c738db77)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I61d1e8b1d32d43f0011b0f93966d57646ea0eb63
Reviewed-on: http://review.coreboot.org/8955
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Iaf8167839f8506bd2ab08c2ba9f8317ba2437f28
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reported-by: Paul Menzel
Reviewed-on: http://review.coreboot.org/9054
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
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The original purpose of soc_secondary_cpu_init() was to provide
a way for the SoC to run code on the secondary processors as
they come up. Now that devicetree based bringup is supported
there's no need to have this functionality.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted SMP into linux.
Change-Id: I6fa39b66a8b728d9982b0721480b7fae45af7c6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1356ec527e2bc61043ccd7dea4a7ff5182b16f3e
Original-Change-Id: Ie5c38ef33efadb2d6fdb2f892b4d08f33eee5c42
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216927
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9044
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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There are some ARMv8/ARMv4 SoC where the ARMv8 part needs to be
SMP aware but the ARMv4 part does not.
Until we need real SMP on ARMv4, work around that situation
with stub defines.
Change-Id: Iec5b4302b19c17fe2b3f677b84a8edf4b4902946
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9046
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This adds SMP bring up support for arm64 cpus. It's
reliant on DEVICE_PATH_CPU devices in the devicetree.
Then for each enabled device it attempts to start then
initialize each CPU. Additionally, there is a cpu_action
construct which allows for running actions on an individual
cpu.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted both cores on ryu into linux.
Change-Id: I3e42fb668034c27808d706427a26be1558ad2af1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a733fd566a8e5793da5ff28f9c16c213f411372e
Original-Change-Id: I407eabd0b6985fc4e86de57a9e034548ec8f3d81
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216925
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9042
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add a cpu-internal.h for internal prototypes to the
architecture specific code.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and booted.
Change-Id: I12a379f86056a9a2007a7c036d65b5e08e558d0e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5dcd488326f6496d80eb1fe1ff4414ebba1280e9
Original-Change-Id: I8ab520478954a3b43e8e0831d1883f9a791850aa
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216924
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9041
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Provide a simple spinlock implentation for arm64. A value
of 0 is unlocked and a value of 1 is locked.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and ran SMP bringup on ryu.
Change-Id: Ie88a715a6b51cd38a5fdd830583dae528cc49d67
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 14dab94610c96d6b1530c64d661833f8e613101c
Original-Change-Id: I3bf2d80b91112d04442455ff0fa3f16900b7327f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216923
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9040
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The spinlock header file was not residing in the correct place.
It needs to live under 'arch/smp'.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with SMP. spinlock.h found.
Change-Id: Ie0e974674a6ea8ec769ca0ce64eb888c4d094652
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 50079befdc3d43306e4ae9e543f7266f1ac99aa0
Original-Change-Id: I0e594cacfafcd6f30802c9563785ca09a2f7a2af
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216922
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9039
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The load-acquire/store-release operations (including exclusive
variants) form a basis for atomic operations. Also remove
the dmb, dsb, and isb functions from lib_helpers as barrier.h
already included these. Lastly, utilize barrier.h.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and ran SMP bringup using barriers.
Change-Id: I6304a478d769dc2626443005b4eec4325d8a06f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8fac8d46b09d449d59f1b4f492d363392dcc4118
Original-Change-Id: I77ff160c635297a2c7cab71cb0d3f49f2536f6ff
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216921
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9038
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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printk() shouldn't be called until the consoles have been
initialized. This just so happened to work by luck. Once
CONFIG_SMP is enabled that breaks because of spinlock
usage in uncached memory.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with CONFIG_SMP and ramstage doesn't hang early.
Change-Id: I54231db3c811c0d19c5c7fbaa406cacd1ff019ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31c3f972ac5c89472009b5b2cb7dbc0f02cfd9a0
Original-Change-Id: I6091b1e949e648b3435231946e5924260bf1807f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216920
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9037
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The code should be GPL. Update accordingly.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=None
Change-Id: I051ceb3f12e9938819b513413aae43cbf51d9b86
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cdff53ebf4c1a1d86d68054c2d25dce45b69ff48
Original-Change-Id: I26a40a239afd851d351dbda0d716ef992b88b6c8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216428
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9035
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Provide access to the MIDR_EL1 register to obtain the
main id for determining CPU implementer and part/revision
information.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and printed the output of this function on ryu.
Change-Id: I42cec75072fc5e8b48f63c1971840fdc415e4326
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad19ffe629d9f16b8fd07051ce73533e97fb3f5c
Original-Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216423
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9032
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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These symbols should have been removed with the stack
refactoring. I'm not sure how it was missed.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into kernel with both cpus.
Change-Id: Ia6c2103d7b5e2c9d74cdc5d1b5f42f8954812231
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d9432b5cf0cce3bfdbfd5371fb3280e3cc746a42
Original-Change-Id: I17bc9a7aaaf133f427b15f803a6003fa2ca8f8a6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215541
Reviewed-on: http://review.coreboot.org/9024
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Provides a minimal API for coordinating with the SoC for
bringing up the secondary CPUs. There's no eventloop or
dispatcher currently nor does it do anything proper when
one of the secondary CPUs are brought up. Those decisions
are deferred to the SoC.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up 2nd cpu using this API.
Change-Id: I8ac0418282e2e5b4ab3abfd21c88f51d704e10f9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5303ae3d6bfc9f8f908fcb890e184eb9b57f1376
Original-Change-Id: I3b7334b7d2df2df093cdc0cbb997e8230d3b2685
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214775
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9019
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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exception_hwinit() provides a path for just setting the hardware
state. This allows for other CPUs but the boot CPU for setting up
the appropriate vector table.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted to the kernel.
Change-Id: Ifd44ab697bce5cd351f05069519785dc80e2b866
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 76a1c9cb3df930b28469608ecb5c35be7ccdadd1
Original-Change-Id: Ib09c813b49a4f00daca0b53d9dca972251fcf476
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214773
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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No need to pass in the same value for the ttb after just
calling mmu_init(). All current users are setting this once
and forgetting it.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted on ryu.
Change-Id: Ie446d16eaf4ea65a34a9c76dd7c6c2f9b19c5d57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bd77461d483b513a569365673c83badc752f4aa8
Original-Change-Id: I54c7e4892d44ea6129429d8a46461d089dd8e2a9
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214772
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9016
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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To allow setting the entry point for the secondary CPUs
provide a pointer, c_entry, which contains the location
to branch to after setting up the stack.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted to the kernel on ryu.
Change-Id: I03e54b081aa5ff70b90fbd7f1b243fdb4f42c5a6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f692c5814ea5c7ff4895576e1db8361ff3b7d9fb
Original-Change-Id: Ic2f6c79cde708b24c379345aed1e2cc0760ccad8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214771
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9015
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move the stack seeding out of assembly and into C so the
code in stage_entry.S can more easily be used. The seeding
of the stack doesn't touch at least 256 bytes to account
for current usage at time fo the call.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into kernel on ryu.
Change-Id: Ib9659ec4265652461bde746140567f21533cc265
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f478cfe175aa674cdfdbbd890663eeaad9d82b1f
Original-Change-Id: I44004220a02b1ff06d27a0555eb4e96d9e213544
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214770
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9014
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Instead of defining the stacks by Kconfig options include
the stack sizes for all the CPUs including each of their
exception stacks. This allows for providing each CPU
on startup a stack to work with.
Note: this currently inherits CONFIG_STACK_SIZE from x86 because
of the Kconfig mess of options not being guarded.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into the kernel on ryu.
Change-Id: Ie5fa1a8b78ed808a14efeb1717b98d6b0dd85eef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6524993f016aac2ac8cd9dba9fbdd9a59260a2b6
Original-Change-Id: Ica09dc256e6ce1dd032433d071894af5f445acdb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214669
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9013
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Provide a common entry point arm64 cores coming out of reset. Also,
take into account CONFIG_ARM64_CPUS_START_IN_ELx to set the
correct SCTLR_ELx register. The SCR_EL3 initialization was removed
as that can be done in policy code in C later. Part of this refactor
allows for greater code reuse for the secure monitor.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=built and booted to linux on ryu
Change-Id: I429f8fd0cdae78318ac171722fa1377924665401
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f92a5a01f07bc370735d75d695aedd8e2ab25608
Original-Change-Id: If16b3f979923ec8add59854db6bad4aaed35e3aa
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214668
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9012
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Depending on the armv8 implementation the cpus could start in
EL1, EL2, or EL3. Therefore allow the SoC to select the appropriate
mode.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built.
Change-Id: I8787fd1bc4e14f03d829e6a5e5af915e29314770
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb6b092a43e34fbc64d941bb62f19a6b8ac2c5de
Original-Change-Id: Id063681ef7691097e528c105fffac5d467585e4e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214666
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9010
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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There are 2 things wrong with the current implementation:
1. the stack isn't guaranteed to be aligned to CONFIG_STACK_SIZE.
2. the stack isn't necessarily CONFIG_STACK_SIZE bytes.
Utilize the smp_processor_id() function to obtain the correct
cpu_info structure to obtain the correct index.
BUG=chrome-os-partner:31545
BRANC=None
TEST=Built and booted.
Change-Id: I43d4a2baa26e48147bc0dbdb3e9e13ad023f0690
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e2c32b1a46ac8dc1364ed03c195322c0bf28dd7f
Original-Change-Id: I2825118e2313dbbf13712a4afdfa05a2e38ee3a4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214665
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9009
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
In order to accomodate MP on arm64 one needs to be able to determine
the current logical processor id. Because it depends on the SoC
implementation the SoC needs to provide this implementation.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built.
Change-Id: I2f09df9bf7d4f829d8f45471bf7281a4ddba2fc8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6033e73d70c3b8296b36ff36b4b848b176917e12
Original-Change-Id: I9511b54b5a1ab340b0f1309b0d9976be68b50903
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214663
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9007
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This just removes some unneeded symbols and comments. Additionally,
moved most of the absolute symbols into the individual sections.
Also, aligned data sections to 64 bytes (typical cache line size).
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted through coreboot normally on ryu.
Change-Id: I8ceed5a48078f70911122d304f2953795af0b421
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0524d4769613dc4a762e0a8e1bc1d2549d2df743
Original-Change-Id: I304e3702247a06507f5f4e23f8776331a3562c68
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214662
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9005
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
BUG=chrome-os-partner:31515
BRANCH=None
TEST=test_exception generates a page fault which is handled by the exception
handler and execution continues after eret from the exception
Change-Id: Ie550492d2ed21b2c3009b5627f1e1a37429e6af0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e29fe77745d10e840c02498e54a0c53835530e5e
Original-Change-Id: I29b7dabaece9b11a04ee3628d83513d30eb07b1d
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/213661
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9000
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Initialize the exception stack on stage_entry
BUG=chrome-os-partner:31515
BRANCH=None
TEST=Exception handling works fine
Change-Id: I66b4e73e77ad746e891cb2ae6662fbf0531f9d8a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a21d0a432e1742fd8b36b3f8fc7748152f7d74d2
Original-Change-Id: I0b6fb95c660c68fb47a30e905acb910b0e2eafea
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/213673
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8999
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Seed the stack in order to avoid boot process from complaining false stack
overflow.
BUG=chrome-os-partner:30824
BRANCH=None
TEST=Compiles successfully for rush and stack overflow error fixed in boot flow
Change-Id: I5d29d24eb5270d38a35a32171881b1aab8bf32e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 26e53568e82ad8418c20c2410f0cbc5c444c9917
Original-Change-Id: Ie51e1bcd263e3b886feb2e0e9c7d544f23c3444e
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210594
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8942
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Non-cacheable normal memory is needed when one wants an easy way
to have a DMA region. That way all the reads and writes will be
picked up by the CPU and the device without any cache management
operations.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With a bevy of other patches can use a carved out DMA region
for talking to USB.
Change-Id: I8172f4b7510dee250aa561d040b27af3080764d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a5bc7ab1709edd97d8795aa9687e6a0edf26ffc6
Original-Change-Id: I36b7fc276467fe3e9cec4d602652d6fa8098c133
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212160
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8924
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over
the bootblock, then exits to the romstage. this is necessary for some SOC
(e.g. tegra124) which runs the bootblock on a different architecture.
With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock.
Then, the bootblock loads the romstage over the verstage and exits to the
romstage. this is probably necessary for some SOC (e.g. rockchip) which does not
have SRAM big enough to fit the verstage and the romstage at the same time.
BUG=none
TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze.
BRANCH=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544
Original-Reviewed-on: https://chromium-review.googlesource.com/212365
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Note: This purposefully is probably broken in vendorcode/google/chromeos
as I'm just trying to set a base for dropping more patches in. The vboot
paths will have to change from how they are currently constructed.
(cherry picked from commit 4fa17395113d86445660091413ecb005485f8014)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I9117434ce99695f9b7021a06196d864f180df5c9
Reviewed-on: http://review.coreboot.org/8881
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Bootblock stack on Danube should be SRAM and defined separately from
the rest of the coreboot stack. The actual coreboot stack will be
defined later.
The top of the stack should be above the bottom, as the stack grows
towards lower addresses.
BUG=chrome-os-partner:31438
TEST=ran bootblock on simulator under codescape, observed stack
properly initialized.
Change-Id: I43d2bae5f85a09a95ca0103b253399bd92555aef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e02724cb4b30990ebaa631dabb45917af29d6437
Original-Change-Id: I3c37c8b5a1c0e7fd19411558a8f6d899fc283191
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/218732
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8767
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
With the proper configuration flags enabled, do_printk is available
from src/console, no need to define it elsewhere.
BUG=chrome-os-partner:31438
TEST=with upcoming patches, the urara board coreboot builds fine
Change-Id: I82071b4ca1686639c0bd39c63a06b61cb5bf5571
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 69c655537c50274a61cf123b7fc387ec60dd29c7
Original-Change-Id: Ib1e3e5750cdc1adc509b4580a4f24d3ff3b105ee
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215862
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8761
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Add the build infrastructure and basic architectural support required
to build for targets using the MIPS architecture. This is sufficient
to run on a simulator, but will require the addition of some cache
maintenance and timer setup in order to run on real hardware.
BUG=chrome-os-partner:31438, chromium:409082
TEST=none yet
Change-Id: I027902d8408e419b626d0aab7768bc564bd49047
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fcc0d934d7223922c878b1f87021cb5c2d7e6f21
Original-Change-Id: If4f99554463bd3760fc142477440326fd16c67cc
Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207972
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8760
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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As MIPS toolchain does not provide adequate support for 64 bit
division and shift operations, the missing functions are required to
be provided by the user.
This patch brings in the Linux implementation of the 64 bit arithmetic
shift borrowed from arch/mips/lib/ashldi3.c (eg. Linux v3.14).
BUG=chromium:406038
TEST=With the upcoming patches coreboot successfully builds for MIPS
targets in chroot (coming later).
Change-Id: I2168f69352a9b9e3c5d197489f701a442e65703c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8ec616161be8ad3aeb6494e7121615e3329b414d
Original-Change-Id: Ia1ccb29d4c9f3c95e04e06f6af7ce8a00e2e7455
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214156
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8759
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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It's helpful to view program size by inspecting the symbols.
_start and _end exist on romstage and ramstage. In order to
be consistent add _end for bootblock too.
BUG=None
BRANCH=None
TEST=Built and noted bootblock has _end symbol.
Change-Id: I06634b317e957e8271bf32530a56b5541c79b9ee
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b4ac926b30749d22e90a6f12ebac52107e241526
Original-Change-Id: I7f0b4dd4078c7d23c70949563b4c3f4df9e66142
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210832
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8824
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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When adding gargabe collection to x86 the --gc-sections
flags was inadvertently missed when linking romstage_null.debug.
Fix this omission.
Change-Id: I7d2700755afa78459c6f8707303a0e64936a1a9f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8850
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
|
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Instead of sprinkling the cbfs calls around (as well as getting
return values incorrect) use the common run_romstage() to perform
the necessary work to load and run romstage.
Change-Id: Id59f47febf5122cb3ee60f9741cfb58cb60ccab5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8711
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Miraculously a console is being compiled in for romstage.
However, as no calls were potentially printing to the preram
console this was being ignored. Instead provide the symbol
required so as not to fail the build.
Change-Id: Id8f0b6e6d15b41fa7fe1b63bf2d91f15baa0edda
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8712
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Instead of two headers for payload and ramstage loading
combine the 2 files into one. This also allows for easier
refactoring by keeping header files consistent.
Change-Id: I4a6dffb78ad84c78e6e96c886d361413f9b4a17d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8708
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The GCC 4.9.2 update showed that the boot_state_init_entry
structures were being padded and assumed to be aligned in to an
increased size. The bootstate scheduler for static entries,
boot_state_schedule_static_entries(), was then calculating the
wrong values within the array. To fix this just use a pointer to
the boot_state_init_entry structure that needs to be scheduled.
In addition to the previous issue noted above, the .bs_init
section was sitting in the read only portion of the image while
the fields within it need to be writable. Also, the
boot_state_schedule_static_entries() was using symbol comparison
to terminate a loop which in C can lead the compiler to always
evaluate the loop at least once since the language spec indicates
no 2 symbols can be the same value.
Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8699
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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Add license header with copyright of the original authors.
Change-Id: I8c55bb38a2a2a387ad2461e11d402c7392fa2497
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8691
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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Currently, the rmodules inclusion for vboot is dependent on ramstage_arch.
This change adds dependency on romstage_arch, since vboot is associated with
romstage. Inclusion based on ramstage_arch is left as is in case someone needs
it in ramstage.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for link, rush and nyan
Original-Change-Id: Ib62415671c26a4a18c7133d98e8c683414def32b
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209568
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 00da67cc02c81d7a6160f7336b33bf53b00e1875)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9df02134af4e396c7257a2db2e2c371cfd1a02bc
Reviewed-on: http://review.coreboot.org/8673
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Provide functionality to create dynamic classes based on program name and the
architecture for which the program needs to be compiled/linked. define_class
takes program_name and arch as its arguments and adds the program_name to
classes-y to create dynamic class and compiler toolset is created for the
specified arch. All the files for this program can then be added to
program_name-y += .. Ensure that define_class is called before any files are
added to the class. Check subdirs-y for order of directory inclusion.
One such example of dynamic class is rmodules. Multiple rmodules can be used
which need to be compiled for different architectures. With dynamic classes,
this is possible.
BUG=chrome-os-partner:30784
BRANCH=None
TEST=Compiles successfully for nyan, rush and link.
Original-Change-Id: I3e3aadbe723d432b9b3500c44bcff578c98f5643
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209379
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 242bb90d7476c2ee47d60c50ee18785edeb1a295)
Some of this cherry-pick had already been committed here:
commit 133096b6dc31163f59f658e15f2eb342a0de2ac6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9f5868d704c4b3251ca6f54afa634588108a788c
Reviewed-on: http://review.coreboot.org/8672
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
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Garbage collected sections allow for trimming the size of the
binaries as well as allowing for not needing to config off
unused functions. To that end, on a rambi build the following
differences are observed:
$ diff -up \
<(readelf -l coreboot-builds/google_rambi/cbfs/fallback/ramstage.elf) \
<(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/ramstage.elf)
--- /dev/fd/63 2015-03-10 12:07:27.927985430 -0500
+++ /dev/fd/62 2015-03-10 12:07:27.927985430 -0500
@@ -6,9 +6,9 @@ There are 4 program headers, starting at
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg
Align
LOAD 0x001000 0x00000000 0x00000000 0x00040 0x00040 RWE 0
- LOAD 0x001040 0x00000040 0x00000040 0x34560 0x34560 RWE 0
- LOAD 0x0355a0 0x000345a0 0x000345a0 0x02578 0x02578 RWE 0
- LOAD 0x037b18 0x00036b18 0x00036b18 0x00000 0x0b560 0
+ LOAD 0x001040 0x00000040 0x00000040 0x2cbf8 0x2cbf8 RWE 0
+ LOAD 0x02dc38 0x0002cc38 0x0002cc38 0x02208 0x02208 RWE 0
+ LOAD 0x02fe40 0x0002ee40 0x0002ee40 0x00000 0x0a888 0
Section to Segment mapping:
Segment Sections...
$ diff -up \
<(readelf -l coreboot-builds/google_rambi/cbfs/fallback/romstage.elf) \
<(readelf -l coreboot-builds/google_rambi_gc_sections/cbfs/fallback/romstage.elf)
--- /dev/fd/63 2015-03-10 12:08:16.855985880 -0500
+++ /dev/fd/62 2015-03-10 12:08:16.851985880 -0500
@@ -5,8 +5,8 @@ There are 1 program headers, starting at
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg
Align
- LOAD 0x000060 0xfff20000 0xfff20000 0x08b81 0x08b81 R E
0x10
+ LOAD 0x000060 0xfff20000 0xfff20000 0x06300 0x06300 R E
0x10
Section to Segment mapping:
Segment Sections...
- 00 .rom .text
+ 00 .rom
The following warnings needed to be applied to CFLAGS_common because for
some reason gcc was miraculously emitting the warnings with the
unrelated *-sections options:
-Wno-unused-but-set-variable
Change-Id: I210784fdfc273ce4cb9927352cbd5a51be3c6929
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8635
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
BUG=None
BRANCH=None
TEST=Compiles successfully
Original-Change-Id: I395c9b7bbe34c6834abc1a169779639f940121bd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209334
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit da15df16464f4203db08fb02ad4c0a0f94d16724)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I818de7cb0d8a44fb20c2bbea108c15ecc2b724ae
Reviewed-on: http://review.coreboot.org/8650
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add support for initializing and enabling mmu for armv8. Using 64KiB granule and
33 bits per VA, thus total VA address space is 6GiB. PA Range is 64GiB. Makes
use of memrange library to get a list of all the mmap regions from the SoC to
initialize XLAT table.
Currently, all calculations in mmu.h are based on the assumptions that max 33
bits are used in VA and granule size is 64KiB. Changes in these assumptions will
have to reflect in the dependent calculations as well.
BUG=chrome-os-partner:30688
BRANCH=None
TEST=Compiles rush successfully and boots until "payload not found". Goes past
all the earlier alignment errors.
Original-Change-Id: Iac1df15f0b81dcf64484a56b94f51357bcd67cc2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208761
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6fe96360c03342115f849074f9e45a2c4e210705)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5360a3be95f198bd0b4f79b62f31228cc7a9c285
Reviewed-on: http://review.coreboot.org/8646
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
|
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The CCSIDR_EL1 register has cache attribute information
for a given cache selection in CSSELR_EL1. However, the
cache isn't being selected before reading CCSIDR_EL1.
Instead use CTR_EL0 which better fits with the semantics
of dcache_line_bytes(). CTR_EL0 has the minimum data cache
line size of all caches in the system encoded in 19:16 encoded
as lg(line size in words).
BUG=None
TEST=Built.
Original-Change-Id: I2cbf888a93031736e668918de928c3a99c26bedd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208720
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 8d5dfba35d74fc4c6ee14365a2e9d9ed9f43115d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1db47ff5850c276d0246ac67e8b96f7ed19016c0
Reviewed-on: http://review.coreboot.org/8642
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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There is nothing platform specific in retrieving S3 resume state from
romstage_handoff structure. Boards without EARLY_CBMEM_INIT update
acpi_slp_type from ACPI power-management block or scratchpad registers.
Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8188
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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This was added to handle cases of Intel FSP platforms that had
EARLY_CBMEM_INIT but could not migrate CAR variables to CBMEM.
These boards were recently fixed.
To support combination of EARLY_CBMEM_INIT without CAR migration was
added maintenance effort with little benefits. You had no CBMEM
console for romstage and the few timestamps you could store were
circulated via PCI scratchpads or CMOS nvram.
Change-Id: I5cffb7f2b14c45b67ee70cf48be4d7a4c9e5f761
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8636
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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The CAR macros and the associated functions are only employed
under the following conditions:
- chipsets which have CAR
- compilation during romstage
Therefore clean up the build-time conditionals to use those 2
constructs.
Change-Id: I2b923feeb68f2b964c5ac57e11391313d9c8ffc5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8634
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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All boards in tree use 0. Looks like this is all work that was
never completed and tested.
We also have static setting sysconf.segbit=0 which would conflict
with PCI_BUS_SEGN_BITS>0.
Having PCI_BUS_SEGN_BITS>0 would also require PCI MMCONF support
to cover over 255 buses.
Change-Id: I060efc44d1560541473b01690c2e8192863c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Some of the SoC's need an early hook to configure
certain registers. One example of this is on t132
where ramstage is the first thing being ran on the
arm64 core and it is the only entity that can configure
certain registers required for the rest of ramstage.
Therefore, provide the opportunity for the SoC to
implement such requirements.
BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and ran through coreboot.
Original-Change-Id: Ib352f3788872f888581b398c9b394b7c4e54b02a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208061
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 2c50e2b39e75d1383e8e573c576630a5b7313349)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I38df63e46c5c21b2d319fc9eb42053c3a0d61bc8
Reviewed-on: http://review.coreboot.org/8595
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Since RES1 and RES0 bits are marked as SBOP(Should-Be-One-or-Preserved) and
SBZP(Should-Be-Zero-or-Preserved) respectively, resetting the SCTLR and SCR
registers should be done with proper bitmask.
BUG=None
BRANCH=None
TEST=Compiles successfully and verified that the RES bits are preserved across
register writes.
Original-Change-Id: I5094ba7e51e8ea6f7d7612ba4d11b10dcbdb1607
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/207815
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit dfb196b4063e4f94d1ba9d5e2d19bae624ed46b3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I033a68b723fea83817aaa6402b86c78abd3e1da9
Reviewed-on: http://review.coreboot.org/8592
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
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To align with arm use the RAMSTAGE_BASE Kconfig option
for start of ramstage. Also, use 16-byte alignment for the
start and end of the sections. 4 bytes were previously used, but
it definitely seems more appropriate to at least have the heap
handing out 16-byte aligned pointers.
BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and booted through attempting to load payload
Original-Change-Id: I39329055696ae21a9ed1d9a64769981ab4dcdddd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207432
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 6291f3bed705154743be78a881a26dfc9d041c5e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic280b4c6435c4f8e0e783fe5bd4694832ce9b550
Reviewed-on: http://review.coreboot.org/8588
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Inconsistent progress was observed running ramstage.
It was determined that the hand-coded assembly functions
were causing issues. Some of the comments seems suspect about
the hardware taking care of alignment. The prudent thing to do
is to use the C ones. Optimization can come later after maturity.
BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and booted to attempting to payload
Original-Change-Id: I4137adf9b36b638ed207e4efd57adaac64c6a6c1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207431
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 2762e478c6b59dd30c59aa87a922d0f78c00c0c4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id3196b0c2bf41a21db31f999ba437d118875a236
Reviewed-on: http://review.coreboot.org/8587
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Ramstage needs an assembly entry point for setting up
the initial state of the CPU. Therefore, a function is
provided, arm64_el3_startup(), that bootstraps the state
of the processor, initializes the stack pointer, and
branches to a defined entry symbol. To make this work
without adding too much preprocessor macro conditions
provide _stack and _estack for all the stages.
Currently the entry point after initialization is 'main',
however it can be changed/extended to do more work such
as seeding the stack contents with tombstones, etc.
It should be noted that romstage and bootblock weren't
tested. Only ramstage is known to work.
BUG=chrome-os-partner:29923
BRANCH=None
TEST=Brought up 64-bit ramstage on rush.
Original-Change-Id: I1f07d5b6656e13e6667b038cdc1f4be8843d1960
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207262
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 7850ee3a7bf48c05f2e64147edb92161f8308f19)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia87697f49638c8c249215d441d95f1ec621e0949
Reviewed-on: http://review.coreboot.org/8585
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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The driver structures live in special sections which have no
direct reference to the symbols. Therefore, when garbage
collecting sections in the linker the drivers are tossed out
resulting in no drivers being linked into ramstage. Fix this
by adding the KEEP() directive to those special sections.
BUG=chrome-os-partner:29923
BRANCH=None
TEST=Built and noted console starts working in ramstage.
Original-Change-Id: Iaa0fd428bf975c82d4e6b0e75a17e6fd231fbaa9
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/207261
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 7c1a3e63e398755de0c77524a0483e6f1019aac0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1e30e73be754ec849cb3cfac3bcb12e95b0f60d4
Reviewed-on: http://review.coreboot.org/8584
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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As a convenience, print the actual stage name when entering a stage.
Also unify the banner between bootblock / romstage and ramstage. No
reason for two different occurences.
Instead of this:
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 booting...
you will see this:
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 bootblock starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 romstage starting...
[..]
coreboot-4.0 Tue May 13 14:13:37 PDT 2014 ramstage starting...
Roughly based on: https://chromium-review.googlesource.com/199671
Change-Id: Id5894535e0551d113c80e4ff0514287391be1bef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/8578
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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Add basic romstage support for rush. Since, dram init needs to be done before we
can jump to armv8 core, romstage will run on armv4 core as well. Thus,
correcting the compiler selection options.
BUG=None
BRANCH=None
TEST=Compiles successfully for rush. Prints romstage banner and initial printk
Original-Change-Id: Ie3cd290e56a712b07c1503dab199e4e34cec04d2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205763
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit d20b4e66209e902f54a07a17d5ce741f0a0b3a7b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic6b7ef4a2ea01c95d0c7f040bbd079219cf5750a
Reviewed-on: http://review.coreboot.org/8573
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Correct function names to make them consistent with generic calling name
BUG=None
BRANCH=None
TEST=Compiles successfully for rush
Original-Change-Id: I50499936e1c8da0aafd7e36a22c2c6ab373230f6
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205582
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 16668529527224fca3086ee88955d29e3a268516)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I449e63b05680ca12ae81a3260fc03836686d7317
Reviewed-on: http://review.coreboot.org/8469
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Define functions for setting cntfrq register in arm and arm64 arch. This allows
SoCs to set this register independently of the architecture being used.
BUG=None
BRANCH=None
TEST=Compiles successfully for nyan and rush
Original-Change-Id: I93240419b2c012eee29a408deff34a42af943a63
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205580
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 768463fef5d630dec915aa0b95e7724d4a6f74b6)
armv8: GPL license armv8 lib
BUG=None
BRANCH=None
TEST=Compiles successfully.
Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250950
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I298c3e76cb52f0876bce3dd4f54d875f62e9310a
Reviewed-on: http://review.coreboot.org/8468
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Add support for library functions required to access different system registers:
1) PSTATE and special purpose registers
2) System control registers
3) Cache-related registers
4) TLB maintenance registers
5) Misc barrier related functions
BUG=None
BRANCH=None
TEST=Compiles successfully
Original-Change-Id: I8809ca2b67b8e560b34577cda1483ee009a1d71a
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203490
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 5da840c5d1f3d8fdf8cc0d7c44772bf0cef03fbb)
armv8: GPL license armv8 lib
BUG=None
BRANCH=None
TEST=Compiles successfully.
Original-Change-Id: Ibe0f09ef6704ad808cc482ffec27a4db32d7f6fd
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250950
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit bc115869bb0bcedbc284677ca5743b9ab40bfc7e)
Get the library and the GPL license in a single commit.
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4753a6b0d13a6f7515243bfa8e749e250fdd749d
Reviewed-on: http://review.coreboot.org/8465
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The early_console.c file isn't used or built. It has been replaced
by the generic uart and console drivers.
Change-Id: I505b4e48d2369dbbfd92ef1dab364c5f2ed924df
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8529
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The change in commit 5636237 allows */cpu/amd/agesa/* to be removed.
TEST: Booted the amd/parmer board.
Change-Id: I8d2d2639f8e5f3b1dd58be96be98db0eff7b268f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8505
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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The existing code generated invalid ACPI processor objects
if the core number was greater than 9. The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.
The modified code will function with up to 99 cores.
Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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In specific configurations, such as homogeneous supercomputing systems,
changeable NVRAM parameters are more of a liability than a useful tool.
This patch allows a coreboot image to be compiled that will always set
the NVRAM parameters to their default values, reducing maintainance
overhead on large clusters.
Change-Id: Ic03e34211d4a58cd60740f2d9a6b50e11fe85822
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8446
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
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Change-Id: I098d1238cda16060c3566f242443007cdaf9bd82
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5106
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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BUG=None
BRANCH=None
TEST=Compiles successfully for rush
Original-Change-Id: Ic8f5d91f6635ef12845ab049a20df5a6e33bbf55
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203142
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ecf7822812d8745af74eaf135b7b806c23ef51a2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I79abbded94376ba90a8c729aaf856ce303509e48
Reviewed-on: http://review.coreboot.org/8410
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
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The "used" attribute was added in commit 27cf2472 which caused these
warnings to start appearing when using the standard coreboot GCC
toolchain:
{standard input}: Assembler messages:
{standard input}:96: Warning: ignoring changed section type for .car.global_data
{standard input}:96: Warning: ignoring changed section attributes for
.car.global_data
The # at the end of the section name causes the assembler to
ignore everything following the name. I verified that the resulting
binaries are the same with and without the #.
Change-Id: Iaac8042533842ed887f33895f083b613a18f496a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8301
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Although bool normally belongs in stdbool.h, for our use cases,
providing these definitions in stdint.h is acceptable.
Change-Id: I1d0ca1018efacc27d7a4a72aa452912e004401f9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8279
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
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Drop the implementation of statically allocated high memory
region for CBMEM. There is no longer the need to explicitly
select DYNAMIC_CBMEM, it is the only remaining choice.
Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7851
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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We can now create CBMEM with dynamic allocation even if CBMEM
location is resolved late in ramstage.
Change-Id: I8529ccbcd4a0e567ebe0a46232ac5d16476e81a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7861
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
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The name was always obscure and confusing. Instead define cbmem_top()
directly in the chipset code for x86 like on ARMs.
TODO: Check TSEG alignment, it used for MTRR programming.
Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
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Move the CAR migration call to arch -specific part of CBMEM init,
it is truly a x86 specific thing.
Change-Id: I715417e54f197b8745e0670d6b900a5660178141
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7860
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
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