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Currently only x86 requires special handling here, for simplicity
avoid introducing <arch/rules.h> and deal with this directly in
<rules.h>.
For consistency prefixes are changed from ARCH_ to ENV_.
Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Allow a driver to return device specific _HID, which will be consumed by
acpigen in order to generate proper SSDTs.
Change-Id: Ibb79eb00c008a3c3cdc12ad2a48b88a055a9216f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35006
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With RELOCATABLE_RAMSTAGE, S3 resume path only uses
memory that is reserved from OS. So there is no need
for low memory backup and recovery.
Change-Id: If7f83711685ac445abf4cd1aa6b66c3391e0e554
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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ACPI S3 resume path can only modify low memory where
the non-relocatable ramstage resides, there is no need
to maintain a bigger backup copy.
Change-Id: Ifae41b51b359010ec02269c674936a87bd15623b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/15476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Start with moving all postcar_frame related function
declarations here from <arch/cpu.h>.
Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/15474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Variable length arrays were a feature added in C99 that allows the
length of an array to be determined at runtime. Eg.
int sum(size_t n) {
int arr[n];
...
}
This adds a small amount of runtime overhead, but is also very
dangerous, since it allows use of an unlimited amount of stack memory,
potentially leading to stack overflow. This is only worsened in
coreboot, which often has very little stack space to begin with. Citing
concerns like this, all instances of VLA's were recently removed from the
Linux kernel. In the immortal words of Linus Torvalds [0],
AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and
much _slower_ code (and more fragile code), than just using a fixed
key size would have done. [...] Anyway, some of these are definitely
easy to just fix, and using VLA's is actively bad not just for
security worries, but simply because VLA's are a really horribly bad
idea in general in the kernel.
This patch follows suit and zaps all VLA's in coreboot. Some of the
existing VLA's are accidental ones, and all but one can be replaced with
small fixed-size buffers. The single tricky exception is in the SPI
controller interface, which will require a rewrite of old drivers
to remove [1].
[0] https://lkml.org/lkml/2018/3/7/621
[1] https://ticket.coreboot.org/issues/217
Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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As most platforms will share the subset of enabling
both low RAM WB and high ROM WP MTRRs, provide them
with a single function.
Add possibility for the platform to skip these if
required.
Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9a4e57f8fd032f2824eab0e5b59d635710e3e24b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It is easier to track CAR_GLOBAL_MIGRATION which is
the approach to be deprecated with the next release.
This change enforces new policy; POSTCAR_STAGE=y is
not allowed together with CAR_GLOBAL_MIGRATION=y.
Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change the TPM2 ACPI Table to support CRB Interface when selected.
Change-Id: Ide3af348fd4676f2d04e1d0b9ad83f9124e09dcc
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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smbios.h had already declared smbios_mainboard_enclosure_type so this
change defines it. It can be overridden in a mainboard so the enclosure
type can be set at runtime.
We have a mainboard that will be used in different enclosures and we are
planning on using a single BIOS image for all of the enclosures so it
will need to be set dynamically based on sku.
BUG=b:138745917
TEST=Built arcada firmware and verified via dmidecode that enclosure type
is correctly set to "Convertible", then temporarily added a
smbios_mainboard_enclosure_type to arcadas board file returning
0x20 and verified with dmidecode that the enclosure type is
"Detachable"
Change-Id: Iba6e582640989f5cb7e6613813e7b033760a977c
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Constify the struct device arguments in below APIs:
> acpi_device_name
> acpi_device_path_fill
> acpi_device_path
> acpi_write_dbg2_pci_uart
> acpi_device_scope
> acpi_device_path_join
The APIs do not seem to modify the argument and are using
device argument as reference to device only.
Change-Id: Ic2ce045f17efa288eb41503795723d0ad5ec78bd
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34625
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The function implementations are in local platform
scopes.
Change-Id: I7a3025398b15fe6d2c5a13cdb65f3e62a49c0bc6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34151
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are only minimal differences between the architecture specific
stdint.h implementations, so let's tidy them up and merge them together
into a single file. In particular,
- Use 'unsigned long' for uintptr_t. This was already the case for x86
and riscv, while arm and mips used 'unsigned int', and arm64 and ppc64
used 'unsigned long long'. This change allows using a single integer
type for uintptr_t across all architectures, and brings it into
consistency with the rest of the code base, which generally uses
'unsigned long' for memory addresses anyway. This change required
fixing several assumptions about integer types in the arm code.
- Use _Bool as the boolean type. This is a specialized boolean type that
was introduced in C99, and is preferrable over hacking booleans
using integers. romcc sadly does not support _Bool, so for that we
stick with the old uint8_t.
- Drop the least and fast integer types. They aren't used
anywhere in the code base and are an unnecessary maintenance burden.
Using the standard fixed width types is essentially always better anyway.
- Drop the UINT64_C() macro. It also isn't used anywhere and doesn't
provide anything that a (uint64_t) cast doesn't.
- Implement the rest of the MIN and MAX numerical limits.
- Use static assertions to check that the integer widths are correct.
Change-Id: I6b52f37793151041b7bdee9ec3708bfad69617b2
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I48c0de73338430282ce1a4442bbeb7c867dc174c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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AMD Picasso, and later, will not use CPU_AMD_AGESA or CPU_AMD_PI.
Those two symbols indicate an Arch2008 system. Add SOC_AMD_COMMON
to cause cpu_is_amd() to return TRUE on Picasso.
This removes an error message of "Unknown CPU".
The patch also assumes AMD Family 10h and non-AGESA Family 15h
devices were seeing the "Unknown CPU" message. No functionality
has been verified on these devices.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I3357606c37082f3587ff91924bf7a0e0f8af9625
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34146
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.
Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Spotted out using -Wconversion gcc warning option.
Change-Id: Ib882cfa6d429fbfcab2b8132280182b427d510aa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33803
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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size_t is the wrong type to store the return value of
acpi_device_path_fill(), since any negative error values will be
converted to a very large unsigned integer and potentially cause
buffer overflow.
Change-Id: Ia8ed62ecfac8eaa18a61545bd203b3c7a7cd9ca5
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This code is currently only used by via/epia-m850,
it is also somewhat buggy.
Change-Id: I140e15d584d3f60f7824bcb71ce63724c11e3f46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34078
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With VBOOT=y && VBOOT_MEASURED_BOOT=y message
digest will be allocated from the stack and
1 KiB reserve used with the recent platforms
was no longer sufficient.
The comment of LZMA scratchpad consuming stack
was obsolete for postcar, so these can be reduced
to same 4 KiB.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57c0bcfbe0d96aac106f771e8efb3bd471302c25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33965
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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`cpuid_eax()` returns an unsigned integer.
Change-Id: Iebb6501130bc9ae333d45ae9d2e10c918245a6d1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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For the PCI_VENDOR_ID_ATI case, we can rely on
pci_rom_acpi_fill_vfct() to make the call if necessary.
For hardware other than ATI, pci_rom_probe() was already
called from pci_rom_ssdt() and pci_dev_init(), so
PCI_ROM_ADDRESS BAR is already enabled, if requested so.
Change-Id: I0ea893a9ac7ba480840ebf5570d8fe0d9e20938f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
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* Add architecture independend way of clearing all DRAM
* Implemented in ramstage as MTRRs need to be set to speed up
clearing. Takes up to 15 seconds per GiB otherwise.
* Use memset_pae on x86
* Add quirks for FSP1.0
Tested on P8H61M-Pro:
* Clears 4GiB in less than 1 second
Tested on wedge100s:
* Clears 8GiB in 2 seconds
Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31550
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ALIGN((a), b) and ALIGN_UP(a, b) needs 'helpers.h'
Change-Id: I029c7c5cbb19c7e69997b3d84f929cb61e8e2b23
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The ALIGN_UP macro is basically an alias of the ALIGN macro; with this change
it's more obvious in which direction the alignment happens.
Change-Id: I6f1b9f9bbcafeb85a6ef5c10ce4b57edc0740e72
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
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This patch contains the rest of the fixes for this subtree; having one change
for every area would create an unnecessary amouint of patches.
Change-Id: Id92c11d58693292d58cba323c8468db858becfb5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33630
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Idfb814abee87d52d0f5970ec0cd291f738631320
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33629
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ALIGN_UP is an alias for ALIGN.
Change-Id: Ie723ebe80f8f627021151413cb43adce6c88a0dc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33628
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Chengdu Haiguang IC Design Co., Ltd (Hygon) is a Joint Venture
between AMD and Haiguang Information Technology Co.,Ltd., aims
at providing high performance x86 processor for China server
market. Its first generation processor codename is Dhyana, which
originates from AMD technology and shares most of the architecture
with AMD's family 17h, but with different CPU Vendor ID ("HygonGenuine")
/Family series number (Family 18h).
More details can be found on:
http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.puwen@hygon.cn
Change-Id: I8af8b0f0675f978ac07522029696e43651a3153f
Signed-off-by: Jinke Fan <fanjinke@hygon.cn>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32876
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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'else' is not needed after a 'break' or 'return'.
Change-Id: Ib7bdefb0027a35de42f6a665b98f9e5a2791061f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change the SMBIOS Version from 2.7 to 2.8. Necessary changes were
already pushed in https://review.coreboot.org/c/coreboot/+/33031
Change-Id: I237cdee7d43e814397b958e4cf941bf58949088d
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Add the SPMI table as defined in the IPMI spec v2:
https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
Tested on Wedge100s.
Change-Id: Idff5134ce4c124f7e76acb0080da404b0c0dfffe
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33487
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The sandybridge systemagent-r6 blob is modified:
- To be more flexible about the location of the stack w.r.t. the heap
- Place the MRC pool right below the MRC_VAR region
- to work with the same DCACHE_RAM_BASE from the native raminit (could
make the CAR linker symbols easily compatible if desired)
This allows CAR setup compatibility between mrc.bin and native
bootpath and also allows for BIOS/memory mappeds region larger than
8MB.
This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also
include the pool on top of MRC_VAR region.
TESTED on T520 (boots and resumes from S3 with mrc.bin).
Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33228
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Selecting which cbfs prefix to load is only implemented with the romcc
bootblock.
Change-Id: I09523b94605f00ab15b5f0ea3986ac08e3a6afc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Icf5e8fa18bea1cdfb85b8a4999d8fccea94d16b9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch removes CONFIG_NO_STAGE_CACHE check from caller function
and add empty inline function incase CONFIG_NO_STAGE_CACHE is enable.
Change-Id: I8e10ef2d261f9b204cecbeae6f65fda037753534
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add support for generating IndexField, which is similar to Field.
Change-Id: If66a627e64953696b0b68488256bd5c141e4c205
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33032
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch makes smm related files compile independent of
ramstage getting compiled.
If user selects RAMPAYLOAD to boot without ramstage, there
will be need for smm code to get compiled independently.
Change-Id: I17a3eb80a4d5ef86e0319357c01b6bf5b90ef15b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ECC Support and VDD Voltage to dimm_info struct. Now Bus Width
and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry.
Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33031
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clang Static Analyzer version 8.0.0 detects null pointer argument
in call to memory copy function. Add sanity check for pointer header
to prevent null pointer dereference.
TEST=Built and boot up to kernel.
Change-Id: I7027b7cae3009a5481048bfa0536a6cbd9bef683
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This patch removes unnecessary kconfig depencies as below
1. CONFIG_ARCH_RAMSTAGE_X86_32
2. CONFIG_RELOCATABLE_RAMSTAGE
Include required files as is without specify kconfig option.
Change-Id: Ic9d1a95e80178775dd78e756f97f6da13a24dc95
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
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<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I57aead27806e307b9827fc7ee2cd663f12ee6e5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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It doesn't make sense to add a property to a non-existent Device
Property package. However, some of these functions will proceed anyway
and allocate a new Device Property package, add the property to
that, and then immediately leak the new package. This changes all the
acpi_dp_add_* functions to ignore a null package.
Change-Id: I664dcdbaa6b1b8a3aeb9a0126d622e2ffb736efd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 135745{6,7}, 138029{2-6}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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SMBIOS Type41 Entries will be automatically created. Type 41 entries
define attributes of the onboard devices.
Change-Id: Idcb3532a5c05666d6613af4f303df85f4f1f6e97
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32910
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Required for automatic onboard device detection in the next patch.
Change-Id: I3087de779faf8d006510c460b5372b22ae54b887
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32909
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new post code, POST_INVALID_ROM, used when coreboot fails to
locate or validate a resource that is stored in ROM.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ie6de6590595d8fcdc57ad156237fffa03d5ead38
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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According to JEP106 from JEDEC, fix manufacture ID of Crucial,
Super Talnet and Micron.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I10a268a7f3bde405b95bd3a16d5d121be623c7ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Previously cpu_index() always succeeded, but since commit 095c931
(src/arch/x86: Use core apic id to get cpu_index()) it is now possible
for it to indicate an error by returning -1. This commit adds error
handling for all calls to cpu_index(), and restores several checks that
were removed in commit 7c712bb (Fix code that would trip -Wtype-limits)
but are now needed.
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I5436eed4cb5675f916924eb9670db04592a8b927
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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TEST=Able to build coreboot for CML.
Change-Id: Ic0f473e04ffc1de50dee871af52eacf0b328b376
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32764
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This cpu_index() implementation assumes that cpu_index() function
might always getting called from coreboot context (ESP stack
pointer will always refer to coreboot).
This might not be true in case of proposed PI spec MP_SERVICES_PPI
implementation, where FSP context (stack pointer refers to fsp)
will request to get cpu_index(), natural alignment logic will
use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte).
This is not the place where cpu_index is actually stored by
ramstage c_start.S
Hence this patch tries to remove those dependencies while retrieving
cpu_index(), rather it uses cpuid to fetch lapic id and matches with
cpus_default_apic_id[] variable to return correct cpu_index().
BRANCH=none
BUG=b:79562868
TEST=Ensures functions can be run on APs without any failure and
cpu_index() also provides correct index number.
Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26346
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We keep the support, though. Just now that `libgfxinit` is fixed, we
don't need the distinction anymore. Causally, we also don't need
CPU_INTEL_MODEL_306AX any more.
TEST=Played tint on kontron/ktqm77. Score 606
Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch renames mp_get_apic_id() to cpu_get_apic_id() and
add_cpu_map_entry() to cpu_add_map_entry() in order access it
outside CONFIG_PARALLEL_MP kconfig scope.
Also make below changes
- Make cpu_add_map_entry() function available externally to call
it from mp_init.c and lapic_cpu_init.c.
BRANCH=none
BUG=b:79562868
Change-Id: I6a6c85df055bc0b5fc8c850cfa04d50859067088
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Use the devicetree values for type 9 slots.
Tested on Lenovo T520.
Change-Id: I1961d8af2d21f755ff52ad58804ea9b31d2a5b9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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The file is no longer used by any code. Remove it.
Change-Id: I73f06cac11201dc37218d352ab995cf4f012c36a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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DMA remapping structure flags settings are Bit 0: INTR_REMAP, Bit 1:
X2APIC_OPT_OUT, Bit 2: DMA_CTRL_PLATFORM_OPT_IN_FLAG, Bits 3-7:
Reserved (0).
BUG=b:130351429
TEST=Image built and kernel booted to kernel.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Iaf4764a9062756cadc335d1932b0da8628797f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32516
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remapping Hardware Status Affinity (RHSA) structure is applicable for
platforms supporting non-uniform memory. An ACPI Name-space Device
Declaration (ANDD) structure uniquely represents an ACPI name-space
enumerated device capable of issuing DMA requests in the platform.
Add RHSA and ANDD structures support for DMAR table generation.
BUG=b:130351429
TEST=Image built and booted to kernel
Change-Id: I042925a7c03831061870d9bca03f11bf25aeb3e7
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: If3c9783ebc41c103c915788139d91644b805f397
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Without VBOOT_MEASURED_BOOT there is no need for these symbols.
Change-Id: I96391b7817c79f760713c67bc469164b5514879e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add SMBIOS type 9 system slots into coreboot, the definiation is up to
date with SMBIOS spec 3.2
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ibcfa377c260083203c1daf5562e103001f76b257
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Serial bus revision [Byte 3] and serial bus specific revision [Byte 9]
are not the same.
Change-Id: I366f62e6aa0e9c0dfbc1ec17adeebc42a0e777eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Change-Id: Ib843eb7144b7dc2932931b9e8f3f1d816bcc1e1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Guckian
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Sandy- and ivybridge use the same mrc.bin that has the heap in an
awkward location.
Change-Id: If985a48c6703c8a86d8051e67595cf0fd409d99a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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As reported by Coverity Scan CID 1400679.
Change-Id: I526b78a0697b7eb3c3dc75974c3a3a714b3d343f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32313
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Current SMBIOS type 17 device and bank locator string is like
"Channel-x-Dimm-x" and "Bank-x", x is deciminal number. Give silicon or
mainboard vendor a chance to replace with something matches with
silkscreen.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I54f7282244cb25a05780a3cdb9d1f5405c600513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Sync acpigen.h content to match with laetst acpica, the link is
https://github.com/acpica/acpica/blob/master/source/include/amlcode.h,
and revision is 20190405. The purspose of the change is just make spec
up to date.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: If5f5da70eb66472ddf5df0d72ca85de41faac128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to
calculate nominal TSC frequency.
As per SDM recommendation:
For any processor in which CPUID.15H is enumerated and
MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is
available, a more accurate frequency can be obtained by using CPUID.15H
This patch also adds header file to capture Intel processor model number.
BUG=b:129839774
TEST=Boot ICL platform and calculate TSC frequency using below methods
1. TSC freq calculated based on MSR 0xCE
tsc: Detected 1600.000 MHz processor
2. TSC freq calculated based on CPUID 0x15
tsc: Detected 1612.800 MHz TSC
Method 2 actually reduce ~25ms of boot performance time.
Note: Method 2 is recommended from gen 6 processor onwards.
Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Fill in the handle to cache entries of type 7 in the type 4 structure.
Tested on Intel Sandy Bridge (Lenovo T520).
All 3 caches are referenced.
Change-Id: Idf876b0c21c65f72a945d26c5898074b140763f8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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The SMBIOS spec requires type 7 to be present.
Add the type 7 fields and enums for SMBIOS 3.1+ and fill it with the
"Deterministic Cache Parameters" as available on Intel and AMD.
As CPUID only provides partial information on caches, some fields are set to
unknown.
The following fields are supported:
* Cache Level
* Cache Size
* Cache Type
* Cache Ways of Associativity
Tested on Intel Sandy Bridge (Lenovo T520).
All 4 caches are displayed in dmidecode and show the correct information.
Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Add two functions to determine if CPU is made by a specific vendor.
Use Kconfig symbols to allow link time optimizations.
Change-Id: I1bd6c3b59cfd992f7ba507bc9f9269669920b24f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julien Viard de Galbert <coreboot-review-ju@vdg.name>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The effect of pointer aliasing on writes is that any data on CPU
registers that has been resolved from (non-const and non-volatile)
memory objects has to be discarded and resolved. In other words, the
compiler assumes that a pointer that does not have an absolute value
at build-time, and is of type 'void *' or 'char *', may write over
any memory object.
Using a unique datatype for MMIO writes makes the pointer to _not_
qualify for pointer aliasing with any other objects in memory. This
avoid constantly resolving the PCI MMCONF address, which is a derived
value from a 'struct device *'.
Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I1bf5ac6c411720d349df8fd706015c6835758cd0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29529
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit b7daf7e8fa18de7bfb3cd102791bc6af89bac4b6.
The review was spread across four different change-ids. Of course,
not all comments were addressed, now coverity complains too.
Change-Id: If5dbc1ae37120330ab192fb15eb4984afc84a7af
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch cleans up remaining uses of raw boolean Kconfig values I
could find by wrapping them with CONFIG(). The remaining naked config
value warnings in the code should all be false positives now (although
the process was semi-manual and involved some eyeballing so I may have
missed a few).
Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This is the second of 2 patches upgrading the SMBIOS interface to the latest 3.2
First patch is in mosys. Newer required fields are added to various types definitions
BUG=NONE
TEST=Boot to OS on GLK Sparky
Change-Id: Iab98e063874c9738e48a387cd91341d266391156
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Previously, the size of memory made for vboot_working_data
through the macro VBOOT2_WORK was always specified in each
individual memlayout file. However, there is effectively no
reason to provide this customizability -- the workbuf size
required for verifying firmware has never been more than 12K.
(This could potentially increase in the future if key sizes
or algorithms are changed, but this could be applied globally
rather than for each individual platform.)
This CL binds the VBOOT2_WORK macro to directly use the
VB2_WORKBUF_RECOMMENDED_DATA_SIZE constant as defined by vboot
API. Since the constant needs to be used in a linker script, we
may not include the full vboot API, and must instead directly
include the vb2_constants.h header.
BUG=b:124141368, b:124192753
TEST=Build locally for eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
CQ-DEPEND=CL:1504490
Change-Id: Id71a8ab2401efcc0194d48c8af9017fc90513cb8
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: If5c5ebacd103d7e1f09585cc4c52753b11ce84d0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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We were used to set the same values in the system and board tables.
We'll keep the mainboard values as defaults for the system tables,
so nothing changes unless somebody overrides the system table hooks.
Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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In the current state of the tree we do not utilise the
mechanism of having per-device overrides for PCI bus
ops.
This change effectively inlines all PCI config accessors
for ramstage as well.
Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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By changing the signatures we do not need to define
PCI config accessors separately for ramstage.
Change-Id: I9364cb34fe8127972c772516a0a0b1d281c5ed00
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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In case PCI_IO_CFG_EXT=n parameter 'reg' was not
properly truncated to 8 bits and it would overflow
to dev.fn part of the register.
A similar thing could happen with 'dev' but that
value originates from PCI_DEV() macro unlike 'reg'.
Change-Id: Id2888e07fc0f2b182b4633a747c1786e5c560678
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31847
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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By design only 'reg' parameter can have the two least-
significant bits set. As 'reg' is often a constant,
'0xCFC + (reg & 3)' resolves to an immediate value
already at buildtime, unlike (addr & 3) which depends
of a constant (but non-immediate) value of 'dev' in
ramstage.
Change-Id: I6e729fe800c92b1ce4994ad2b4203072fa75a958
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31754
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Sorting makes only sense if there are at least two entries available.
Change-Id: If40638bf1fe24dcff4b7839967445fb4218184f8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch fixes Coverity issue
CID 1399153: Uninitialized variables (UNINIT)
Change-Id: I736b532c687612912271317b8941e69f41af00ba
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31782
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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One could understand 'where' as bus, device, function
or register. Make it clear it is register.
Change-Id: I95d0330ba40510e48be70ca1d8f58aca66c8f695
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use fixed width types and const pointers for dev.
Change-Id: Ide3b70238479ad3e1869ed22aa4fa0f1ff8aa766
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Create the way of adding the discrete VGA OpROM at config UI (alternative to
./cbfstool ./cb.rom add -f vgabios_dgpu.bin -n pci1002,6663.rom -t optionrom )
DGPU options are accessible only if CONFIG_VGA_BIOS is enabled.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I0a7bf0fe95c833cf3df0c7cb20fc27b6ab218c5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch adds timestamp for "end of romstage" with postcar if platform
has selected postcar as dedicated stage.
If postcar stage doesn't exist then "end of romstage" timestamp will get
call while starting of ramstage as exist today.
TEST=It's been observed that "end of romstage" timestamp doesn't appear
in "cbmem -t" log when ramstage is not getting executed. As part of this fix
"end of romstage" timestamp is showing in "cbmem -t" log on Intel platform
where POSTCAR is a dedicated stage.
Change-Id: I17fd89296354b66a5538f85737c79145232593d3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch adds dedicated timestamp value for postcar stage.
TEST=Able to see "start of postcar" and "end of postcar" timestamp
while executing cbmem -t after booting to chrome console.
> cbmem -t
951:returning from FspMemoryInit 20,485,324 (20,103,067)
4:end of romstage 20,559,235 (73,910)
100:start of postcar 20,560,266 (1,031)
101:end of postcar 20,570,038 (9,772)
Change-Id: I084f66949667ad598f811d4233b4e639bc4c113e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Until now the TCPA log wasn't working correctly.
* Refactor TCPA log code.
* Add TCPA log dump fucntion.
* Make TCPA log available in bootblock.
* Fix TCPA log formatting.
* Add x86 and Cavium memory for early log.
Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Make GDT a separate table and don't reuse GDT descriptor as unused
first field of GDT.
Required for separate x86_64 GDT descriptor, pointing to the same
GDT.
Tested on qemu.
Change-Id: I513329b67d49ade1055bc07cf7b93ff2e0131e0b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31769
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fail builds if MRC blobs pool heap would get corrupted
by CAR relocatable data from coreboot proper.
Add runtime logging how much pool was required.
Change-Id: Ibc771b592b35d77be81fce87769314fe6bb84c87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31150
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reduces parameter passing and visibility of
parsing struct *dev to PCI bus:dev.fn.
Change-Id: Ie4232ca1db9cffdf21ed133143acfb7517577736
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ie32f1d43168c277be46cdbd7fbfa2445d9899689
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31699
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31698
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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