| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-09-13 | arch/x86/bootblock_crt0.S: Leverage eax in protected mode entry | Himanshu Sahdev aka CunningLearner |
| 2019-09-10 | AUTHORS: Move src/arch/x86 copyrights into AUTHORS file | Martin Roth |
| 2019-03-08 | coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) | Julius Werner |
| 2018-12-24 | soc/intel/quark: Drop BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP | Kyösti Mälkki |
| 2016-06-11 | arch/x86: Support "weak" BIST and timestamp save routines | Lee Leahy |
| 2016-06-11 | arch/x86: Add debug spinloop | Lee Leahy |
| 2016-06-09 | arch/x86: Enable SSE in bootblock_crt0.S | Lee Leahy |
| 2016-04-15 | bootblock_crt0: Use CR* macros from cpu/x86/cr.h | Furquan Shaikh |
| 2016-02-02 | arch/x86: Add second paragraph to license header | Martin Roth |
| 2016-01-30 | arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCK | Alexandru Gagniuc |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |