coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-09-26	riscv: Update register address	wxjstz
2016-12-20	riscv: enable counters via m[us]counteren	Ronald G. Minnich
2016-12-18	riscv: Add support for timer interrupts	Ronald G. Minnich
2016-11-20	riscv: map first 4GiB of physical address space	Ronald G. Minnich
2016-11-14	riscv: add a variable to control trap management	Ronald G. Minnich
2016-10-24	RISCV: Clean up the common architectural code	Ronald G. Minnich
2016-08-23	arch/riscv: Map the kernel space into RAM (2GiB+)	Jonathan Neuschäfer
2016-08-23	arch/riscv: Implement the SBI again	Jonathan Neuschäfer
2016-08-23	arch/riscv: Enable U-mode/S-mode counters (stime, etc.)	Jonathan Neuschäfer
2016-08-23	arch/riscv: Delegate exceptions to supervisor mode if appropriate	Jonathan Neuschäfer
2016-08-23	arch/riscv: Print the page table structure after construction	Jonathan Neuschäfer
2016-08-11	arch/riscv: Fix the page table setup code	Jonathan Neuschäfer
2016-08-11	arch/riscv: Update encoding.h and dependent files	Jonathan Neuschäfer
2016-08-02	arch/riscv: Add include/arch/barrier.h	Jonathan Neuschäfer
2016-07-28	arch/riscv: Only initialize virtual memory if it's available	Jonathan Neuschäfer
2016-07-18	arch/riscv: Remove enter_supervisor	Jonathan Neuschäfer
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-16	riscv-virtual-memory: move page tables into virtual address space	Thaminda Edirisooriya
2015-09-10	riscv-virtual-memory: Add virtual memory setup	Thaminda Edirisooriya