coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2024-08-20	arch/riscv: Remove ram probing	Maximilian Brune
2024-03-09	arch/riscv: Add SMP support for exception handler	Xiang Wang
2024-03-04	riscv/mb/qemu: fix DRAM probing	Philipp Hug
2023-04-21	arch/riscv/trap_handler.c: Use new names for CSR	Arthur Heymans
2023-02-09	treewide: Remove repeated words	Elyes Haouas
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-03-06	src/arch/riscv: Convert to SPDX license header	Patrick Georgi
2018-02-20	arch/riscv: Align trap_entry to 4 bytes, as required by spec	Jonathan Neuschäfer
2017-12-02	arch/riscv: Remove supervisor_trap_entry	Jonathan Neuschäfer
2017-12-02	arch/riscv: Return from trap_handler instead of jumping out	Jonathan Neuschäfer
2017-12-02	arch/riscv: Unify trap return	Jonathan Neuschäfer
2017-11-07	arch/riscv: Use a separate trap stack	Jonathan Neuschäfer
2017-11-07	arch/riscv: Drop mret workaround	Jonathan Neuschäfer
2017-01-16	riscv: get SBI calls to work	Ronald G. Minnich
2016-11-02	riscv: Add a bandaid for the new toolchain	Ronald G. Minnich
2016-08-15	arch/riscv: Set the stack pointer upon trap entry	Jonathan Neuschäfer
2016-07-18	arch/riscv: Change all eret instructions to .word 0x30200073 (mret)	Jonathan Neuschäfer
2016-06-12	arch/riscv/trap_util.S: Use "li" pseudo-instruction to load a constant	Jonathan Neuschäfer
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-15	riscv-trap-handling: Add functionality, prevent stack corruption	Thaminda Edirisooriya
2015-09-10	riscv-trap-handling: Add implementation for trap calls in riscv	Thaminda Edirisooriya
2015-08-26	riscv-trap-handling: Add preliminary trap handling for riscv	Thaminda Edirisooriya