coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2016-10-24	RISCV: Clean up the common architectural code	Ronald G. Minnich
2016-10-15	riscv: Clean up {qemu,spike}_util	Jonathan Neuschäfer
2016-10-07	RISCV: update the encoding.h file.	Ronald G. Minnich
2016-09-12	src/arch: Improve code formatting	Elyes HAOUAS
2016-08-23	arch/riscv: Add functions to read/write memory on behalf of supervisor/user mode	Jonathan Neuschäfer
2016-08-23	arch/riscv: Implement the SBI again	Jonathan Neuschäfer
2016-08-23	arch/riscv: Print the page table structure after construction	Jonathan Neuschäfer
2016-08-11	arch/riscv: Update encoding.h and dependent files	Jonathan Neuschäfer
2016-08-02	arch/riscv: Add include/arch/barrier.h	Jonathan Neuschäfer
2016-07-28	arch/riscv: Remove spinlock code from atomic.h	Jonathan Neuschäfer
2016-07-19	arch/riscv: Enable unaligned load handling	Jonathan Neuschäfer
2016-07-18	arch/riscv: Remove enter_supervisor	Jonathan Neuschäfer
2016-06-12	arch/riscv: copy read/write8/16/32 from x86	Jonathan Neuschäfer
2016-05-02	lib/coreboot_table: use the architecture dependent table size	Aaron Durbin
2016-05-02	arch: introduce architecture dependent common variables	Aaron Durbin
2016-02-11	arches: lib: add main_decl.h for main() declaration	Aaron Durbin
2016-02-11	arch/{arm64,riscv}: remove jmp_to_elf_entry() declaration	Aaron Durbin
2016-02-11	arch: remove stage_exit()	Aaron Durbin
2016-01-18	arch/riscv: Add missing license headers	Martin Roth
2015-11-11	arm/arm64: Generalize bootblock C entry point	Julius Werner
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-16	riscv-memlayout: fix existing memlayout issues, add sbi interface	Thaminda Edirisooriya
2015-09-15	riscv-trap-handling: Add functionality, prevent stack corruption	Thaminda Edirisooriya
2015-09-10	riscv-trap-handling: Add implementation for trap calls in riscv	Thaminda Edirisooriya
2015-09-10	riscv-virtual-memory: Add virtual memory setup	Thaminda Edirisooriya
2015-08-26	riscv-trap-handling: Add preliminary trap handling for riscv	Thaminda Edirisooriya
2015-08-09	riscv-spike: support for Spike emulation of riscv	Thaminda Edirisooriya
2015-06-08	Remove empty lines at end of file	Elyes HAOUAS
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-21	Unify byte order macros and clrsetbits	Julius Werner
2015-04-06	New mechanism to define SRAM/memory map with automatic bounds checking	Julius Werner
2015-02-02	src/arch/*/include/stdint.h: Provide definitions for bool type	Alexandru Gagniuc
2015-01-27	CBMEM: Tidy up CAR migration	Kyösti Mälkki
2015-01-27	CBMEM console: Fix CAR migration step	Kyösti Mälkki
2014-12-01	Add UCB RISCV support for architecture, soc, and emulation mainboard..	Ronald G. Minnich