coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-01-28	commonlib: Add commonlib/bsd	Julius Werner
2019-11-10	arch/riscv: Pass cbmem_top to ramstage via calling argument	Arthur Heymans
2019-11-06	arch/riscv: Use FDT from calling argument when using FIT	Arthur Heymans
2019-08-03	riscv: add support for OpenSBI	Xiang Wang
2019-06-23	riscv: workaround selfboot putting the coreboot table into prog_entry_arg	Xiang Wang
2019-04-23	src: Add missing include 'console.h'	Elyes HAOUAS
2019-02-02	riscv: Simplify payload handling	Xiang Wang
2019-01-16	buildsystem: Promote rules.h to default include	Kyösti Mälkki
2018-11-05	riscv: add support to block smp in each stage	Xiang Wang
2018-10-11	selfboot: remove bounce buffers	Ronald G. Minnich
2018-02-20	arch/riscv: Pass the bootrom-provided FDT to the payload	Jonathan Neuschäfer
2018-02-20	arch/riscv: Don't set up virtual memory	Jonathan Neuschäfer
2017-12-02	riscv: Remove config string support	Jonathan Neuschäfer
2016-11-12	riscv: start to use the configstring functions	Ronald G. Minnich
2016-10-24	RISCV: Clean up the common architectural code	Ronald G. Minnich
2016-07-14	arch/riscv: Unconditionally start payloads in machine mode	Jonathan Neuschäfer
2016-02-22	die() when attempting to use bounce buffer on non-i386.	Vladimir Serbinenko
2015-12-10	lib: remove assets infrastructure	Aaron Durbin
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-23	RISCV: modify arch_prog_run to handle payloads correctly.	Ronald G. Minnich
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-03	program loading: unify on struct prog	Aaron Durbin
2015-04-03	program loading: add prog_run() function	Aaron Durbin
2015-04-03	program loading: introduce struct prog	Aaron Durbin
2015-03-20	loaders: add program_loading.h header file	Aaron Durbin
2014-12-01	Add UCB RISCV support for architecture, soc, and emulation mainboard..	Ronald G. Minnich