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2019-07-19Documentation/code_of_conduct: Highlight the reporting processPatrick Georgi
Make it a separate section, emphasize that people should get support early, note that personal interaction and email are the two best ways to seek help. Change-Id: I8cb613fefe1a7b4db1ee948fb9927a38f0421011 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-19Documentation: Add Intel TXTPatrick Rudolph
Change-Id: I9e9606d0e4294ad3552ec3b3b44629f9e732d82b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-19Documentation/code_of_conduct: Assume the best as long as you canPatrick Georgi
"Always assume" is rather final and (in some readings) invalidates the need for the rest of the text. Change-Id: Ibf6f776494367d012ce69a64fa928c1dd4206c0e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-17mainboard/portwell/m107: Do initial mainboard commitFrans Hendriks
Initial support for Portwell PQ7-M107 (Q7) module. Code based on Intel Strago mainboard. BUG=N/A TEST=booting SeaBIOS and Linux 4.20 kernel on PQ7-M107 Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-16Doc/lessons/lesson1: Fix title consistencyAngel Pons
Make the title for lesson 1 match the format used for lesson 2 and the lessons index, for consistency purposes. Change-Id: I133d758ddf4974096cbf9f10ae96c148fc859efc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-15Documentation: Add FSP bugsPatrick Rudolph
As Intel doesn't even document known bugs add a list of FSP bugs here. Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-10soc/intel/block/cpu: remove unused USE_COREBOOT_NATIVE_MP_INITArthur Heymans
Only CONFIG_USE_INTEL_FSP_MP_INIT makes a difference whether native MP init is used or not. Also make USE_INTEL_FSP_MP_INIT mutually exclusive with USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI as this option requires coreboot to set up AP and publish PPI based on it. Change-Id: I65b80805d3cd7b66f8c9f878d3c741b98f24288d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33357 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02cpu/x86/pae/pgtbl: Add memset with PAEPatrick Rudolph
To clear all DRAM on x86_32, add a new method that uses PAE to access more than 32bit of address space. Add Documentation as well. Required for clearing all system memory as part of security API. Tested on wedge100s: Takes less than 2 seconds to clear 8GiB of DRAM. Tested on P8H61M-Pro: Takes less than 1 second to clear 4GiB of DRAM. Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-27mainboard: Add support for ASUS P8Z77-M PRO desktop mainboardVlado Cibic
Add support for ASUS P8Z77-M PRO desktop mainboard Working: - Tianocore and SeaBIOS boot - PS/2 keyboard and mouse - Audio - S3 Suspend, shutdown and reboot - USB2 / USB3 - Gigabit Ethernet - SATA3, SATA2 and eSATA - NVME - CPU Temp sensors - TPM - Native raminit and also MRC - PCIe GPU in all PCIe slots (16x/8x/4x) (linux) - Integrated graphics with both libgfxinit and Intel Video OpROM (all connectors VGA/DVI-D/HDMI) Signed-off-by: Vlado Cibic <vladocb@protonmail.com> Change-Id: I47d24ac8b236f929c3160f9a769b971d83710f9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/33328 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-27security: Add memory subfolderPatrick Rudolph
Add files to introduce a memory clearing framework. Introduce Kconfig PLATFORM_HAS_DRAM_CLEAR that is to be selected by platforms, that are able to clear all DRAM. Introduce Kconfig SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT that is user selectable to always clear DRAM on non S3 boot. The function security_clear_dram_request tells the calling platform when to wipe all DRAM. Will be extended by TEE frameworks. Add Documentation for the new security API. Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2019-06-24Documentation: Add PC Engines apu2Piotr Kleinschmidt
Describe how to run coreboot on the PC Engines apu2 mainboard. Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-24Documentation: Add PC Engines apu1Piotr Kleinschmidt
Describe how to run coreboot on the PC Engines apu1 mainboard. Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-21drivers/ipmi: Add chip opsPatrick Rudolph
* Add chips ops for IPMI KCS. * Get IPMI version over KCS. * Generates ACPI SPMI table for IPMI KCS. * Generates SMBIOS type 38 for IPMI KCS. * Generates ACPI SPMI device for IPMI KCS on LPC device. * Add documentation To use this driver on BMC that support KCS on I/O: 1. Add an entry to the devicetree.cb: chip drivers/ipmi device pnp ca2.0 on end # IPMI KCS end 2. Select IPMI_KCS in Kconfig. 3. (Optional) enable LPC I/O decode for the given address. Tested on Wedge100s. Change-Id: I73cbd2058ccdc5395baf244f31345a85eb0047d7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-21Documentatioan: update stage handoff protocolXiang Wang
Change-Id: I170fc16675c2701f6ea133cfce6e5fabdfb0e8d3 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-06-17doc/mb/upsquared: Add documentationFelix Singer
This patch adds documentation about the UP² mainboard and the IFWI used by Apollolake platform. Change-Id: Ic708ddbd2616eee4e5ec2740b3eac18b408bde38 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-13Documentation/soc/amd: Add Family 17hMarshall Dawson
Begin a directory for AMD soc devices and add an explanation of how Family 17h works. Newer AMD systems use a unique paradign for initializing the x86 processors. Change-Id: I7bd8649996add80747f6a60b9dfd35a94a560be1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-09Documentation: Add display panel specificsDaniel Maslowski
Change-Id: If1a393578556d51499c700b68187034830d19215 Signed-off-by: Daniel Maslowski <daniel.maslowski@img.ly> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-06mb/hp: Add Z220 SFF workstationPatrick Rudolph
* Add initial board commit based on HP8200 SFF. * Add documentation. * Serial and PCIe slot are working. Tested on HP Z220. Change-Id: I75987a7ea9a008a64281f0d5ab27e5148d36a4ec Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33207 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-05mainboard/facebook/fbg1701: Do initial mainboard commitFrans Hendriks
Initial support for Facebook FBG-1701 system. coreboot implementation based on Intel Strago mainboard. Configure 'Onboard memory manufacturer' which must match HW. BUG=N/A TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701 Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-04kconfig: Drop IS_ENABLED() macroNico Huber
We keep its definition in libpayload, though, to maintain compatibility with existing payload code. For now. Change-Id: I8fc0d0136ba2316ef393c5c17f2b3ac3a9c6328d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-04vendorcode/eltan: Add vendor code for measured and verified bootFrans Hendriks
This patch contains the general files for the vendorcode/eltan that has been uploaded recently: - Add eltan directory to vendorcode. - Add documentation about the support in the vendorcode directories. - Add the Makefile.inc and Kconfig for the vendorcode/eltan and vendorcode/eltan/security. BUG=N/A TEST=Created verified binary and verify logging on Portwell PQ-M107 Change-Id: Ic1d5a21d40b6a31886777e8e9fe7b28c860f1a80 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-30mb/roda/rk9: Document flash headerNico Huber
Change-Id: I5bd131635340ffa0c6b8979fc8e263fc5f09fdc5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-29Documentation: Warn about ME cleaner on Sandy BridgePatrick Rudolph
Document known issues with 'disabled' ME. Change-Id: I364f3ed49341523c781eb2f3b41e866f33632a7e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32889 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-25Documentation: Add HP EliteBook 8760wIru Cai
Also add the HP EliteBook document from wiki. Change-Id: I189db9c279705af53d82af66d0c2e8afb6f84d73 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30950 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-23mb/asus/p8h61-m_pro: Add small fixesPatrick Rudolph
* Add VBT * Configure OnBoard NIC * Add documentation Change-Id: Iad739b4e1dacb41f5f63247150951df7013bbf0c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-22post_code: add post code for video initialization failureKeith Short
Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon initialization returns an error when graphics was also initialized. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22post_code: add post code for hardware initialization failureKeith Short
Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to detect or initialize a required hardware component. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22post_code: add post code for memory errorKeith Short
Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails to initialize RAM. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22post_code: add post code for invalid vendor binaryKeith Short
Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails to locate or validate a vendor supplied binary. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-22post_code: add post code for critical CBFS failuresKeith Short
Add a new post code POST_INVALID_CBFS, used when coreboot fails to locate or validate a resource that is stored in CBFS. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: If1c8b92889040f9acd6250f847db02626809a987 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-22post_code: add post code for failure to load next stageKeith Short
Add a new post code, POST_INVALID_ROM, used when coreboot fails to locate or validate a resource that is stored in ROM. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ie6de6590595d8fcdc57ad156237fffa03d5ead38 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-22mb/up/squared: Add mainboardFelix Singer
Works: - bootblock, romstage, ramstage - Serial console UART0, UART1 - SPI flash console - iGPU init with libgfxinit - LAN1, LAN2 - USB2, USB3 - HDMI, DisplayPort - eMMC - flashing with flashrom externally WIP: - Documentation - VGA For some reason Seabios can not find the CBFS region and therefore it can't load seavgabios, but generally it is working as soon as Linux is booted. - ACPI Works not: - Devices needs proper configuration - Seabios can't find CBFS region Untested: - GPIO pin header - 60 pin EXHAT - Camera interface - MIPI-CSI2 2-lane (2MP) - MIPI-CSI2 4-lane (8MP) - SATA3 - USB3 OTG - embedded DisplayPort - M.2 slot - mini PCIe - flashing with flashrom internally using Linux Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-21Documentation: Add RotunduPatrick Rudolph
Add information about flash and programming header. Change-Id: If34016e20dd580f92695bef5b67dd0c282b0b421 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-16Documentation/lessons: Tidy up lesson 2Jacob Garber
- The link to create an account is now "Sign in" and not "Register" - Use monospace formatting for terminal commands and file names - Properly escape less-than and greater-than - Correct the 'make lint' example command - Reformat example commit messages - Add formatting for website links - Other whitespace fixes Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I9931bef8c30387d1c08b59973d6de9b5c0419814 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-05-15Documentation/lessons/lesson2.md: Add reminder to check username setAlan Green
If username is not set, then the ssh option is not available. This was initially confusing for me. Signed-off-by: Alan Green <avg@google.com> Change-Id: I731c29a1daa9f8c298710471c7d1fe758b059d08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-05-08Documentation: Convert vboot to markdownPatrick Rudolph
Convert the HTML document to markdown and place it under security section. Change-Id: I212c6d0c977fd6772371ff6676478d48cc215d6e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32610 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-06Documentation: Add MSI MS-7707Bluemax
Change-Id: Iba38bda9becba9fcffb51afc4756023659f092ef Signed-off-by: Max Blau <tripleshiftone@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-30Documentation: Add FITPatrick Rudolph
Describe the Firmware Interface Table and reference useful documentation. Change-Id: I00abc1fd13be7b48d56ba8cb65d2542ed07f9017 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-28Documentation/northbridge/intel/haswell/mrc.bin.md: add SPD addressesDaniel Maslowski
Change-Id: I8bf81637f582373d9bba1d47fe5205d459151f3e Signed-off-by: Daniel Maslowski <dan@orangecms.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-23hifive-unleashed: update documentation to match current statePhilipp Hug
Signed-off-by: Philipp Hug <philipp@hug.cx> Change-Id: I3f1b7dd4ef52a64c9a222f2d5cffe2b73806fe4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-19Documentation: Add small fixesPatrick Rudolph
* Remove empty security.md * Remove second H1 header from lib/index.md * Move two documents in appropriate subfolders * Fix file path * Drop document overview Change-Id: I0e9df6203e82003c01b84967ea6bd779d7583fef Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-11Documentation: Explain FMAP and FMDHung-Te Lin
The Flashmap (FMAP) was not clearly documented. The new flashmap.md explains where to find more details about that and how / why it was used in coreboot. Also explained what is FMD and how to use it (based on original README.fmaptool). BUG=None TEST=None (only documentation) Change-Id: Ia389e56c632096d7c905ed221fd4f140dec382e6 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11Documentation: Make lenovo codenames human readablePatrick Rudolph
Use rst parser to convert the csv to markdown tables. Change-Id: I7fd61bd7a4e8818901520311332ae4027e7a7d02 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-11Documentation: Allow the use of CSVPatrick Rudolph
Allow the use of CSV files if properly referenced from markdown. Sphinx will parse the file and create a human readable table, allowing easy integration of autogenerated files. Change-Id: I6fa13acf67ff1c6c9e3985054405c5446808da03 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-11Documentation: Add coreboot architecturePatrick Rudolph
Describe the coreboot stages, given a short introduction what is done and add a chart for coreboot's vs EDK II bootflow as well as the source for the SVG. TODO: Describe stages in detail in a separate commit. Change-Id: I98cb61b1d0d29ac9d03f5ef3644d51a8e14bad74 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-10Doc/mb/asrock/h110m: update info about PEGMaxim Polyakov
- Now there is no need to additionally configure the FSP before building; - PEG works with high link speed 8 GT/s (Gen 3); - external GPU supported, but dynamic switching between iGPU and PEG is not yet supported. Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31949 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08Docs/kconfig: Update to use CONFIG()Nico Huber
Change-Id: Ica7b601d1c9c3bcf39b8b805d48e969f8a944927 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-06Doc/mb/asrock/h110m: Fix the linksMaxim Polyakov
Change-Id: I7b925518416a4268037efac9060ef911e4ae74cd Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-04Documentation/gfx/libgfxinit.md: Align line breaksPhilipp Bartsch
Remove word splitting '-' at line breaks, since they show up within the lines of the rendered html. Change-Id: Ifbd43628f60057a0666fe221de1fe85f0a29cd2d Signed-off-by: Philipp Bartsch <phil@grmr.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32147 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04Documentation: Fix invisible textPhilipp Bartsch
Encapsulate angled brackets in backticks '<filepath>' to make text visible in html rendering. Change-Id: I1ab926956c909aa3cd2fd92068ccb7b800dd1d4a Signed-off-by: Philipp Bartsch <phil@grmr.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32146 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04Documentation: Fix broken linkPhilipp Bartsch
Change-Id: Idd08bc49fb7bf3770e03f747d97d90aacc12eada Signed-off-by: Philipp Bartsch <phil@grmr.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-26Documentation/soc/intel: Add MP Initialization documentSubrata Banik
This patch provides documentation for MP initialization option available in coreboot. Change-Id: I055808e2ddf03663e1ec5d3d423054d1caa911cb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-19Documentation/soc/intel/fsp: Move mp_service_ppi document in corrct directorySubrata Banik
This patch moves mp service ppi document from icelake/MultiProcesorInit.md to ppi/mp_service_ppi.c. Change-Id: I1bbaeb2644f219b5a1fda0c7c4b594184d53958c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31840 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-19mainboard: Add ASRock H110M-DVSMaxim Polyakov
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard. Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit. Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio. TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation. Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload. Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-15Revert "Documentation: Our coding style now allows 80 + 2*8 columns in a line"Julius Werner
This reverts commit b3a8cc54dbaf833c590a56f912209a5632b71f49. This change was submitted under the incorrect assumption that there was agreement on a coding style change. There wasn't, so while the issue is under discussion we should revert to the previous status quo. Change-Id: I37a5585764346af11a98bdf58c810dd3cf5bfe40 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-14Documentation: Add Asus F2A85-MBalazs Vinarz
Change-Id: I4d195f4833ba71fdc559815cafb0f5d0d254e897 Signed-off-by: Balazs Vinarz <vinibali1@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-12Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPISubrata Banik
Some new feature added into FSP specification to perform dispatching of external PPI service from boot firmware (coreboot) to FSP. Change-Id: Iaf6b54ccd27e21860539bb2a9966054fdb027108 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31839 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-12Documentation/soc/intel: Add documentation for Intel FSPSubrata Banik
This patch combines open source documentation for Intel FSP specification. Change-Id: I3a8bc0198a1e01ec019139b728834713978501ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31838 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-09Docs/project_ideas: Add a "parse SerialICE traces" project ideaPatrick Georgi
Change-Id: I696811ff93948358f03ff617d294ecc40bd4c746 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-09Docs/project_ideas: Add a stub for Ghidra integrationPatrick Georgi
It may be useful to have a common, easily available toolbench for firmware analysis and Ghidra looks promising. Change-Id: I56d0ff875bb939f6d31f088232f8a6fd168abbb6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31806 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08Docs/project_ideas: Expand "toolchain" project descriptionPatrick Georgi
One-off packages do us little good, we need to be able to automate building them. Change-Id: Idd9b6b231435ea9d6e946c7ccaa71174b497742c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31804 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08Documentation: Our coding style now allows 80 + 2*8 columns in a linePatrick Georgi
Update the document to match clang-format and checkpatch formally, and provide a rationale. Change-Id: I597a27d4e22d07e033b36f0dceb554ac1d8d5789 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-07Docs/project_ideas: Add coverity scan cleanup projectPatrick Georgi
Change-Id: I16d9a7f7088254c5c207adc9299a8525bf38199f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-07Documentation: Add myself as potential mentor for QEMU targetsPatrick Georgi
Change-Id: I11df0283f14ae03243247fe9377754b216df0442 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31556 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07security/tpm: Fix TCPA log featurePhilipp Deppenwiese
Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-25security/vboot: Add measured boot modePhilipp Deppenwiese
* Introduce a measured boot mode into vboot. * Add hook for stage measurements in prog_loader and cbfs. * Implement and hook-up CRTM in vboot and check for suspend. Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/29547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-20Documentation: take the sting out of the requirementsPatrick Georgi
The requirements read a bit as if we only encourage coreboot experts to try to take on these projects. These requirements should be understood as "this is what you'll need to learn", hopefully guiding interested people in picking a project that suits their interests. Change-Id: I43b6e2e0df5f00e1ded8d14cee8c771e3f595ce7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31480 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-20Documentation: Add Clang support to project ideasPatrick Georgi
Change-Id: Iaccb5ca5606b83a4b37930b4399ddcf9eddd494b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-19Documentation: Add past talks to conferences pagePatrick Georgi
Change-Id: I2b8a0ebda3c8fa7d1777a6f0628fd99d73a0d341 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-18Documentation: add Skulls to the list of distributionsMartin Kepplinger
There seem to be enough users of the Skulls images to have the project listed in our docs. Change-Id: I5a8f24005fec87d53af7ad53370cb6a704378622 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/31463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-18Documentation/lesson1: Update references to compiler packagesNico Huber
Change-Id: Ie9daa70c56552cccfe28e9a4903f87d43221375e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-02-17Documentation: Add broader payload coverage to project ideasPatrick Georgi
A couple people discussed recently how it's a shame that on some architectures we can bring up a device but then have nothing to do with it afterwards. Having payloads to choose from would help a lot there. Change-Id: Ia66f22947d09afe3076cc2ee12f5b652fe80fc3a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-15Documentation: Add KASAN to the project ideas listWerner Zeh
Adding the Kernel Address Sanitizer feature to coreboot would help to find bugs. Change-Id: If00010e81147ec50e037678230df17c6888e40a2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/31414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-11Documentation: remove the upcoming events chapter from the conferences pageMartin Kepplinger
I think our docs inside of the codebase might not be the ideal place to announce future events. First, they might be scheduled so shortly before the conference that the change, if at all done, would barely make it to the repo and the web. Also, _if_ really maintained, it would churn the docs unnessesarily. But, I doubt that anyone of us would want to maintain this here at all. Lastly, I think that nobody out there would _look for_ upcoming events in coreboot's documentation. We have bigger problems in the Documentation directory than this :) Change-Id: I918e17a427405a05722c6e0d61dc422f94cac809 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/31266 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-11Documentation: add the most recent talks to the conferences pageMartin Kepplinger
Add Philipps great 35c3 talk and Davids and Andreas fosdem talk to the conferences page. linuxboot adds those to their website too but they can't be linked to too often :) Change-Id: I1e7ce078020dc5e9c9d9d47210c70ee16ef2f82e Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/31265 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-11Documentation: add link to chromebookdb.com to distribution pageMartin Kepplinger
As suggested by Philipp, let's add this link. Change-Id: I6ff21f37a04dc5a9c3db1ff7ac9a786fb0b51211 Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/31263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-11Documentation: add the Heads project to the list of distributionsMartin Kepplinger
As this is a unique, actively maintained project, we should probably point there too. The text is just copied parts of the http://osresearch.net/ website. Change-Id: Ib2a8e4b28bc94c5dc6a1ae9388f96ad2c502ccab Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/c/31257 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-07Documentation: Mention PC Engines as ships-with-coreboot hardwarePatrick Georgi
Change-Id: I9d57abcff9c2472cc58b7fbca00441cd38a7f1a1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
2019-02-06Documentation: update/improve distribution listingMatt DeVillier
- improve descriptions of Purism and ChromeOS hardware - add entry for Libretrend Librebox - improve description of Mr Chromebox and John Lewis' 3rd party ChromeOS firmware offerings Change-Id: I66bd1a3701091e499d88738a7c06126de66e58ff Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/31252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-06Documentation: Add Project Ideas documentPatrick Georgi
We already had such a page on the wiki, but it's outdated and the wiki is supposed to go the way of the dodo anyway. This is a fresh start to make sure that all ideas we're coming up with are still current and that there are mentors willing to support them. Change-Id: Idd68f845930bd37a2293969b9a153cf584d6d15f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30972 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05Documentation: describe coreboot on the dev site's landing pagePatrick Georgi
Get some content on the documentation site's front page. Change-Id: I7f36234ef783e041a44590858bb75a69b96ee668 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-05Documentation: Describe our ecosystemPatrick Georgi
Neither payloads nor distributors are an integral part of the coreboot source tree, but they're very important parts of the coreboot ecosystems, so add some descriptions. Change-Id: Id64744c252b6b78c4811fbded48c441ef486ad94 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-05Documentation: Allow passing arguments into make livesphinxPatrick Georgi
It's what the doc.coreboot.org docker container is running and when using its livehtml feature, it listens at localhost, which isn't always desirable. With `docker run -e SPHINXOPTS="-H $localip" ...` it now listens at localip, which is more flexible. Change-Id: Ia0614e57458c32169f6d614783366025e9c814b3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31128 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-30Documentation: Add some description of our communal placesPatrick Georgi
Change-Id: Iede98359c22aefbfd5725a5e7cd661ef18d7284e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-30Documentation: Add coding styleArthur Heymans
This is the old wiki page https://www.coreboot.org/Coding_Style coverted from mediawiki to markdown. Change-Id: Id56a8b7500121c4d9c18bc0b6bbc2c05402268dc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-28Documentation: Fix up list of releasesPatrick Georgi
4.9 was still marked as "upcoming" and 4.10 was missing altogether, leading to a sphinx warning. Change-Id: I008d546715b7841eb9f325a6f698380dd4c1a7c2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/31126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-26mb/qemu-riscv: update to match current qemu versionPhilipp Hug
Boots again to payload not found on qemu. Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/30554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-17mb/lenovo/x220: Add x1 as a variantBill XIE
ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a clone of X220, with additional USB3 controller on pci-e (as i7 variant of x220), and a powered ESATA port wired to ata4 (Linux' annotation). Documentation added. Tested: - CPU i5-2520M - Slotted DIMM 8GiB - Camera - Mini pci-e on wlan slot - Msata on wwan slot - On board SDHCI connected to pci-e - USB3 controller connected to pci-e - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from SeaBIOS, or Linux payload (Heads) Not tested: - Fingerprint reader on USB2 - Onboard USB2 interfaces (wlan slot, wwan slot) Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/c/29434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-14[RFC]util/checklist: Remove this functionalityArthur Heymans
It was only hooked up for galileo board when using the obsolete FSP1.1. I don't see how it can be useful... Change-Id: Ifd7cbd664cfa3b729a11c885134fd9b5de62a96c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30691 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-09Doc/mb/asrock/h81m-hds: Link to the Haswell documentationTristan Corrick
Change-Id: I50da6da6c1321f8d9d94b11d19187a8c22709705 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-09Doc/mb/supermicro/x10slm-f: Remove PCIe issue that has been fixedTristan Corrick
The issue in question was resolved with commit 334be3289d6c ("nb/intel/haswell: Add support for PEG"). Also add a link to the known issues for Haswell, which has some information on PCIe. Change-Id: Icc3061b60893394e3d537d3b86f4ac748cec2eb4 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-08Documentation/releases: Note the disappearance of device_tPatrick Georgi
That was truly a huge task. Change-Id: Ifd79aaf005bf39744bd4fd930ba2441f966ec0b3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-08Documentation: Add 4.10 release notes templatePatrick Georgi
Change-Id: Ibb7aab2367c379bbf7ab93a41ce06095916d0f95 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-07Documentation/gerrit: Update parts about WIP and draft commitsPatrick Georgi
Gerrit dropped the "draft" concept and replaced it with private commits and work-in-progress commits, options that can be used independently from each other. Change-Id: I6abe267c2091c750fc234057be3a4e62adb59c4c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04Documentation: Update 4.9 release notesPatrick Georgi
Change-Id: Ib1057541dc0decd98921f3c84de3c08f10cd802e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30344 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03Doc/mb/asrock/h81m-hds: Remove PCIe issue that has been fixedTristan Corrick
PCIe graphics for display output still doesn't work, but that is now listed in the Haswell-specific documentation. Change-Id: I28c50db353b2b965eb847b379d9e1944cb720c77 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-03Doc/nb/intel/haswell: Add a list of known issuesTristan Corrick
Change-Id: If0339831550f6c70e8056f78633e9a402f35a793 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30455 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-03Doc/nb/intel/haswell: Mention util/chromeos as a way to get mrc.binTristan Corrick
Change-Id: Ic099d0f052db5ef6a699d54b26028bae2fae4770 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-29mainboard: Add Supermicro X10SLM+-FTristan Corrick
This board runs well with coreboot. The documentation part of this commit lists what works and what doesn't. Tested with GRUB 2.02 as a payload, loading SeaBIOS 1.12.0 which then boots FreeBSD 11.2. It has also been tested with GRUB directly booting Debian GNU/Linux 9.6 (kernel 4.9). Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-24Documentation/nb/intel: Add Haswell documentationTristan Corrick
At the moment, this just gives some details on the MRC. Change-Id: I84e8ca2543b2e19b84a24f7d7032a4aedb6e9272 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-29 07:46:37 +0000